Lab8

module Lab8(
                input CLOCK_50,
                input [3:0] KEY,
                output reg [1:0] LEDR
);
    reg[2:0] prev1, prev2, prev3, temp1, temp2;  //prev is the last key pressed.  000 if A, 001 B, 010 C, 011 D, 111 null
    wire a, b, c, d;
    reg[0:0] A, B, C, D;

    oneshot k0(KEY[0], CLOCK_50, a);
    oneshot k1(KEY[1], CLOCK_50, b);
    oneshot k2(KEY[2], CLOCK_50, c);
    oneshot k3(KEY[3], CLOCK_50, d);

    initial begin
        prev1 = 3'b111;
        prev2 = 3'b111;
        prev3 = 3'b111;
        LEDR[0] = 1'b1;
        LEDR[1] = 1'b0;
    end
    always @(posedge CLOCK_50) begin
        if (prev3 == 3'b000 & prev2 == 3'b001 & prev1 == 3'b000 & LEDR[1] == 1'b0) begin
            LEDR[0] = 0;
        end
        else if (prev3 != 3'b111 & prev2 != 3'b111 & prev1 != 3'b111 & LEDR[1] == 1'b0) begin
            LEDR[0] = 1;
            LEDR[1] = 1;
        end
        if (LEDR[1] == 1'b1 & prev2 == 3'b000 & prev1 == 3'b000 & D == 1'b1) begin
            LEDR[1] = 0;
        end
        if (A) begin
            prev1 <= 000;
            prev2 <= prev1;
            prev3 <= prev2;
        end
        if (B) begin
            prev1 <= 001;
            prev2 <= prev1;
            prev3 <= prev2;
        end
        if (C) begin
            prev1 <= 010;
            prev2 <= prev1;
            prev3 <= prev2;
        end
        if (D) begin
            prev1 <= 111;
            prev2 <= 111;
            prev3 <= 111;
            LEDR[0] = 1;
        end
        A = a;
        B = b;
        C = c;
        D = d;
    end
endmodule


module oneshot(sin, clock, sout);
    input sin, clock;
    output sout;
    reg sout, q;

    always @(posedge sin or posedge sout) begin
        if(sout)
            q <= 0;
        else
            q <= 1;
    end
    always @(posedge clock) begin
        sout <= q;
    end
endmodule