`timescale 10ns / 1ns

typedef enum
    {   ParitySpace = 'b00,
        ParityMark  = 'b11,
        ParityEven  = 'b10,
        ParityOdd   = 'b01}
    ParityType;

module SerialTX(
    input wire iClockP,             // posedge triggered
    input wire iResetP,             // posedge triggered
    input wire [2:0] iDataBits,     // 0 = 1, 1 = 2 ... 7 = 8
    input wire iStopBits,           // 0 = 1, 1 = 2
    input wire iParityEnable,       // 0 - off, 1 - on
    input wire [1:0] iParityType,   // 00 - space, 11 - mark, 10 - even, 01 - odd
    input wire [7:0] iDataFeed,     // data to send
    input wire iSend,
    output wire oReady,
    output bit oTX);

    bit [2:0] rDataBits;
    bit rStopBits;
    bit rParityEnable;
    bit [1:0] rParityType;
    bit [7:0] rDataFeed;
    bit rParityBit;

    enum bit [3:0] { StartState, DataState, ParityState, StopState, IdleState } rTXState;
    bit [2:0] rBitsSent;

    assign oReady = (rTXState == IdleState);

    always @(posedge iClockP, posedge iResetP, posedge iSend)
    begin
        if (iResetP != '0) begin
            rDataBits       <= iDataBits;
            rStopBits       <= iStopBits;
            rParityEnable   <= iParityEnable;
            rParityType     <= iParityType;
            rTXState        <= IdleState;
            rBitsSent       <= 'd0;
            rParityBit      <= 'd1;
            oTX             <= 'd1;
        end
        else begin
            case (rTXState)
            StartState:     StartStateTask();
            DataState:      DataStateTask();
            ParityState:    ParityStateTask();
            StopState:      StopStateTask();
            IdleState:      IdleStateTask();
            default:        IdleStateTask();
            endcase;
        end
    end

    task IdleStateTask();
        if (iSend != '0) begin
            rTXState <= StartState;
            rDataFeed <= iDataFeed;
            rBitsSent <= rDataBits;
            oTX <= '0;
        end
    endtask;

    task StartStateTask();
        rTXState <= DataState;
        oTX <= rDataFeed[rBitsSent];
        rBitsSent <= rBitsSent - 3'd1;
    endtask;

    task DataStateTask();
        oTX <= rDataFeed[rBitsSent];
        if (rBitsSent != 3'd0) begin
            rBitsSent <= rBitsSent - 3'd1;
        end
        else begin
            if (rParityEnable != '0) begin
                rTXState <= ParityState;
                case (rParityType)
                ParityOdd:      oTX <= rParityBit;
                ParityEven:     oTX <= ~rParityBit;
                ParityMark:     oTX <= '1;
                ParitySpace:    oTX <= '0;
                endcase;
            end
            else begin
                rTXState <= StopState;
                oTX <= '1;
            end
            rBitsSent <= 3'd1 + rStopBits;
        end
    endtask;

    task ParityStateTask();
        rTXState <= StopState;
    endtask;

    task StopStateTask();
        if (rBitsSent == 3'd0) begin
            rTXState <= IdleState;
        end
        rBitsSent <= rBitsSent - 3'd1;
    endtask;

endmodule