library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity registar_tb is
end registar_tb;

architecture Test_tb of registar_tb is
 signal sARITH : std_logic;
 signal sLOAD : std_logic;
 signal sDATA: std_logic_vector(7 downto 0);
 signal sSHL : std_logic;
 signal sSHR : std_logic;
 signal sCLK : std_logic;
 signal sRST: std_logic;
 signal sSHREG : std_logic_vector(7 downto 0);


 component registar
 port(
		iARITH: in std_logic;
		iLOAD: in std_logic;
		iDATA: in std_logic_vector(7 downto 0);
		iSHL: in std_logic;
		iSHR: in std_logic;
		iCLK: in std_logic;
		iRST: in std_logic;
		oSHREG: out std_logic_vector(7 downto 0)
		);
 end component;

 constant iCLK_PERIOD: time:=10ns;


begin  -- instanciranje i mapiranje glavnih portova i signala
 uut : registar port map (
 iARITH => sARITH,
 iLOAD => sLOAD,
 iDATA => sDATA,
 iSHL=>sSHL,
 iSHR=>sSHR,
 iCLK=>sCLK,
 iRST=>sRST,
 oSHREG=>sSHREG
 );

 iCLK_process: process
	begin
	sCLK<='0';
	wait for iCLK_period/2;
	sCLK<='1';
	wait for iCLK_period/2;


 end process;


 stimulus : process
 begin

 --sEN<='1';
 sRST <= '1';
 wait for 5.25 * iCLK_period;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='1';
 sSHL<='1';
 sSHR<='0';
wait for 100 ns;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='0';
 sSHL<='1';
 sSHR<='0';
wait for 100 ns;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='1';
 sSHL<='0';
 sSHR<='1';
wait for 100 ns;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='0';
 sSHL<='0';
 sSHR<='1';
wait for 100 ns;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='1';
 sSHL<='1';
 sSHR<='1';
wait for 100 ns;

 sDATA<="11010011";
 sRST<='0';
 sLOAD<='0';
 sARITH<='1';
 sSHL<='0';
 sSHR<='0';
wait for 100 ns;



sRST<='0';
sLOAD<='1';


  wait;
 end process stimulus;
end architecture;