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May 23rd, 2019
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  1. COMPONENT REGISTER_ID_EX
  2. GENERIC (
  3. N : INTEGER := 16;
  4. ADDRESSSIZE : INTEGER := 3
  5. );
  6. PORT (
  7. CLOCK, ISEOR, WASJUMPOUT, ISJUMP, ISJR, ISBRANCH, ISR, ISMFPC, ISLW, ISSW, ISREADDIGIT, ISPRINTDIGIT : IN STD_LOGIC;
  8. ALUFUNC : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  9. R1REG , R2REG , IMMEDIATE16 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
  10. R2AD, R1AD : IN STD_LOGIC_VECTOR(ADDRESSSIZE-1 DOWNTO 0);
  11. JUMPSHORTADDR : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
  12. ---------------------------------------------------------------------
  13. ISEOR_IDEX, WASJUMPOUT_IDEX, ISJUMP_IDEX, ISJR_IDEX , ISBRANCH_IDEX, ISR_IDEX, ISMFPC_IDEX, ISLW_IDEX, ISSW_IDEX, ISREADDIGIT_IDEX, ISPRINTDIGIT_IDEX : OUT STD_LOGIC;
  14. ALUFUNC_IDEX : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  15. R1REG_IDEX , R2REG_IDEX , IMMEDIATE16_IDEX : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
  16. R2AD_IDEX , R1AD_IDEX : OUT STD_LOGIC_VECTOR(ADDRESSSIZE-1 DOWNTO 0);
  17. JUMPSHORTADDR_IDEX : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  18. );
  19. END COMPONENT;
  20.  
  21. LIBRARY IEEE;
  22. USE IEEE.STD_LOGIC_1164.ALL;
  23. USE IEEE.NUMERIC_STD.ALL;
  24.  
  25. ENTITY REGISTER_ID_EX IS
  26. GENERIC (
  27. N : INTEGER := 16;
  28. ADDRESSSIZE : INTEGER := 3
  29. );
  30. PORT (
  31. CLOCK, ISEOR, WASJUMPOUT, ISJUMP, ISJR, ISBRANCH, ISR, ISMFPC, ISLW, ISSW, ISREADDIGIT, ISPRINTDIGIT : IN STD_LOGIC;
  32. ALUFUNC : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  33. R1REG , R2REG , IMMEDIATE16 : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
  34. R2AD, R1AD : IN STD_LOGIC_VECTOR(ADDRESSSIZE-1 DOWNTO 0);
  35. JUMPSHORTADDR : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
  36. ---------------------------------------------------------------------
  37. ISEOR_IDEX, WASJUMPOUT_IDEX, ISJUMP_IDEX, ISJR_IDEX , ISBRANCH_IDEX, ISR_IDEX, ISMFPC_IDEX, ISLW_IDEX, ISSW_IDEX, ISREADDIGIT_IDEX, ISPRINTDIGIT_IDEX : OUT STD_LOGIC;
  38. ALUFUNC_IDEX : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  39. R1REG_IDEX , R2REG_IDEX , IMMEDIATE16_IDEX : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
  40. R2AD_IDEX , R1AD_IDEX : OUT STD_LOGIC_VECTOR(ADDRESSSIZE-1 DOWNTO 0);
  41. JUMPSHORTADDR_IDEX : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
  42. );
  43. END REGISTER_ID_EX;
  44.  
  45. ARCHITECTURE BEHAVIOR OF REGISTER_ID_EX IS
  46. BEGIN
  47.  
  48. PC: PROCESS(CLOCK)
  49. BEGIN
  50. IF CLOCK='1' THEN
  51. ISEOR_IDEX <= ISEOR;
  52. WASJUMPOUT_IDEX <= WASJUMPOUT;
  53. ISJUMP_IDEX <= ISJUMP;
  54. ISJR_IDEX <= ISJR;
  55. ISBRANCH_IDEX <= ISBRANCH;
  56. ISR_IDEX <= ISR;
  57. ISMFPC_IDEX <= ISMFPC;
  58. ALUFUNC_IDEX <= ALUFUNC;
  59. R1REG_IDEX <= R1REG;
  60. R2REG_IDEX <= R2REG;
  61. IMMEDIATE16_IDEX <= IMMEDIATE16;
  62. R2AD_IDEX <= R2AD;
  63. R1AD_IDEX <= R1AD;
  64. JUMPSHORTADDR_IDEX <= JUMPSHORTADDR;
  65. END IF;
  66. END PROCESS PC;
  67.  
  68. END ARCHITECTURE BEHAVIOR;
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