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  1. #include <Wire.h>
  2. #include <SPI.h>
  3.  
  4. #define address  (0x42 >> 1)
  5.  
  6. #include <Wire.h>
  7. #include <SPI.h>
  8.  
  9. #define address  (0x42 >> 1)
  10.  
  11. #define vga   0
  12. #define qvga  1
  13. #define qqvga   2
  14. #define yuv422  0
  15. #define rgb565  1
  16. #define bayerRGB  2
  17.  
  18. /* Registers */
  19. #define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
  20. #define REG_BLUE    0x01  /* blue gain */
  21. #define REG_RED       0x02  /* red gain */
  22. #define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
  23. #define REG_COM1    0x04  /* Control 1 */
  24. #define COM1_CCIR656  0x40    /* CCIR656 enable */
  25.  
  26. #define REG_BAVE    0x05  /* U/B Average level */
  27. #define REG_GbAVE   0x06  /* Y/Gb Average level */
  28. #define REG_AECHH   0x07  /* AEC MS 5 bits */
  29. #define REG_RAVE    0x08  /* V/R Average level */
  30. #define REG_COM2    0x09  /* Control 2 */
  31. #define COM2_SSLEEP         0x10  /* Soft sleep mode */
  32. #define REG_PID           0x0a  /* Product ID MSB */
  33. #define REG_VER           0x0b  /* Product ID LSB */
  34. #define REG_COM3    0x0c  /* Control 3 */
  35. #define COM3_SWAP         0x40  /* Byte swap */
  36. #define COM3_SCALEEN          0x08  /* Enable scaling */
  37. #define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
  38. #define REG_COM4    0x0d  /* Control 4 */
  39. #define REG_COM5    0x0e  /* All "reserved" */
  40. #define REG_COM6    0x0f  /* Control 6 */
  41. #define REG_AECH    0x10  /* More bits of AEC value */
  42. #define REG_CLKRC   0x11  /* Clocl control */
  43. #define CLK_EXT           0x40  /* Use external clock directly */
  44. #define CLK_SCALE   0x3f  /* Mask for internal clock scale */
  45. #define REG_COM7    0x12  /* Control 7 */ //REG mean address.
  46. #define COM7_RESET          0x80  /* Register reset */
  47. #define COM7_FMT_MASK         0x38
  48. #define COM7_FMT_VGA          0x00
  49. #define COM7_FMT_CIF          0x20  /* CIF format */
  50. #define COM7_FMT_QVGA         0x10  /* QVGA format */
  51. #define COM7_FMT_QCIF         0x08  /* QCIF format */
  52. #define COM7_RGB          0x04  /* bits 0 and 2 - RGB format */
  53. #define COM7_YUV          0x00  /* YUV */
  54. #define COM7_BAYER          0x01  /* Bayer format */
  55. #define COM7_PBAYER         0x05  /* "Processed bayer" */
  56. #define REG_COM8    0x13  /* Control 8 */
  57. #define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
  58. #define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
  59. #define COM8_BFILT    0x20  /* Band filter enable */
  60. #define COM8_AGC    0x04  /* Auto gain enable */
  61. #define COM8_AWB    0x02  /* White balance enable */
  62. #define COM8_AEC    0x01  /* Auto exposure enable */
  63. #define REG_COM9    0x14  /* Control 9- gain ceiling */
  64. #define REG_COM10   0x15  /* Control 10 */
  65. #define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
  66. #define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
  67. #define COM10_HREF_REV          0x08  /* Reverse HREF */
  68. #define COM10_VS_LEAD         0x04  /* VSYNC on clock leading edge */
  69. #define COM10_VS_NEG          0x02  /* VSYNC negative */
  70. #define COM10_HS_NEG          0x01  /* HSYNC negative */
  71. #define REG_HSTART    0x17  /* Horiz start high bits */
  72. #define REG_HSTOP   0x18  /* Horiz stop high bits */
  73. #define REG_VSTART    0x19  /* Vert start high bits */
  74. #define REG_VSTOP   0x1a  /* Vert stop high bits */
  75. #define REG_PSHFT   0x1b  /* Pixel delay after HREF */
  76. #define REG_MIDH    0x1c  /* Manuf. ID high */
  77. #define REG_MIDL    0x1d  /* Manuf. ID low */
  78. #define REG_MVFP    0x1e  /* Mirror / vflip */
  79. #define MVFP_MIRROR         0x20  /* Mirror image */
  80. #define MVFP_FLIP   0x10  /* Vertical flip */
  81.  
  82. #define REG_AEW           0x24  /* AGC upper limit */
  83. #define REG_AEB           0x25    /* AGC lower limit */
  84. #define REG_VPT           0x26  /* AGC/AEC fast mode op region */
  85. #define REG_HSYST   0x30  /* HSYNC rising edge delay */
  86. #define REG_HSYEN   0x31  /* HSYNC falling edge delay */
  87. #define REG_HREF    0x32  /* HREF pieces */
  88. #define REG_TSLB    0x3a  /* lots of stuff */
  89. #define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
  90. #define REG_COM11   0x3b  /* Control 11 */
  91. #define COM11_NIGHT         0x80  /* NIght mode enable */
  92. #define COM11_NMFR          0x60  /* Two bit NM frame rate */
  93. #define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
  94. #define COM11_50HZ          0x08  /* Manual 50Hz select */
  95. #define COM11_EXP   0x02
  96. #define REG_COM12   0x3c  /* Control 12 */
  97. #define COM12_HREF          0x80  /* HREF always */
  98. #define REG_COM13   0x3d  /* Control 13 */
  99. #define COM13_GAMMA         0x80  /* Gamma enable */
  100. #define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
  101. #define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
  102. #define REG_COM14   0x3e  /* Control 14 */
  103. #define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
  104. #define REG_EDGE    0x3f  /* Edge enhancement factor */
  105. #define REG_COM15   0x40  /* Control 15 */
  106. #define COM15_R10F0         0x00  /* Data range 10 to F0 */
  107. #define COM15_R01FE         0x80  /*      01 to FE */
  108. #define COM15_R00FF         0xc0  /*      00 to FF */
  109. #define COM15_RGB565          0x10  /* RGB565 output */
  110. #define COM15_RGB555          0x30  /* RGB555 output */
  111. #define REG_COM16   0x41  /* Control 16 */
  112. #define COM16_AWBGAIN         0x08  /* AWB gain enable */
  113. #define REG_COM17   0x42  /* Control 17 */
  114. #define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
  115. #define COM17_CBAR          0x08  /* DSP Color bar */
  116. /*
  117. * This matrix defines how the colors are generated, must be
  118. * tweaked to adjust hue and saturation.
  119. *
  120. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  121. * They are nine-bit signed quantities, with the sign bit
  122. * stored in0x58.Sign for v-red is bit 0, and up from there.
  123. */
  124. #define REG_CMATRIX_BASE  0x4f
  125. #define CMATRIX_LEN           6
  126. #define REG_CMATRIX_SIGN  0x58
  127. #define REG_BRIGHT    0x55  /* Brightness */
  128. #define REG_CONTRAS         0x56  /* Contrast control */
  129. #define REG_GFIX    0x69  /* Fix gain control */
  130. #define REG_REG76   0x76  /* OV's name */
  131. #define R76_BLKPCOR         0x80  /* Black pixel correction enable */
  132. #define R76_WHTPCOR         0x40  /* White pixel correction enable */
  133. #define REG_RGB444          0x8c  /* RGB 444 control */
  134. #define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
  135. #define R444_RGBX   0x01  /* Empty nibble at end */
  136. #define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
  137. #define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
  138. #define REG_BD50MAX         0xa5  /* 50hz banding step limit */
  139. #define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
  140. #define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
  141. #define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
  142. #define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
  143. #define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
  144. #define REG_BD60MAX         0xab  /* 60hz banding step limit */
  145. #define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
  146. #define REG_BLUE    0x01  /* blue gain */
  147. #define REG_RED           0x02  /* red gain */
  148. #define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
  149. #define REG_COM1    0x04  /* Control 1 */
  150. #define COM1_CCIR656          0x40  /* CCIR656 enable */
  151. #define REG_BAVE    0x05  /* U/B Average level */
  152. #define REG_GbAVE   0x06  /* Y/Gb Average level */
  153. #define REG_AECHH   0x07  /* AEC MS 5 bits */
  154. #define REG_RAVE    0x08  /* V/R Average level */
  155. #define REG_COM2    0x09  /* Control 2 */
  156. #define COM2_SSLEEP         0x10  /* Soft sleep mode */
  157. #define REG_PID           0x0a  /* Product ID MSB */
  158. #define REG_VER           0x0b  /* Product ID LSB */
  159. #define REG_COM3    0x0c  /* Control 3 */
  160. #define COM3_SWAP         0x40  /* Byte swap */
  161. #define COM3_SCALEEN          0x08  /* Enable scaling */
  162. #define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
  163. #define REG_COM4    0x0d  /* Control 4 */
  164. #define REG_COM5    0x0e  /* All "reserved" */
  165. #define REG_COM6    0x0f  /* Control 6 */
  166. #define REG_AECH    0x10  /* More bits of AEC value */
  167. #define REG_CLKRC   0x11  /* Clocl control */
  168. #define CLK_EXT           0x40  /* Use external clock directly */
  169. #define CLK_SCALE   0x3f  /* Mask for internal clock scale */
  170. #define REG_COM7    0x12  /* Control 7 */
  171. #define COM7_RESET          0x80  /* Register reset */
  172. #define COM7_FMT_MASK         0x38
  173. #define COM7_FMT_VGA          0x00
  174. #define COM7_FMT_CIF          0x20  /* CIF format */
  175. #define COM7_FMT_QVGA         0x10  /* QVGA format */
  176. #define COM7_FMT_QCIF         0x08  /* QCIF format */
  177. #define COM7_RGB    0x04  /* bits 0 and 2 - RGB format */
  178. #define COM7_YUV    0x00  /* YUV */
  179. #define COM7_BAYER          0x01  /* Bayer format */
  180. #define COM7_PBAYER         0x05  /* "Processed bayer" */
  181. #define REG_COM8    0x13  /* Control 8 */
  182. #define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
  183. #define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
  184. #define COM8_BFILT    0x20  /* Band filter enable */
  185. #define COM8_AGC    0x04  /* Auto gain enable */
  186. #define COM8_AWB    0x02  /* White balance enable */
  187. #define COM8_AEC    0x01  /* Auto exposure enable */
  188. #define REG_COM9    0x14  /* Control 9- gain ceiling */
  189. #define REG_COM10   0x15  /* Control 10 */
  190. #define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
  191. #define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
  192. #define COM10_HREF_REV          0x08  /* Reverse HREF */
  193. #define COM10_VS_LEAD           0x04  /* VSYNC on clock leading edge */
  194. #define COM10_VS_NEG          0x02  /* VSYNC negative */
  195. #define COM10_HS_NEG          0x01  /* HSYNC negative */
  196. #define REG_HSTART    0x17  /* Horiz start high bits */
  197. #define REG_HSTOP   0x18  /* Horiz stop high bits */
  198. #define REG_VSTART    0x19  /* Vert start high bits */
  199. #define REG_VSTOP   0x1a  /* Vert stop high bits */
  200. #define REG_PSHFT   0x1b  /* Pixel delay after HREF */
  201. #define REG_MIDH    0x1c  /* Manuf. ID high */
  202. #define REG_MIDL    0x1d  /* Manuf. ID low */
  203. #define REG_MVFP    0x1e  /* Mirror / vflip */
  204. #define MVFP_MIRROR         0x20  /* Mirror image */
  205. #define MVFP_FLIP   0x10  /* Vertical flip */
  206. #define REG_AEW           0x24  /* AGC upper limit */
  207. #define REG_AEB           0x25  /* AGC lower limit */
  208. #define REG_VPT           0x26  /* AGC/AEC fast mode op region */
  209. #define REG_HSYST   0x30  /* HSYNC rising edge delay */
  210. #define REG_HSYEN   0x31  /* HSYNC falling edge delay */
  211. #define REG_HREF    0x32  /* HREF pieces */
  212. #define REG_TSLB    0x3a  /* lots of stuff */
  213. #define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
  214. #define REG_COM11   0x3b  /* Control 11 */
  215. #define COM11_NIGHT         0x80  /* NIght mode enable */
  216. #define COM11_NMFR          0x60  /* Two bit NM frame rate */
  217. #define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
  218. #define COM11_50HZ          0x08  /* Manual 50Hz select */
  219. #define COM11_EXP   0x02
  220. #define REG_COM12   0x3c  /* Control 12 */
  221. #define COM12_HREF          0x80  /* HREF always */
  222. #define REG_COM13   0x3d  /* Control 13 */
  223. #define COM13_GAMMA         0x80  /* Gamma enable */
  224. #define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
  225. #define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
  226. #define REG_COM14   0x3e  /* Control 14 */
  227. #define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
  228. #define REG_EDGE    0x3f  /* Edge enhancement factor */
  229. #define REG_COM15   0x40  /* Control 15 */
  230. #define COM15_R10F0         0x00  /* Data range 10 to F0 */
  231. #define COM15_R01FE         0x80  /*      01 to FE */
  232. #define COM15_R00FF         0xc0  /*      00 to FF */
  233. #define COM15_RGB565          0x10  /* RGB565 output */
  234. #define COM15_RGB555          0x30  /* RGB555 output */
  235. #define REG_COM16   0x41  /* Control 16 */
  236. #define COM16_AWBGAIN         0x08  /* AWB gain enable */
  237. #define REG_COM17   0x42  /* Control 17 */
  238. #define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
  239. #define COM17_CBAR          0x08  /* DSP Color bar */
  240.  
  241. #define CMATRIX_LEN             6
  242. #define REG_BRIGHT    0x55  /* Brightness */
  243. #define REG_REG76   0x76  /* OV's name */
  244. #define R76_BLKPCOR         0x80  /* Black pixel correction enable */
  245. #define R76_WHTPCOR         0x40  /* White pixel correction enable */
  246. #define REG_RGB444          0x8c  /* RGB 444 control */
  247. #define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
  248. #define R444_RGBX   0x01  /* Empty nibble at end */
  249. #define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
  250. #define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
  251. #define REG_BD50MAX         0xa5  /* 50hz banding step limit */
  252. #define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
  253. #define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
  254. #define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
  255. #define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
  256. #define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
  257. #define REG_BD60MAX         0xab  /* 60hz banding step limit */
  258. #define MTX1            0x4f  /* Matrix Coefficient 1 */
  259. #define MTX2            0x50  /* Matrix Coefficient 2 */
  260. #define MTX3            0x51  /* Matrix Coefficient 3 */
  261. #define MTX4            0x52  /* Matrix Coefficient 4 */
  262. #define MTX5            0x53  /* Matrix Coefficient 5 */
  263. #define MTX6            0x54  /* Matrix Coefficient 6 */
  264. #define REG_CONTRAS         0x56  /* Contrast control */
  265. #define MTXS            0x58  /* Matrix Coefficient Sign */
  266. #define AWBC7           0x59  /* AWB Control 7 */
  267. #define AWBC8           0x5a  /* AWB Control 8 */
  268. #define AWBC9           0x5b  /* AWB Control 9 */
  269. #define AWBC10            0x5c  /* AWB Control 10 */
  270. #define AWBC11            0x5d  /* AWB Control 11 */
  271. #define AWBC12            0x5e  /* AWB Control 12 */
  272. #define REG_GFI           0x69  /* Fix gain control */
  273. #define GGAIN           0x6a  /* G Channel AWB Gain */
  274. #define DBLV            0x6b  
  275. #define AWBCTR3           0x6c  /* AWB Control 3 */
  276. #define AWBCTR2           0x6d  /* AWB Control 2 */
  277. #define AWBCTR1           0x6e  /* AWB Control 1 */
  278. #define AWBCTR0           0x6f  /* AWB Control 0 */
  279.  
  280.  
  281. struct regval_list{
  282.  uint8_t reg_num;
  283.  uint8_t value;
  284. };
  285.  
  286. uint8_t myImage[32][32];
  287.  
  288. const struct regval_list qvga_ov7670[] PROGMEM = {
  289.  { REG_COM14, 0x19 },
  290.  { 0x72, 0x11 },
  291.  { 0x73, 0xf1 },
  292.  
  293.  { REG_HSTART, 0x16 },
  294.  { REG_HSTOP, 0x04 },
  295.  { REG_HREF, 0xF6 },
  296.  { REG_VSTART, 0x02 },
  297.  { REG_VSTOP, 0x7a },
  298.  { REG_VREF, 0x0a },
  299.  
  300.  { 0xff, 0xff }, /* END MARKER */
  301. };
  302.  
  303. const struct regval_list yuv422_ov7670[] PROGMEM = {
  304.  { REG_COM7, 0x0 },  /* Selects YUV mode */
  305.  { REG_RGB444, 0 },  /* No RGB444 please */
  306.  { REG_COM1, 0 },
  307.  { REG_COM15, COM15_R00FF },
  308.  { REG_COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
  309.  { 0x4f, 0x80 },   /* "matrix coefficient 1" */
  310.  { 0x50, 0x80 },   /* "matrix coefficient 2" */
  311.  { 0x51, 0 },    /* vb */
  312.  { 0x52, 0x22 },   /* "matrix coefficient 4" */
  313.  { 0x53, 0x5e },   /* "matrix coefficient 5" */
  314.  { 0x54, 0x80 },   /* "matrix coefficient 6" */
  315.  { REG_COM13, COM13_UVSAT },
  316.  { 0xff, 0xff },   /* END MARKER */
  317. };
  318.  
  319. const struct regval_list ov7670_default_regs[] PROGMEM = {//from the linux driver
  320.  { REG_COM7, COM7_RESET },
  321.  { REG_TSLB, 0x04 }, /* OV */
  322.  { REG_COM7, 0 },  /* VGA */
  323.  /*
  324.  * Set the hardware window.  These values from OV don't entirely
  325.  * make sense - hstop is less than hstart.  But they work...
  326.  */
  327.  { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  328.  { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  329.  { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  330.  
  331.  { REG_COM3, 0 }, { REG_COM14, 0 },
  332.  /* Mystery scaling numbers */
  333.  { 0x70, 0x3a }, { 0x71, 0x35 },
  334.  { 0x72, 0x11 }, { 0x73, 0xf0 },
  335.  { 0xa2,/* 0x02 changed to 1*/1 }, { REG_COM10, 0x0 },
  336.  /* Gamma curve values */
  337.  { 0x7a, 0x20 }, { 0x7b, 0x10 },
  338.  { 0x7c, 0x1e }, { 0x7d, 0x35 },
  339.  { 0x7e, 0x5a }, { 0x7f, 0x69 },
  340.  { 0x80, 0x76 }, { 0x81, 0x80 },
  341.  { 0x82, 0x88 }, { 0x83, 0x8f },
  342.  { 0x84, 0x96 }, { 0x85, 0xa3 },
  343.  { 0x86, 0xaf }, { 0x87, 0xc4 },
  344.  { 0x88, 0xd7 }, { 0x89, 0xe8 },
  345.  /* AGC and AEC parameters.  Note we start by disabling those features,
  346.  then turn them only after tweaking the values. */
  347.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP },
  348.  { REG_GAIN, 0 }, { REG_AECH, 0 },
  349.  { REG_COM4, 0x40 }, /* magic reserved bit */
  350.  { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  351.  { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  352.  { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  353.  { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  354.  { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  355.  { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  356.  { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  357.  { REG_HAECC7, 0x94 },
  358.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC },
  359.  { 0x30, 0 }, { 0x31, 0 },//disable some delays
  360.  /* Almost all of these are magic "reserved" values.  */
  361.  { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  362.  { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  363.  { 0x21, 0x02 }, { 0x22, 0x91 },
  364.  { 0x29, 0x07 }, { 0x33, 0x0b },
  365.  { 0x35, 0x0b }, { 0x37, 0x1d },
  366.  { 0x38, 0x71 }, { 0x39, 0x2a },
  367.  { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  368.  { 0x4e, 0x20 }, { REG_GFIX, 0 },
  369.  /*{0x6b, 0x4a},*/{ 0x74, 0x10 },
  370.  { 0x8d, 0x4f }, { 0x8e, 0 },
  371.  { 0x8f, 0 }, { 0x90, 0 },
  372.  { 0x91, 0 }, { 0x96, 0 },
  373.  { 0x9a, 0 }, { 0xb0, 0x84 },
  374.  { 0xb1, 0x0c }, { 0xb2, 0x0e },
  375.  { 0xb3, 0x82 }, { 0xb8, 0x0a },
  376.  
  377.  /* More reserved magic, some of which tweaks white balance */
  378.  { 0x43, 0x0a }, { 0x44, 0xf0 },
  379.  { 0x45, 0x34 }, { 0x46, 0x58 },
  380.  { 0x47, 0x28 }, { 0x48, 0x3a },
  381.  { 0x59, 0x88 }, { 0x5a, 0x88 },
  382.  { 0x5b, 0x44 }, { 0x5c, 0x67 },
  383.  { 0x5d, 0x49 }, { 0x5e, 0x0e },
  384.  { 0x6c, 0x0a }, { 0x6d, 0x55 },
  385.  { 0x6e, 0x11 }, { 0x6f, 0x9e }, /* it was 0x9F "9e for advance AWB" */
  386.  { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  387.  { REG_RED, 0x60 },
  388.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC | COM8_AWB },
  389.  
  390.  /* Matrix coefficients */
  391.  { 0x4f, 0x80 }, { 0x50, 0x80 },
  392.  { 0x51, 0 },    { 0x52, 0x22 },
  393.  { 0x53, 0x5e }, { 0x54, 0x80 },
  394.  { 0x58, 0x9e },
  395.  
  396.  { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  397.  { 0x75, 0x05 }, { REG_REG76, 0xe1 },
  398.  { 0x4c, 0 },     { 0x77, 0x01 },
  399.  { REG_COM13, /*0xc3*/0x48 }, { 0x4b, 0x09 },
  400.  { 0xc9, 0x60 },   /*{REG_COM16, 0x38},*/
  401.  { 0x56, 0x40 },
  402.  
  403.  { 0x34, 0x11 }, { REG_COM11, COM11_EXP | COM11_HZAUTO },
  404.  { 0xa4, 0x82/*Was 0x88*/ }, { 0x96, 0 },
  405.  { 0x97, 0x30 }, { 0x98, 0x20 },
  406.  { 0x99, 0x30 }, { 0x9a, 0x84 },
  407.  { 0x9b, 0x29 }, { 0x9c, 0x03 },
  408.  { 0x9d, 0x4c }, { 0x9e, 0x3f },
  409.  { 0x78, 0x04 },
  410.  
  411.  /* Extra-weird stuff.  Some sort of multiplexor register */
  412.  { 0x79, 0x01 }, { 0xc8, 0xf0 },
  413.  { 0x79, 0x0f }, { 0xc8, 0x00 },
  414.  { 0x79, 0x10 }, { 0xc8, 0x7e },
  415.  { 0x79, 0x0a }, { 0xc8, 0x80 },
  416.  { 0x79, 0x0b }, { 0xc8, 0x01 },
  417.  { 0x79, 0x0c }, { 0xc8, 0x0f },
  418.  { 0x79, 0x0d }, { 0xc8, 0x20 },
  419.  { 0x79, 0x09 }, { 0xc8, 0x80 },
  420.  { 0x79, 0x02 }, { 0xc8, 0xc0 },
  421.  { 0x79, 0x03 }, { 0xc8, 0x40 },
  422.  { 0x79, 0x05 }, { 0xc8, 0x30 },
  423.  { 0x79, 0x26 },
  424.  
  425.  { 0xff, 0xff }, /* END MARKER */
  426. };
  427.  
  428.  
  429. void wrSensorRegs8_8(const struct regval_list reglist[]){
  430.    int index = 0;
  431.    regval_list regpaar = reglist[index];
  432.  
  433.    do {
  434.      write(regpaar.reg_num, regpaar.value);
  435.      index++;
  436.      regpaar = reglist[index];
  437.    } while (regpaar.reg_num != 0xFF);
  438. }
  439.  
  440. void setColor(void){
  441.  wrSensorRegs8_8(yuv422_ov7670);
  442. }
  443.  
  444. void setRes(void){
  445.  write(REG_COM3, 4); // REG_COM3 enable scaling
  446.  wrSensorRegs8_8(qvga_ov7670);
  447. }
  448.  
  449. #define RESET 33
  450. #define VSYNC 52
  451. #define PCLK 32
  452.  
  453. #define D8 44
  454. #define D7 45
  455. #define D6 46
  456. #define D5 47
  457. #define D4 48
  458. #define D3 49
  459. #define D2 50
  460. #define D1 51
  461.  
  462. #define pullup1 22
  463. #define pullup2 23
  464.  
  465. void camInit(void){
  466.  pinMode(RESET, OUTPUT);
  467.  digitalWrite(RESET, HIGH);
  468.  
  469.  pinMode(pullup1, OUTPUT);
  470.  digitalWrite(pullup1, HIGH);
  471.  
  472.  pinMode(pullup2, OUTPUT);
  473.  digitalWrite(pullup2, HIGH);
  474.  
  475.  
  476.  write(0x12, 0x80);
  477.  delayMicroseconds(100);
  478.  wrSensorRegs8_8(ov7670_default_regs);
  479.  write(REG_COM10, 32);//PCLK does not toggle on HBLANK.
  480.  
  481.  pinMode(13, OUTPUT);
  482.  
  483.    
  484.  pinMode(D1, INPUT);
  485.  pinMode(D2, INPUT);
  486.  pinMode(D3, INPUT);
  487.  pinMode(D4, INPUT);
  488.  pinMode(D5, INPUT);
  489.  pinMode(D6, INPUT);
  490.  pinMode(D7, INPUT);
  491.  pinMode(D8, INPUT);
  492.  
  493.  pinMode(VSYNC, INPUT);
  494.  pinMode(PCLK, INPUT);
  495. }
  496.  
  497. void setup() {
  498.  Serial.begin(460800);
  499.  Wire.begin();
  500.  
  501.  int32_t mask_PWM_pin = digitalPinToBitMask(7);
  502.  REG_PMC_PCER1 = 1<<4;               // activate clock for PWM controller
  503.  REG_PIOC_PDR |= mask_PWM_pin;  // activate peripheral functions for pin (disables all PIO functionality)
  504.  REG_PIOC_ABSR |= mask_PWM_pin; // choose peripheral option B    
  505.  REG_PWM_CLK = 0;                     // choose clock rate, 0 -> full MCLK as reference 84MHz
  506.  REG_PWM_CMR6 = 0<<9;             // select clock and polarity for PWM channel (pin7) -> (CPOL = 0)
  507.  REG_PWM_CPRD6 = 8;                // initialize PWM period -> T = value/84MHz (value: up to 16bit), value=8 -> 10.5MHz
  508.  REG_PWM_CDTY6 = 4;                // initialize duty cycle, REG_PWM_CPRD6 / value = duty cycle, for 8/4 = 50%
  509.  REG_PWM_ENA = 1<<6;               // enable PWM on PWM channel (pin 7 = PWML6)
  510.  
  511.  camInit();
  512.  setRes();
  513.  setColor();
  514.  write(0x11, 6);
  515. }
  516.  
  517.  
  518. void loop() {
  519.  captureImg(320, 240);
  520. }
  521.  
  522. static void captureImg(uint16_t wg, uint16_t hg){
  523.  uint16_t y, x;
  524.  
  525.  Serial.println("*RDY*");
  526.  
  527.  while (!(REG_PIOB_PDSR & (1 << 21)));//wait for high
  528.  while ((REG_PIOB_PDSR & (1 << 21)));//wait for low
  529.  
  530.  y = hg;
  531.  while (y--){
  532.    x = wg;
  533.    while (x--){
  534.      while ((REG_PIOD_PDSR & (1 << 10)));//wait for low
  535.      myImage[y][x] = (REG_PIOC_PDSR & 0xFF000) >> 12;
  536.      while (!(REG_PIOD_PDSR & (1 << 10)));//wait for high
  537.      while ((REG_PIOD_PDSR & (1 << 10)));//wait for low
  538.      while (!(REG_PIOD_PDSR & (1 << 10)));//wait for high      
  539.    }
  540.  }
  541.  
  542.  for (y = 0; y < hg; y++) {
  543.    for (x = 0; x < wg; x++) {
  544.      uart_putchar(myImage[y][x]);      
  545.    }
  546.  }
  547. }
  548.  
  549. void write(uint8_t regID, byte regDat){
  550.  Wire.beginTransmission(address);
  551.  Wire.write(regID & 0x00FF);    
  552.  Wire.write(regDat & 0x00FF);    
  553.    
  554.  if(Wire.endTransmission(true)){
  555.    Serial.print("error write reg ");
  556.    Serial.println(regID);
  557.  }
  558.  delay(20);
  559. }
  560.  
  561.  
  562. static inline int uart_putchar(const uint8_t c) {
  563.    while(!(UART->UART_SR & UART_SR_TXRDY));
  564.    UART->UART_THR = c;
  565.    return 0;
  566. }
  567.  
  568. #define vga   0
  569. #define qvga  1
  570. #define qqvga   2
  571. #define yuv422  0
  572. #define rgb565  1
  573. #define bayerRGB  2
  574.  
  575. /* Registers */
  576. #define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
  577. #define REG_BLUE    0x01  /* blue gain */
  578. #define REG_RED       0x02  /* red gain */
  579. #define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
  580. #define REG_COM1    0x04  /* Control 1 */
  581. #define COM1_CCIR656  0x40    /* CCIR656 enable */
  582.  
  583. #define REG_BAVE    0x05  /* U/B Average level */
  584. #define REG_GbAVE   0x06  /* Y/Gb Average level */
  585. #define REG_AECHH   0x07  /* AEC MS 5 bits */
  586. #define REG_RAVE    0x08  /* V/R Average level */
  587. #define REG_COM2    0x09  /* Control 2 */
  588. #define COM2_SSLEEP         0x10  /* Soft sleep mode */
  589. #define REG_PID           0x0a  /* Product ID MSB */
  590. #define REG_VER           0x0b  /* Product ID LSB */
  591. #define REG_COM3    0x0c  /* Control 3 */
  592. #define COM3_SWAP         0x40  /* Byte swap */
  593. #define COM3_SCALEEN          0x08  /* Enable scaling */
  594. #define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
  595. #define REG_COM4    0x0d  /* Control 4 */
  596. #define REG_COM5    0x0e  /* All "reserved" */
  597. #define REG_COM6    0x0f  /* Control 6 */
  598. #define REG_AECH    0x10  /* More bits of AEC value */
  599. #define REG_CLKRC   0x11  /* Clocl control */
  600. #define CLK_EXT           0x40  /* Use external clock directly */
  601. #define CLK_SCALE   0x3f  /* Mask for internal clock scale */
  602. #define REG_COM7    0x12  /* Control 7 */ //REG mean address.
  603. #define COM7_RESET          0x80  /* Register reset */
  604. #define COM7_FMT_MASK         0x38
  605. #define COM7_FMT_VGA          0x00
  606. #define COM7_FMT_CIF          0x20  /* CIF format */
  607. #define COM7_FMT_QVGA         0x10  /* QVGA format */
  608. #define COM7_FMT_QCIF         0x08  /* QCIF format */
  609. #define COM7_RGB          0x04  /* bits 0 and 2 - RGB format */
  610. #define COM7_YUV          0x00  /* YUV */
  611. #define COM7_BAYER          0x01  /* Bayer format */
  612. #define COM7_PBAYER         0x05  /* "Processed bayer" */
  613. #define REG_COM8    0x13  /* Control 8 */
  614. #define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
  615. #define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
  616. #define COM8_BFILT    0x20  /* Band filter enable */
  617. #define COM8_AGC    0x04  /* Auto gain enable */
  618. #define COM8_AWB    0x02  /* White balance enable */
  619. #define COM8_AEC    0x01  /* Auto exposure enable */
  620. #define REG_COM9    0x14  /* Control 9- gain ceiling */
  621. #define REG_COM10   0x15  /* Control 10 */
  622. #define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
  623. #define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
  624. #define COM10_HREF_REV          0x08  /* Reverse HREF */
  625. #define COM10_VS_LEAD         0x04  /* VSYNC on clock leading edge */
  626. #define COM10_VS_NEG          0x02  /* VSYNC negative */
  627. #define COM10_HS_NEG          0x01  /* HSYNC negative */
  628. #define REG_HSTART    0x17  /* Horiz start high bits */
  629. #define REG_HSTOP   0x18  /* Horiz stop high bits */
  630. #define REG_VSTART    0x19  /* Vert start high bits */
  631. #define REG_VSTOP   0x1a  /* Vert stop high bits */
  632. #define REG_PSHFT   0x1b  /* Pixel delay after HREF */
  633. #define REG_MIDH    0x1c  /* Manuf. ID high */
  634. #define REG_MIDL    0x1d  /* Manuf. ID low */
  635. #define REG_MVFP    0x1e  /* Mirror / vflip */
  636. #define MVFP_MIRROR         0x20  /* Mirror image */
  637. #define MVFP_FLIP   0x10  /* Vertical flip */
  638.  
  639. #define REG_AEW           0x24  /* AGC upper limit */
  640. #define REG_AEB           0x25    /* AGC lower limit */
  641. #define REG_VPT           0x26  /* AGC/AEC fast mode op region */
  642. #define REG_HSYST   0x30  /* HSYNC rising edge delay */
  643. #define REG_HSYEN   0x31  /* HSYNC falling edge delay */
  644. #define REG_HREF    0x32  /* HREF pieces */
  645. #define REG_TSLB    0x3a  /* lots of stuff */
  646. #define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
  647. #define REG_COM11   0x3b  /* Control 11 */
  648. #define COM11_NIGHT         0x80  /* NIght mode enable */
  649. #define COM11_NMFR          0x60  /* Two bit NM frame rate */
  650. #define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
  651. #define COM11_50HZ          0x08  /* Manual 50Hz select */
  652. #define COM11_EXP   0x02
  653. #define REG_COM12   0x3c  /* Control 12 */
  654. #define COM12_HREF          0x80  /* HREF always */
  655. #define REG_COM13   0x3d  /* Control 13 */
  656. #define COM13_GAMMA         0x80  /* Gamma enable */
  657. #define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
  658. #define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
  659. #define REG_COM14   0x3e  /* Control 14 */
  660. #define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
  661. #define REG_EDGE    0x3f  /* Edge enhancement factor */
  662. #define REG_COM15   0x40  /* Control 15 */
  663. #define COM15_R10F0         0x00  /* Data range 10 to F0 */
  664. #define COM15_R01FE         0x80  /*      01 to FE */
  665. #define COM15_R00FF         0xc0  /*      00 to FF */
  666. #define COM15_RGB565          0x10  /* RGB565 output */
  667. #define COM15_RGB555          0x30  /* RGB555 output */
  668. #define REG_COM16   0x41  /* Control 16 */
  669. #define COM16_AWBGAIN         0x08  /* AWB gain enable */
  670. #define REG_COM17   0x42  /* Control 17 */
  671. #define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
  672. #define COM17_CBAR          0x08  /* DSP Color bar */
  673. /*
  674. * This matrix defines how the colors are generated, must be
  675. * tweaked to adjust hue and saturation.
  676. *
  677. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  678. * They are nine-bit signed quantities, with the sign bit
  679. * stored in0x58.Sign for v-red is bit 0, and up from there.
  680. */
  681. #define REG_CMATRIX_BASE  0x4f
  682. #define CMATRIX_LEN           6
  683. #define REG_CMATRIX_SIGN  0x58
  684. #define REG_BRIGHT    0x55  /* Brightness */
  685. #define REG_CONTRAS         0x56  /* Contrast control */
  686. #define REG_GFIX    0x69  /* Fix gain control */
  687. #define REG_REG76   0x76  /* OV's name */
  688. #define R76_BLKPCOR         0x80  /* Black pixel correction enable */
  689. #define R76_WHTPCOR         0x40  /* White pixel correction enable */
  690. #define REG_RGB444          0x8c  /* RGB 444 control */
  691. #define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
  692. #define R444_RGBX   0x01  /* Empty nibble at end */
  693. #define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
  694. #define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
  695. #define REG_BD50MAX         0xa5  /* 50hz banding step limit */
  696. #define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
  697. #define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
  698. #define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
  699. #define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
  700. #define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
  701. #define REG_BD60MAX         0xab  /* 60hz banding step limit */
  702. #define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
  703. #define REG_BLUE    0x01  /* blue gain */
  704. #define REG_RED           0x02  /* red gain */
  705. #define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
  706. #define REG_COM1    0x04  /* Control 1 */
  707. #define COM1_CCIR656          0x40  /* CCIR656 enable */
  708. #define REG_BAVE    0x05  /* U/B Average level */
  709. #define REG_GbAVE   0x06  /* Y/Gb Average level */
  710. #define REG_AECHH   0x07  /* AEC MS 5 bits */
  711. #define REG_RAVE    0x08  /* V/R Average level */
  712. #define REG_COM2    0x09  /* Control 2 */
  713. #define COM2_SSLEEP         0x10  /* Soft sleep mode */
  714. #define REG_PID           0x0a  /* Product ID MSB */
  715. #define REG_VER           0x0b  /* Product ID LSB */
  716. #define REG_COM3    0x0c  /* Control 3 */
  717. #define COM3_SWAP         0x40  /* Byte swap */
  718. #define COM3_SCALEEN          0x08  /* Enable scaling */
  719. #define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
  720. #define REG_COM4    0x0d  /* Control 4 */
  721. #define REG_COM5    0x0e  /* All "reserved" */
  722. #define REG_COM6    0x0f  /* Control 6 */
  723. #define REG_AECH    0x10  /* More bits of AEC value */
  724. #define REG_CLKRC   0x11  /* Clocl control */
  725. #define CLK_EXT           0x40  /* Use external clock directly */
  726. #define CLK_SCALE   0x3f  /* Mask for internal clock scale */
  727. #define REG_COM7    0x12  /* Control 7 */
  728. #define COM7_RESET          0x80  /* Register reset */
  729. #define COM7_FMT_MASK         0x38
  730. #define COM7_FMT_VGA          0x00
  731. #define COM7_FMT_CIF          0x20  /* CIF format */
  732. #define COM7_FMT_QVGA         0x10  /* QVGA format */
  733. #define COM7_FMT_QCIF         0x08  /* QCIF format */
  734. #define COM7_RGB    0x04  /* bits 0 and 2 - RGB format */
  735. #define COM7_YUV    0x00  /* YUV */
  736. #define COM7_BAYER          0x01  /* Bayer format */
  737. #define COM7_PBAYER         0x05  /* "Processed bayer" */
  738. #define REG_COM8    0x13  /* Control 8 */
  739. #define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
  740. #define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
  741. #define COM8_BFILT    0x20  /* Band filter enable */
  742. #define COM8_AGC    0x04  /* Auto gain enable */
  743. #define COM8_AWB    0x02  /* White balance enable */
  744. #define COM8_AEC    0x01  /* Auto exposure enable */
  745. #define REG_COM9    0x14  /* Control 9- gain ceiling */
  746. #define REG_COM10   0x15  /* Control 10 */
  747. #define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
  748. #define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
  749. #define COM10_HREF_REV          0x08  /* Reverse HREF */
  750. #define COM10_VS_LEAD           0x04  /* VSYNC on clock leading edge */
  751. #define COM10_VS_NEG          0x02  /* VSYNC negative */
  752. #define COM10_HS_NEG          0x01  /* HSYNC negative */
  753. #define REG_HSTART    0x17  /* Horiz start high bits */
  754. #define REG_HSTOP   0x18  /* Horiz stop high bits */
  755. #define REG_VSTART    0x19  /* Vert start high bits */
  756. #define REG_VSTOP   0x1a  /* Vert stop high bits */
  757. #define REG_PSHFT   0x1b  /* Pixel delay after HREF */
  758. #define REG_MIDH    0x1c  /* Manuf. ID high */
  759. #define REG_MIDL    0x1d  /* Manuf. ID low */
  760. #define REG_MVFP    0x1e  /* Mirror / vflip */
  761. #define MVFP_MIRROR         0x20  /* Mirror image */
  762. #define MVFP_FLIP   0x10  /* Vertical flip */
  763. #define REG_AEW           0x24  /* AGC upper limit */
  764. #define REG_AEB           0x25  /* AGC lower limit */
  765. #define REG_VPT           0x26  /* AGC/AEC fast mode op region */
  766. #define REG_HSYST   0x30  /* HSYNC rising edge delay */
  767. #define REG_HSYEN   0x31  /* HSYNC falling edge delay */
  768. #define REG_HREF    0x32  /* HREF pieces */
  769. #define REG_TSLB    0x3a  /* lots of stuff */
  770. #define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
  771. #define REG_COM11   0x3b  /* Control 11 */
  772. #define COM11_NIGHT         0x80  /* NIght mode enable */
  773. #define COM11_NMFR          0x60  /* Two bit NM frame rate */
  774. #define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
  775. #define COM11_50HZ          0x08  /* Manual 50Hz select */
  776. #define COM11_EXP   0x02
  777. #define REG_COM12   0x3c  /* Control 12 */
  778. #define COM12_HREF          0x80  /* HREF always */
  779. #define REG_COM13   0x3d  /* Control 13 */
  780. #define COM13_GAMMA         0x80  /* Gamma enable */
  781. #define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
  782. #define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
  783. #define REG_COM14   0x3e  /* Control 14 */
  784. #define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
  785. #define REG_EDGE    0x3f  /* Edge enhancement factor */
  786. #define REG_COM15   0x40  /* Control 15 */
  787. #define COM15_R10F0         0x00  /* Data range 10 to F0 */
  788. #define COM15_R01FE         0x80  /*      01 to FE */
  789. #define COM15_R00FF         0xc0  /*      00 to FF */
  790. #define COM15_RGB565          0x10  /* RGB565 output */
  791. #define COM15_RGB555          0x30  /* RGB555 output */
  792. #define REG_COM16   0x41  /* Control 16 */
  793. #define COM16_AWBGAIN         0x08  /* AWB gain enable */
  794. #define REG_COM17   0x42  /* Control 17 */
  795. #define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
  796. #define COM17_CBAR          0x08  /* DSP Color bar */
  797.  
  798. #define CMATRIX_LEN             6
  799. #define REG_BRIGHT    0x55  /* Brightness */
  800. #define REG_REG76   0x76  /* OV's name */
  801. #define R76_BLKPCOR         0x80  /* Black pixel correction enable */
  802. #define R76_WHTPCOR         0x40  /* White pixel correction enable */
  803. #define REG_RGB444          0x8c  /* RGB 444 control */
  804. #define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
  805. #define R444_RGBX   0x01  /* Empty nibble at end */
  806. #define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
  807. #define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
  808. #define REG_BD50MAX         0xa5  /* 50hz banding step limit */
  809. #define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
  810. #define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
  811. #define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
  812. #define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
  813. #define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
  814. #define REG_BD60MAX         0xab  /* 60hz banding step limit */
  815. #define MTX1            0x4f  /* Matrix Coefficient 1 */
  816. #define MTX2            0x50  /* Matrix Coefficient 2 */
  817. #define MTX3            0x51  /* Matrix Coefficient 3 */
  818. #define MTX4            0x52  /* Matrix Coefficient 4 */
  819. #define MTX5            0x53  /* Matrix Coefficient 5 */
  820. #define MTX6            0x54  /* Matrix Coefficient 6 */
  821. #define REG_CONTRAS         0x56  /* Contrast control */
  822. #define MTXS            0x58  /* Matrix Coefficient Sign */
  823. #define AWBC7           0x59  /* AWB Control 7 */
  824. #define AWBC8           0x5a  /* AWB Control 8 */
  825. #define AWBC9           0x5b  /* AWB Control 9 */
  826. #define AWBC10            0x5c  /* AWB Control 10 */
  827. #define AWBC11            0x5d  /* AWB Control 11 */
  828. #define AWBC12            0x5e  /* AWB Control 12 */
  829. #define REG_GFI           0x69  /* Fix gain control */
  830. #define GGAIN           0x6a  /* G Channel AWB Gain */
  831. #define DBLV            0x6b  
  832. #define AWBCTR3           0x6c  /* AWB Control 3 */
  833. #define AWBCTR2           0x6d  /* AWB Control 2 */
  834. #define AWBCTR1           0x6e  /* AWB Control 1 */
  835. #define AWBCTR0           0x6f  /* AWB Control 0 */
  836. #define REG_PMC_PCER1
  837.  
  838. struct regval_list{
  839.  uint8_t reg_num;
  840.  uint8_t value;
  841. };
  842.  
  843. uint8_t myImage[32][32];
  844.  
  845. const struct regval_list qvga_ov7670[] PROGMEM = {
  846.  { REG_COM14, 0x19 },
  847.  { 0x72, 0x11 },
  848.  { 0x73, 0xf1 },
  849.  
  850.  { REG_HSTART, 0x16 },
  851.  { REG_HSTOP, 0x04 },
  852.  { REG_HREF, 0xF6 },
  853.  { REG_VSTART, 0x02 },
  854.  { REG_VSTOP, 0x7a },
  855.  { REG_VREF, 0x0a },
  856.  
  857.  { 0xff, 0xff }, /* END MARKER */
  858. };
  859.  
  860. const struct regval_list yuv422_ov7670[] PROGMEM = {
  861.  { REG_COM7, 0x0 },  /* Selects YUV mode */
  862.  { REG_RGB444, 0 },  /* No RGB444 please */
  863.  { REG_COM1, 0 },
  864.  { REG_COM15, COM15_R00FF },
  865.  { REG_COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
  866.  { 0x4f, 0x80 },   /* "matrix coefficient 1" */
  867.  { 0x50, 0x80 },   /* "matrix coefficient 2" */
  868.  { 0x51, 0 },    /* vb */
  869.  { 0x52, 0x22 },   /* "matrix coefficient 4" */
  870.  { 0x53, 0x5e },   /* "matrix coefficient 5" */
  871.  { 0x54, 0x80 },   /* "matrix coefficient 6" */
  872.  { REG_COM13, COM13_UVSAT },
  873.  { 0xff, 0xff },   /* END MARKER */
  874. };
  875.  
  876. const struct regval_list ov7670_default_regs[] PROGMEM = {//from the linux driver
  877.  { REG_COM7, COM7_RESET },
  878.  { REG_TSLB, 0x04 }, /* OV */
  879.  { REG_COM7, 0 },  /* VGA */
  880.  /*
  881.  * Set the hardware window.  These values from OV don't entirely
  882.  * make sense - hstop is less than hstart.  But they work...
  883.  */
  884.  { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  885.  { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  886.  { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  887.  
  888.  { REG_COM3, 0 }, { REG_COM14, 0 },
  889.  /* Mystery scaling numbers */
  890.  { 0x70, 0x3a }, { 0x71, 0x35 },
  891.  { 0x72, 0x11 }, { 0x73, 0xf0 },
  892.  { 0xa2,/* 0x02 changed to 1*/1 }, { REG_COM10, 0x0 },
  893.  /* Gamma curve values */
  894.  { 0x7a, 0x20 }, { 0x7b, 0x10 },
  895.  { 0x7c, 0x1e }, { 0x7d, 0x35 },
  896.  { 0x7e, 0x5a }, { 0x7f, 0x69 },
  897.  { 0x80, 0x76 }, { 0x81, 0x80 },
  898.  { 0x82, 0x88 }, { 0x83, 0x8f },
  899.  { 0x84, 0x96 }, { 0x85, 0xa3 },
  900.  { 0x86, 0xaf }, { 0x87, 0xc4 },
  901.  { 0x88, 0xd7 }, { 0x89, 0xe8 },
  902.  /* AGC and AEC parameters.  Note we start by disabling those features,
  903.  then turn them only after tweaking the values. */
  904.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP },
  905.  { REG_GAIN, 0 }, { REG_AECH, 0 },
  906.  { REG_COM4, 0x40 }, /* magic reserved bit */
  907.  { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  908.  { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  909.  { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  910.  { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  911.  { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  912.  { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  913.  { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  914.  { REG_HAECC7, 0x94 },
  915.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC },
  916.  { 0x30, 0 }, { 0x31, 0 },//disable some delays
  917.  /* Almost all of these are magic "reserved" values.  */
  918.  { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  919.  { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  920.  { 0x21, 0x02 }, { 0x22, 0x91 },
  921.  { 0x29, 0x07 }, { 0x33, 0x0b },
  922.  { 0x35, 0x0b }, { 0x37, 0x1d },
  923.  { 0x38, 0x71 }, { 0x39, 0x2a },
  924.  { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  925.  { 0x4e, 0x20 }, { REG_GFIX, 0 },
  926.  /*{0x6b, 0x4a},*/{ 0x74, 0x10 },
  927.  { 0x8d, 0x4f }, { 0x8e, 0 },
  928.  { 0x8f, 0 }, { 0x90, 0 },
  929.  { 0x91, 0 }, { 0x96, 0 },
  930.  { 0x9a, 0 }, { 0xb0, 0x84 },
  931.  { 0xb1, 0x0c }, { 0xb2, 0x0e },
  932.  { 0xb3, 0x82 }, { 0xb8, 0x0a },
  933.  
  934.  /* More reserved magic, some of which tweaks white balance */
  935.  { 0x43, 0x0a }, { 0x44, 0xf0 },
  936.  { 0x45, 0x34 }, { 0x46, 0x58 },
  937.  { 0x47, 0x28 }, { 0x48, 0x3a },
  938.  { 0x59, 0x88 }, { 0x5a, 0x88 },
  939.  { 0x5b, 0x44 }, { 0x5c, 0x67 },
  940.  { 0x5d, 0x49 }, { 0x5e, 0x0e },
  941.  { 0x6c, 0x0a }, { 0x6d, 0x55 },
  942.  { 0x6e, 0x11 }, { 0x6f, 0x9e }, /* it was 0x9F "9e for advance AWB" */
  943.  { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  944.  { REG_RED, 0x60 },
  945.  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC | COM8_AWB },
  946.  
  947.  /* Matrix coefficients */
  948.  { 0x4f, 0x80 }, { 0x50, 0x80 },
  949.  { 0x51, 0 },    { 0x52, 0x22 },
  950.  { 0x53, 0x5e }, { 0x54, 0x80 },
  951.  { 0x58, 0x9e },
  952.  
  953.  { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  954.  { 0x75, 0x05 }, { REG_REG76, 0xe1 },
  955.  { 0x4c, 0 },     { 0x77, 0x01 },
  956.  { REG_COM13, /*0xc3*/0x48 }, { 0x4b, 0x09 },
  957.  { 0xc9, 0x60 },   /*{REG_COM16, 0x38},*/
  958.  { 0x56, 0x40 },
  959.  
  960.  { 0x34, 0x11 }, { REG_COM11, COM11_EXP | COM11_HZAUTO },
  961.  { 0xa4, 0x82/*Was 0x88*/ }, { 0x96, 0 },
  962.  { 0x97, 0x30 }, { 0x98, 0x20 },
  963.  { 0x99, 0x30 }, { 0x9a, 0x84 },
  964.  { 0x9b, 0x29 }, { 0x9c, 0x03 },
  965.  { 0x9d, 0x4c }, { 0x9e, 0x3f },
  966.  { 0x78, 0x04 },
  967.  
  968.  /* Extra-weird stuff.  Some sort of multiplexor register */
  969.  { 0x79, 0x01 }, { 0xc8, 0xf0 },
  970.  { 0x79, 0x0f }, { 0xc8, 0x00 },
  971.  { 0x79, 0x10 }, { 0xc8, 0x7e },
  972.  { 0x79, 0x0a }, { 0xc8, 0x80 },
  973.  { 0x79, 0x0b }, { 0xc8, 0x01 },
  974.  { 0x79, 0x0c }, { 0xc8, 0x0f },
  975.  { 0x79, 0x0d }, { 0xc8, 0x20 },
  976.  { 0x79, 0x09 }, { 0xc8, 0x80 },
  977.  { 0x79, 0x02 }, { 0xc8, 0xc0 },
  978.  { 0x79, 0x03 }, { 0xc8, 0x40 },
  979.  { 0x79, 0x05 }, { 0xc8, 0x30 },
  980.  { 0x79, 0x26 },
  981.  
  982.  { 0xff, 0xff }, /* END MARKER */
  983. };
  984.  
  985.  
  986. void wrSensorRegs8_8(const struct regval_list reglist[]){
  987.    int index = 0;
  988.    regval_list regpaar = reglist[index];
  989.  
  990.    do {
  991.      write(regpaar.reg_num, regpaar.value);
  992.      index++;
  993.      regpaar = reglist[index];
  994.    } while (regpaar.reg_num != 0xFF);
  995. }
  996.  
  997. void setColor(void){
  998.  wrSensorRegs8_8(yuv422_ov7670);
  999. }
  1000.  
  1001. void setRes(void){
  1002.  write(REG_COM3, 4); // REG_COM3 enable scaling
  1003.  wrSensorRegs8_8(qvga_ov7670);
  1004. }
  1005.  
  1006. #define RESET 33
  1007. #define VSYNC 52
  1008. #define PCLK 32
  1009.  
  1010. #define D8 44
  1011. #define D7 45
  1012. #define D6 46
  1013. #define D5 47
  1014. #define D4 48
  1015. #define D3 49
  1016. #define D2 50
  1017. #define D1 51
  1018.  
  1019. #define pullup1 22
  1020. #define pullup2 23
  1021.  
  1022. void camInit(void){
  1023.  pinMode(RESET, OUTPUT);
  1024.  digitalWrite(RESET, HIGH);
  1025.  
  1026.  pinMode(pullup1, OUTPUT);
  1027.  digitalWrite(pullup1, HIGH);
  1028.  
  1029.  pinMode(pullup2, OUTPUT);
  1030.  digitalWrite(pullup2, HIGH);
  1031.  
  1032.  
  1033.  write(0x12, 0x80);
  1034.  delayMicroseconds(100);
  1035.  wrSensorRegs8_8(ov7670_default_regs);
  1036.  write(REG_COM10, 32);//PCLK does not toggle on HBLANK.
  1037.  
  1038.  pinMode(13, OUTPUT);
  1039.  
  1040.    
  1041.  pinMode(D1, INPUT);
  1042.  pinMode(D2, INPUT);
  1043.  pinMode(D3, INPUT);
  1044.  pinMode(D4, INPUT);
  1045.  pinMode(D5, INPUT);
  1046.  pinMode(D6, INPUT);
  1047.  pinMode(D7, INPUT);
  1048.  pinMode(D8, INPUT);
  1049.  
  1050.  pinMode(VSYNC, INPUT);
  1051.  pinMode(PCLK, INPUT);
  1052. }
  1053.  
  1054. void setup() {
  1055.  Serial.begin(460800);
  1056.  Wire.begin();
  1057.  
  1058.  int32_t mask_PWM_pin = digitalPinToBitMask(7);
  1059.  REG_PMC_PCER1 = 1<<4;               // activate clock for PWM controller *******************************************************8
  1060.  REG_PIOC_PDR |= mask_PWM_pin;  // activate peripheral functions for pin (disables all PIO functionality)
  1061.  REG_PIOC_ABSR |= mask_PWM_pin; // choose peripheral option B    
  1062.  REG_PWM_CLK = 0;                     // choose clock rate, 0 -> full MCLK as reference 84MHz
  1063.  REG_PWM_CMR6 = 0<<9;             // select clock and polarity for PWM channel (pin7) -> (CPOL = 0)
  1064.  REG_PWM_CPRD6 = 8;                // initialize PWM period -> T = value/84MHz (value: up to 16bit), value=8 -> 10.5MHz
  1065.  REG_PWM_CDTY6 = 4;                // initialize duty cycle, REG_PWM_CPRD6 / value = duty cycle, for 8/4 = 50%
  1066.  REG_PWM_ENA = 1<<6;               // enable PWM on PWM channel (pin 7 = PWML6)
  1067.  
  1068.  camInit();
  1069.  setRes();
  1070.  setColor();
  1071.  write(0x11, 6);
  1072. }
  1073.  
  1074.  
  1075. void loop() {
  1076.  captureImg(320, 240);
  1077. }
  1078.  
  1079. static void captureImg(uint16_t wg, uint16_t hg){
  1080.  uint16_t y, x;
  1081.  
  1082.  Serial.println("*RDY*");
  1083.  
  1084.  while (!(REG_PIOB_PDSR & (1 << 21)));//wait for high
  1085.  while ((REG_PIOB_PDSR & (1 << 21)));//wait for low
  1086.  
  1087.  y = hg;
  1088.  while (y--){
  1089.    x = wg;
  1090.    while (x--){
  1091.      while ((REG_PIOD_PDSR & (1 << 10)));//wait for low
  1092.      myImage[y][x] = (REG_PIOC_PDSR & 0xFF000) >> 12;
  1093.      while (!(REG_PIOD_PDSR & (1 << 10)));//wait for high
  1094.      while ((REG_PIOD_PDSR & (1 << 10)));//wait for low
  1095.      while (!(REG_PIOD_PDSR & (1 << 10)));//wait for high      
  1096.    }
  1097.  }
  1098.  
  1099.  for (y = 0; y < hg; y++) {
  1100.    for (x = 0; x < wg; x++) {
  1101.      uart_putchar(myImage[y][x]);      
  1102.    }
  1103.  }
  1104. }
  1105.  
  1106. void write(uint8_t regID, byte regDat){
  1107.  Wire.beginTransmission(address);
  1108.  Wire.write(regID & 0x00FF);    
  1109.  Wire.write(regDat & 0x00FF);    
  1110.    
  1111.  if(Wire.endTransmission(true)){
  1112.    Serial.print("error write reg ");
  1113.    Serial.println(regID);
  1114.  }
  1115.  delay(20);
  1116. }
  1117.  
  1118.  
  1119. static inline int uart_putchar(const uint8_t c) {
  1120.    while(!(UART->UART_SR & UART_SR_TXRDY));
  1121.    UART->UART_THR = c;
  1122.    return 0;
  1123. }
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