control[12], Vec4 Addition ALU

iooo ooMM mmmm dddd CCaa aaaa aaAA AADD bbbb bbbb BBBB

i - whether to get Argument 1 from the vector multiplication ALU (above)
o - opcode:
    00000 - arg0 + arg1
    00100 - fract(arg1)
    01000 - notEqual(arg0, arg1)
    01100 - floor(arg1)
    01101 - ceil(arg1)
    01011 - equal(arg0, arg1)
    01001 - lessThan(arg0, arg1)
    01010 - lessThanEqual(arg0, arg1)
    01111 - max(arg0, arg1)
    01110 - min(arg0, arg1)
    10000 - sum3 - dest.xyzw = sum of first 3 components of arg1
    10001 - sum4 - dest.xyzw = sum of all components of arg1
        Note: for sum3 and sum4, the output is broadcast to all channels -
        you can use the write mask to select which component to write to
    10100 - dFdx(arg0, arg1)
    10101 - dFdy(arg0, arg1)
        Note: dFdx(x) is actually implemented as dFdx(-x, x) (same for dFdy)
        See "Speculation on derivatives" above
    11111 - arg1 (passthrough)
m - Mask, same as varying fetch opcode
d - Destination register
C - Argument 0 modifier
a - Argument 0 Swizzle descriptor
A - Argument 0 Source
D - Argument 1 modifier
b - Argument 1 Swizzle descriptor
B - Argument 1 Source
M - output modifier:
    00 - don't round
    01 - saturate - clamp(output, 0.0, 1.0)
    10 - max(0.0, output)
    11 - round to integer

Modifiers:
bit 0 - absolute value
bit 1 - negate