reg_shr & reg_shr_tb

module reg_shr(
   input [3:0] d,
   input shr, clk, rst_b,
   output reg [15:0] q);
always @ (posedge clk, negedge rst_b)
begin
    if (!rst_b) q <= 16'd0;
    else if (shr) q <= {d, q[15:4]};
end
endmodule

//************************************************************************************

module reg_shr_tb(
   output reg [3:0] d,
   output reg clk, rst_b, shr,
   output [15:0] q
);

reg_shr cut(.d(d), .clk(clk), .rst_b(rst_b), .shr(shr), .q(q) );

initial begin
   clk = 1'd0;
   repeat (9) #25 clk = ~clk;
end

initial begin
    rst_b = 1'd0;
    #5 rst_b = 1'd1;
    #145 rst_b = 1'd0;
    #5 rst_b = 1'd1;
end

initial begin
    shr = 1'd1;
    #100 shr = 1'd0;
    #50 shr = 1'd1;
end

initial begin
    d = 4'h0;
    #50 d = 4'ha;
    #50 d = 4'hf;
    #50 d = 4'h5;
    #50 d = 4'h8;
end
endmodule