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Aug 17th, 2019
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  1. module sram_controller(
  2.     input memoryClock,
  3.     input `SRAM_ADDR_VEC inAddr,
  4.     inout `SRAM_WORD_VEC data,
  5.     input exec,
  6.     input rw, // r = 0, w = 1
  7.    
  8.     output busy,
  9.     output ready,
  10.    
  11.     // physical interface
  12.     output `SRAM_ADDR_VEC physAddr,
  13.     inout `SRAM_WORD_VEC memData,
  14.     output oe,
  15.     output we,
  16.     output ce
  17.     );
  18.  
  19.     reg `SRAM_ADDR_VEC inAddrBuf;
  20.     reg `SRAM_WORD_VEC dataBuf;
  21.     reg rwBuf;
  22.     reg working = 0;
  23.     reg driveData = 0;
  24.     reg dataReady = 0;
  25.    
  26.     reg outEnable = 0, writeEnable = 0, chipEnable = 0; // todo init from datasheet
  27.    
  28.     always @(memoryClock) begin
  29.         if (!memoryClock) begin // falling edge
  30.             if (working) begin
  31.                 dataReady <= 0; // un-assert the old data in either case
  32.                                
  33.                 if (working && rwBuf) begin // waiting to write
  34.                     driveData <= 1; // so drive data for write
  35.                 end
  36.             end
  37.            
  38.         end
  39.         else begin // rising edge
  40.             driveData <= 0; // in any case, we don't need to drive the data to phy anymore
  41.        
  42.             if (working && !rwBuf) begin // we were waiting for read
  43.                 dataBuf <= memData; // latch the read
  44.                 dataReady <= 1;
  45.             end
  46.            
  47.             working <= exec; // if we've got an exec request this tick, we're still working
  48.            
  49.             if (!exec) begin // go idle
  50.                 chipEnable <= 0;
  51.                 outEnable <= 0;
  52.                 writeEnable <= 0;
  53.             end
  54.             else begin // we've got something to exec
  55.                 // update local buffers
  56.                 rwBuf <= rw; // capture if this is a read or write cycle
  57.                 inAddrBuf <= inAddr; // drive the address
  58.                 if (rw) dataBuf <= data;
  59.                
  60.                 // read cycle 2, write cycle 3 from the datasheet
  61.                 // both have zero required skew between O/WE and CE.
  62.                 // we wait to drive the output data in the w cycle
  63.                 // until the falling edge of the memory clock
  64.                 chipEnable <= 1; // enable chip
  65.                 outEnable <= !rw; // rw is low read, high write
  66.                 writeEnable <= rw;
  67.             end
  68.        
  69.         end
  70.     end
  71.  
  72.     assign busy = exec;
  73.     assign ready = dataReady && !rwBuf;
  74.  
  75.     assign data = (dataReady) ? dataBuf : 8'bZ;
  76.  
  77.     assign physAddr = inAddrBuf;
  78.     assign memData = (driveData) ? dataBuf : 8'bZ;
  79.  
  80.     assign oe = !outEnable;
  81.     assign we = !writeEnable;
  82.     assign ce = !chipEnable;
  83.    
  84.  
  85. endmodule
  86.  
  87.  
  88.  
  89. // ==============================================================
  90.  
  91.  
  92. module sram_controller(
  93.     input memoryClock,
  94.     input `SRAM_ADDR_VEC inAddr,
  95.     inout `SRAM_WORD_VEC data,
  96.     input exec,
  97.     input rw, // r = 0, w = 1
  98.    
  99.     output busy,
  100.     output ready,
  101.    
  102.     // physical interface
  103.     output `SRAM_ADDR_VEC physAddr,
  104.     inout `SRAM_WORD_VEC memData,
  105.     output oe,
  106.     output we,
  107.     output ce
  108.     );
  109.    
  110.     reg `SRAM_ADDR_VEC inAddrR;
  111.     reg `SRAM_WORD_VEC dataR;
  112.     reg execR;
  113.     reg rwR; // r = 0, w = 1
  114.  
  115.     assign inAddrR = inAddr;
  116.     assign dataR = data;
  117.     assign execR = exec;
  118.     assign rwR = rw;
  119.  
  120.     reg `SRAM_ADDR_VEC inAddrBuf;
  121.     reg `SRAM_WORD_VEC dataBuf;
  122.     reg rwBuf;
  123.     reg working = 0;
  124.     reg driveData = 0;
  125.     reg dataReady = 0;
  126.    
  127.     reg outEnable = 0, writeEnable = 0, chipEnable = 0; // todo init from datasheet
  128.    
  129.     always @(memoryClock) begin
  130.         if (!memoryClock) begin // falling edge
  131.             if (working) begin
  132.                 dataReady <= 0; // un-assert the old data in either case
  133.                                
  134.                 if (working && rwBuf) begin // waiting to write
  135.                     driveData <= 1; // so drive data for write
  136.                 end
  137.             end
  138.            
  139.         end
  140.         else begin // rising edge
  141.             driveData <= 0; // in any case, we don't need to drive the data to phy anymore
  142.        
  143.             if (working && !rwBuf) begin // we were waiting for read
  144.                 dataBuf <= memData; // latch the read (which the compiler says is a bad thing)
  145.                 dataReady <= 1;
  146.             end
  147.             else
  148.                 dataBuf <= 16'b0;
  149.                 dataReady <= 0;
  150.             end
  151.            
  152.             working <= exec; // if we've got an exec request this tick, we're still working
  153.            
  154.             if (!execR) begin // go idle
  155.                 chipEnable <= 0;
  156.                 outEnable <= 0;
  157.                 writeEnable <= 0;
  158.             end
  159.             else begin // we've got something to exec
  160.                 // update local buffers
  161.                 rwBuf <= rwR; // capture if this is a read or write cycle
  162.                 inAddrBuf <= inAddrR; // drive the address
  163.                 if (rw) dataBuf <= data;
  164.                
  165.                 // read cycle 2, write cycle 3 from the datasheet
  166.                 // both have zero required skew between O/WE and CE.
  167.                 // we wait to drive the output data in the w cycle
  168.                 // until the falling edge of the memory clock
  169.                 chipEnable <= 1; // enable chip
  170.                 outEnable <= !rw; // rw is low read, high write
  171.                 writeEnable <= rw;
  172.             end
  173.     end
  174.  
  175.     assign busy = exec;
  176.     assign ready = dataReady && !rwBuf;
  177.  
  178.     assign data = (dataReady) ? dataBuf : 8'bZ;
  179.  
  180.     assign physAddr = inAddrBuf;
  181.     assign memData = (driveData) ? dataBuf : 8'bZ;
  182.  
  183.     assign oe = !outEnable;
  184.     assign we = !writeEnable;
  185.     assign ce = !chipEnable;
  186.    
  187.  
  188. endmodule
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