Lab7

module Lab7(
                input CLOCK_50,
                input [3:0] KEY,
                output reg [6:0] HEX0,
                output reg [6:0] HEX1,
                output reg [6:0] HEX2
);
    wire [6:0] h0,h1,h2;
    reg [32:0] count,tenths,seconds,secd,tenthsd,t0,t2;
    reg flag, flagc;

    hex_7seg s0(tenths%10,h0);
    hex_7seg s1(seconds%10,h1);
    hex_7seg s2(seconds/10%10,h2);
    /*initial begin
        count <= 0;
        HEX0 <= 7'b1000000;
        HEX1 <= 7'b1000000;
        HEX2 <= 7'b1000000;
    end*/
    initial begin
        flag = 0;
        flagc = 1;
    end
    always @(posedge CLOCK_50) begin
        if(flag) begin
            count <= count + 1;

            if(count >= 5000000) begin
                tenths <= tenths + 1;
                if(tenths >= 10) begin
                    seconds <= seconds + 1;
                    tenths <= 0;
                end
                count <= 0;
            end
        end
        if(!KEY[0]) begin
            count <=0;
            tenths <=0;
            seconds <=0;
            flag = 0;
        end

        if(!KEY[1]) begin
            flag = 1;
            flagc = 1;
        end
        if(!KEY[2])
            flag = 0;
        if(!KEY[3]) begin
            flagc = 0;
        end

        if(flagc) begin
            HEX0 <= h0;
            HEX1 <= h1;
            HEX2 <= h2;
        end

    end


endmodule


module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = 7'b1000000;
        4'h1: seg = 7'b1111001;     // ---a----
        4'h2: seg = 7'b0100100;     // |      |
        4'h3: seg = 7'b0110000;     // f      b
        4'h4: seg = 7'b0011001;     // |      |
        4'h5: seg = 7'b0010010;     // ---g----
        4'h6: seg = 7'b0000010;     // |      |
        4'h7: seg = 7'b1111000;     // e      c
        4'h8: seg = 7'b0000000;     // |      |
        4'h9: seg = 7'b0011000;     // ---d----
        4'ha: seg = 7'b0001000;
        4'hb: seg = 7'b0000011;
        4'hc: seg = 7'b1000110;
        4'hd: seg = 7'b0100001;
        4'he: seg = 7'b0000110;
        4'hf: seg = 7'b0001110;
endcase
endmodule