if opcode == 'svshape':
    # 1.6.33 SVM-FORM from fields.txt
    # |0     |6        |11      |16    |21    |25 |26    |31  |
    # | PO   |  SVxd   |   SVyd | SVzd | SVRM |vf |   XO      |
    insn = 22 << (31-5)          # opcode 22, bits 0-5
    fields = list(map(int, fields))
    insn |= (fields[0]-1) << (31-10)  # SVxd       , bits 6-10
    insn |= (fields[1]-1) << (31-15)  # SVyd       , bits 11-15
    insn |= (fields[2]-1) << (31-20)  # SVzd       , bits 16-20
    insn |= (fields[3]) << (31-24)    # SVRM       , bits 21-24
    insn |= (fields[4]) << (31-25)    # vf         , bits 25
    insn |= 0b00001 << (31-31)        # XO         , bits 26..31
    #insn &= ((1<<32)-1)
    log("svshape", bin(insn))
    yield ".long 0x%x" % insn
    return

if opcode in ["setvl", "setvl."]:
    # 1.6.28 SVL-FORM - from fields.txt
    # |0     |6    |11    |16   |23 |24 |25 |26    |31 |
    # | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
    insn = 22 << (31-5)          # opcode 22, bits 0-5
    fields = list(map(int, fields))
    insn |= fields[0] << (31-10)  # RT       , bits 6-10
    insn |= fields[1] << (31-15)  # RA       , bits 11-15
    insn |= (fields[2]-1) << (31-22)  # SVi      , bits 16-22
    insn |= fields[3] << (31-25)  # vf       , bit  25
    insn |= fields[4] << (31-24)  # vs       , bit  24
    insn |= fields[5] << (31-23)  # ms       , bit  23
    insn |= 0b00000 << (31-30)  # XO       , bits 26..30
    if opcode == 'setvl.':
        insn |= 1 << (31-31)     # Rc=1     , bit 31
    log("setvl", bin(insn))
    yield ".long 0x%x" % insn
    return