integer                   k;
   initial
     begin
        $dumpfile("./build/iverilog/foo.vcd");
        for (k = 0; k < WIDTH + 2; k = k + 1)
          begin
             $dumpvars(0, re_pipe[k]);
             $dumpvars(0, im_pipe[k]);
             $dumpvars(0, im_c_pipe[k]);
             $dumpvars(0, re_c_pipe[k]);
          end
     end