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--
-- Title       : abcd
-- Design      : one
-- Author      : student
-- Company     : Upt
--
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--
-- File        : abcd.vhd
-- Generated   : Mon Nov 20 18:41:57 2017
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {abcd} architecture {abcd}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity abcd is
	PORT(
	a, b, c, d: in bit;
	clock, reset: in bit;
	x: out bit
	);
end abcd;

--}} End of automatically maintained section

architecture abcd of abcd is
type state is (Sa, Sb, Sc);
signal pr_state, nx_state: state;
begin
	process (reset, clock)
	begin
		if (reset='1') then
			pr_state <= Sa;
		elsif (clock'EVENT AND clock='1') then
			pr_state <= nx_state;
		end if;
	end process;
	process(d, pr_state)
	begin
		case pr_state is
			when Sa => x <= a;
			if(d = '1') then
				nx_state <= Sb;
			end if;
			when Sb => x <= b;
			if(d = '0') then
				nx_state <= Sc;
			end if;
			when Sc => x <= c;
			if(d = '1') then
				nx_state <= Sa;
			end if;
		end case;
	end process;
end abcd;