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  1. From a576378efc21973bd91fbbd01cd461a0f7e7659a Mon Sep 17 00:00:00 2001
  2. From: Insei <goodmobiledevices@gmail.com>
  3. Date: Sat, 27 May 2017 19:40:22 +0300
  4. Subject: [PATCH] sound
  5.  
  6. ---
  7. arch/arm/configs/tegra12_defconfig | 1 +
  8. arch/arm/mach-tegra/Makefile | 2 +-
  9. arch/arm/mach-tegra/board-ardbeg.c | 73 +-
  10. arch/arm/mach-tegra/board-ardbeg.h | 8 +-
  11. arch/arm/mach-tegra/common.c | 2 +-
  12. arch/arm/mach-tegra/devices.c | 6 +
  13. arch/arm/mach-tegra/devices.h | 1 +
  14. arch/arm/mach-tegra/include/mach/tegra_emc.h | 1 +
  15. arch/arm/mach-tegra/tegra12_emc.c | 4 +
  16. include/sound/core.h | 15 +-
  17. include/sound/rt5670.h | 30 +
  18. include/sound/soc-dapm.h | 8 +-
  19. include/sound/soc.h | 2 +-
  20. sound/core/pcm.c | 4 +-
  21. sound/core/pcm_lib.c | 7 +-
  22. sound/core/pcm_native.c | 3 -
  23. sound/soc/codecs/Kconfig | 8 +
  24. sound/soc/codecs/Makefile | 4 +
  25. sound/soc/codecs/rt5639.c | 2 +-
  26. sound/soc/codecs/rt5639_ioctl.c | 2 +-
  27. sound/soc/codecs/rt5640.c | 6 +-
  28. sound/soc/codecs/rt5645_ioctl.c | 2 +-
  29. sound/soc/codecs/rt5671-dsp.c | 1966 +++++++++++
  30. sound/soc/codecs/rt5671-dsp.h | 82 +
  31. sound/soc/codecs/rt5671.c | 4513 ++++++++++++++++++++++++++
  32. sound/soc/codecs/rt5671.h | 2091 ++++++++++++
  33. sound/soc/codecs/rt5671_ioctl.c | 138 +
  34. sound/soc/codecs/rt5671_ioctl.h | 45 +
  35. sound/soc/codecs/rt56xx_ioctl.c | 4 +-
  36. sound/soc/codecs/rt56xx_ioctl.h | 1 +
  37. sound/soc/codecs/rt_codec_ioctl.c | 4 +-
  38. sound/soc/codecs/spdif_transciever.c | 8 -
  39. sound/soc/codecs/tfa98xx.c | 1513 +++++++++
  40. sound/soc/codecs/tfa98xx.h | 2590 +++++++++++++++
  41. sound/soc/soc-cache.c | 4 +-
  42. sound/soc/soc-core.c | 40 +-
  43. sound/soc/soc-dapm.c | 226 +-
  44. sound/soc/soc-jack.c | 5 +-
  45. sound/soc/soc-pcm.c | 125 +-
  46. sound/soc/tegra/Kconfig | 13 +
  47. sound/soc/tegra/Makefile | 2 +
  48. sound/soc/tegra/tegra_asoc_utils.c | 40 +-
  49. sound/soc/tegra/tegra_asoc_utils.h | 1 +
  50. sound/soc/tegra/tegra_rt5671.c | 951 ++++++
  51. 44 files changed, 14303 insertions(+), 250 deletions(-)
  52. create mode 100644 include/sound/rt5670.h
  53. create mode 100644 sound/soc/codecs/rt5671-dsp.c
  54. create mode 100644 sound/soc/codecs/rt5671-dsp.h
  55. create mode 100755 sound/soc/codecs/rt5671.c
  56. create mode 100644 sound/soc/codecs/rt5671.h
  57. create mode 100644 sound/soc/codecs/rt5671_ioctl.c
  58. create mode 100644 sound/soc/codecs/rt5671_ioctl.h
  59. create mode 100644 sound/soc/codecs/tfa98xx.c
  60. create mode 100644 sound/soc/codecs/tfa98xx.h
  61. create mode 100644 sound/soc/tegra/tegra_rt5671.c
  62.  
  63. diff --git a/arch/arm/configs/tegra12_defconfig b/arch/arm/configs/tegra12_defconfig
  64. index 1ef65e6..dc0eebd 100644
  65. --- a/arch/arm/configs/tegra12_defconfig
  66. +++ b/arch/arm/configs/tegra12_defconfig
  67. @@ -580,3 +580,4 @@ CONFIG_BCMDHD_INSMOD_NO_FW_LOAD=y
  68. # Touchscreen
  69. CONFIG_INPUT_TOUCHSCREEN=y
  70. CONFIG_TOUCHSCREEN_ATMEL_MXT=y
  71. +CONFIG_SND_SOC_TEGRA_RT5671=y
  72. diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
  73. index 6d6b4a9..fe7b087 100644
  74. --- a/arch/arm/mach-tegra/Makefile
  75. +++ b/arch/arm/mach-tegra/Makefile
  76. @@ -1,7 +1,7 @@
  77. GCOV_PROFILE := y
  78.  
  79. asflags-y += -march=armv7-a
  80. -subdir-ccflags-y := -Werror
  81. +//subdir-ccflags-y := -Werror
  82.  
  83. obj-y += ahb.o
  84. obj-y += common.o
  85. diff --git a/arch/arm/mach-tegra/board-ardbeg.c b/arch/arm/mach-tegra/board-ardbeg.c
  86. index c38b262..cc07972 100644
  87. --- a/arch/arm/mach-tegra/board-ardbeg.c
  88. +++ b/arch/arm/mach-tegra/board-ardbeg.c
  89. @@ -57,6 +57,7 @@
  90. #include <media/tegra_dtv.h>
  91. #include <linux/clocksource.h>
  92. #include <linux/irqchip.h>
  93. +#include <sound/rt5670.h>
  94. #include <linux/irqchip/tegra.h>
  95. #include <linux/tegra-soc.h>
  96. #include <linux/tegra_fiq_debugger.h>
  97. @@ -99,6 +100,28 @@
  98.  
  99. static struct board_info board_info, display_board_info;
  100.  
  101. +static struct rt5670_platform_data rt5671_pdata = {
  102. + .jd_mode = 2,
  103. + .codec_gpio = TEGRA_GPIO_CDC_IRQ,
  104. + .in2_diff = true,
  105. + .in3_diff = false,
  106. + .in4_diff = true,
  107. + .bclk_32fs = {false, true, true, true},
  108. +};
  109. +
  110. +static struct i2c_board_info __initdata audio_board_info[] = {
  111. + {
  112. + I2C_BOARD_INFO("rt5671", 0x1c),
  113. + .platform_data = &rt5671_pdata,
  114. + },
  115. + {
  116. + I2C_BOARD_INFO("tfa98xx", 0x34),
  117. + },
  118. + {
  119. + I2C_BOARD_INFO("tfa98xx", 0x37),
  120. + },
  121. +};
  122. +
  123. static struct resource ardbeg_bluedroid_pm_resources[] = {
  124. [0] = {
  125. .name = "shutdown_gpio",
  126. @@ -205,6 +228,7 @@ static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
  127. { "uartb", "pll_p", 408000000, false},
  128. { "uartc", "pll_p", 408000000, false},
  129. { "uartd", "pll_p", 408000000, false},
  130. + { "audio.emc", "emc", 50000000, false},
  131. { NULL, NULL, 0, 0},
  132. };
  133.  
  134. @@ -231,10 +255,7 @@ static void ardbeg_i2c_init(void)
  135. struct board_info board_info;
  136. tegra_get_board_info(&board_info);
  137.  
  138. - if (board_info.board_id == BOARD_PM374) {
  139. - i2c_register_board_info(0, &max98090_board_info, 1);
  140. - } else if (board_info.board_id != BOARD_PM359)
  141. - i2c_register_board_info(0, &rt5639_board_info, 1);
  142. + i2c_register_board_info(0, audio_board_info, ARRAY_SIZE(audio_board_info));
  143.  
  144. if (board_info.board_id == BOARD_PM359 ||
  145. board_info.board_id == BOARD_PM358 ||
  146. @@ -276,13 +297,13 @@ static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
  147. .modem_interrupt = false,
  148. };
  149.  
  150. -static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
  151. - .gpio_hp_det = TEGRA_GPIO_HP_DET,
  152. - .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
  153. +static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5671 = {
  154. + .gpio_hp_det = -1,
  155. + .gpio_ldo1_en = -1,
  156. .gpio_spkr_en = -1,
  157. .gpio_int_mic_en = -1,
  158. .gpio_ext_mic_en = -1,
  159. - .gpio_hp_mute = -1,
  160. + .gpio_hp_mute = TEGRA_GPIO_HP_MUTE,
  161. .gpio_codec1 = -1,
  162. .gpio_codec2 = -1,
  163. .gpio_codec3 = -1,
  164. @@ -292,26 +313,12 @@ static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
  165. .i2s_mode = TEGRA_DAIFMT_I2S,
  166. .sample_size = 16,
  167. .channels = 2,
  168. - .bit_clk = 1536000,
  169. - },
  170. - .i2s_param[BT_SCO] = {
  171. - .audio_port_id = 3,
  172. - .is_i2s_master = 1,
  173. - .i2s_mode = TEGRA_DAIFMT_DSP_A,
  174. - },
  175. - .i2s_param[BASEBAND] = {
  176. - .audio_port_id = 0,
  177. - .is_i2s_master = 1,
  178. - .i2s_mode = TEGRA_DAIFMT_I2S,
  179. - .sample_size = 16,
  180. - .rate = 16000,
  181. - .channels = 2,
  182. - .bit_clk = 1024000,
  183. + .rate = 48000,
  184. },
  185. };
  186.  
  187. static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
  188. - .gpio_hp_det = NORRIN_GPIO_HP_DET,
  189. + .gpio_hp_det = -1,
  190. .gpio_ext_mic_en = TEGRA_GPIO_HP_DET,
  191. .gpio_hp_mute = -1,
  192. .edp_support = true,
  193. @@ -384,11 +391,11 @@ static void ardbeg_audio_init(void)
  194. #endif /* FIX ME! Problem in gpio pin's rt5639 */
  195. }
  196.  
  197. -static struct platform_device ardbeg_audio_device_rt5639 = {
  198. - .name = "tegra-snd-rt5639",
  199. +static struct platform_device ardbeg_audio_device_rt5671 = {
  200. + .name = "tegra-snd-rt5671",
  201. .id = 0,
  202. .dev = {
  203. - .platform_data = &ardbeg_audio_pdata_rt5639,
  204. + .platform_data = &ardbeg_audio_pdata_rt5671,
  205. },
  206. };
  207.  
  208. @@ -477,6 +484,7 @@ static struct platform_device *ardbeg_devices[] __initdata = {
  209. &tegra_i2s_device1,
  210. &tegra_i2s_device3,
  211. &tegra_i2s_device4,
  212. + &ardbeg_audio_device_rt5671,
  213. &tegra_spdif_device,
  214. &spdif_dit_device,
  215. &bluetooth_dit_device,
  216. @@ -1319,17 +1327,15 @@ static void __init tegra_ardbeg_late_init(void)
  217. #endif
  218. ardbeg_uart_init();
  219. ardbeg_usb_init();
  220. - ardbeg_modem_init();
  221. #ifdef CONFIG_TEGRA_XUSB_PLATFORM
  222. ardbeg_xusb_init();
  223. #endif
  224. ardbeg_i2c_init();
  225. - ardbeg_audio_init();
  226. platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
  227. - if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
  228. - platform_device_register(&norrin_audio_device_max98090);
  229. - else if (board_info.board_id != BOARD_PM359)
  230. - platform_device_register(&ardbeg_audio_device_rt5639);
  231. +// if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
  232. +// platform_device_register(&norrin_audio_device_max98090);
  233. +// else if (board_info.board_id != BOARD_PM359)
  234. +// platform_device_register(&ardbeg_audio_device_rt5639);
  235. tegra_io_dpd_init();
  236. if (board_info.board_id == BOARD_E2548 ||
  237. board_info.board_id == BOARD_P2530)
  238. @@ -1351,7 +1357,6 @@ static void __init tegra_ardbeg_late_init(void)
  239. loki_regulator_init();
  240. else
  241. ardbeg_regulator_init();
  242. - ardbeg_dtv_init();
  243. ardbeg_suspend_init();
  244.  
  245. if ((board_info.board_id == BOARD_PM374) ||
  246. diff --git a/arch/arm/mach-tegra/board-ardbeg.h b/arch/arm/mach-tegra/board-ardbeg.h
  247. index e72e9e7..48ee32e 100644
  248. --- a/arch/arm/mach-tegra/board-ardbeg.h
  249. +++ b/arch/arm/mach-tegra/board-ardbeg.h
  250. @@ -97,11 +97,9 @@ enum tegra_bb_type {
  251. #define TOUCH_GPIO_RST_MAXIM_STI_SPI TEGRA_GPIO_PK4
  252.  
  253. /* Audio-related GPIOs */
  254. -/*Same GPIO's used for T114(Interposer) and T124*/
  255. -/*Below GPIO's are same for Laguna and Ardbeg*/
  256. -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PH4
  257. -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7
  258. -#define NORRIN_GPIO_HP_DET TEGRA_GPIO_PI7
  259. +#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW2
  260. +#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PK2
  261. +#define TEGRA_GPIO_HP_MUTE TEGRA_GPIO_PX1
  262. /*LDO_EN signal is required only for RT5639 and not for RT5645,
  263. on Laguna the LDO_EN signal comes from a GPIO expander and
  264. this is exposed as a fixed regulator directly handeled from
  265. diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
  266. index 23ae029..2965873 100644
  267. --- a/arch/arm/mach-tegra/common.c
  268. +++ b/arch/arm/mach-tegra/common.c
  269. @@ -2374,7 +2374,7 @@ int __init tegra_soc_device_init(const char *machine)
  270. soc_dev = soc_device_register(soc_dev_attr);
  271. if (IS_ERR_OR_NULL(soc_dev)) {
  272. kfree(soc_dev_attr);
  273. - return -1;
  274. + return -EPERM;
  275. }
  276.  
  277. return 0;
  278. diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
  279. index 3b2665d..b1498ce 100644
  280. --- a/arch/arm/mach-tegra/devices.c
  281. +++ b/arch/arm/mach-tegra/devices.c
  282. @@ -1536,6 +1536,12 @@ struct platform_device baseband_dit_device = {
  283. .id = 2,
  284. };
  285.  
  286. +struct platform_device fm_dit_device = {
  287. + .name = "spdif-dit",
  288. + .id = 3,
  289. +};
  290. +
  291. +
  292. struct platform_device tegra_pcm_device = {
  293. .name = "tegra-pcm-audio",
  294. .id = -1,
  295. diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
  296. index eaba9cf..2c02b02 100644
  297. --- a/arch/arm/mach-tegra/devices.h
  298. +++ b/arch/arm/mach-tegra/devices.h
  299. @@ -80,6 +80,7 @@ extern struct platform_device tegra_das_device;
  300. extern struct platform_device spdif_dit_device;
  301. extern struct platform_device bluetooth_dit_device;
  302. extern struct platform_device baseband_dit_device;
  303. +extern struct platform_device fm_dit_device;
  304. extern struct platform_device tegra_pcm_device;
  305. extern struct platform_device tegra_tdm_pcm_device;
  306. extern struct platform_device tegra_offload_device;
  307. diff --git a/arch/arm/mach-tegra/include/mach/tegra_emc.h b/arch/arm/mach-tegra/include/mach/tegra_emc.h
  308. index 16c2208..c149c26 100644
  309. --- a/arch/arm/mach-tegra/include/mach/tegra_emc.h
  310. +++ b/arch/arm/mach-tegra/include/mach/tegra_emc.h
  311. @@ -45,6 +45,7 @@ enum emc_user_id {
  312. EMC_USER_VI2,
  313. EMC_USER_ISP1,
  314. EMC_USER_ISP2,
  315. + EMC_USER_AUDIO,
  316. EMC_USER_NUM,
  317. };
  318.  
  319. diff --git a/arch/arm/mach-tegra/tegra12_emc.c b/arch/arm/mach-tegra/tegra12_emc.c
  320. index 8e9dbe8..647d2b2 100644
  321. --- a/arch/arm/mach-tegra/tegra12_emc.c
  322. +++ b/arch/arm/mach-tegra/tegra12_emc.c
  323. @@ -102,6 +102,10 @@ static struct emc_iso_usage tegra12_emc_iso_usage[] = {
  324. 50, iso_share_calc_t124_general
  325. },
  326. {
  327. + BIT(EMC_USER_AUDIO),
  328. + 50, iso_share_calc_t124_general
  329. + },
  330. + {
  331. BIT(EMC_USER_DC1) | BIT(EMC_USER_VI),
  332. 50, iso_share_calc_t124_general
  333. },
  334. diff --git a/include/sound/core.h b/include/sound/core.h
  335. index 5bfe513..aab7626 100644
  336. --- a/include/sound/core.h
  337. +++ b/include/sound/core.h
  338. @@ -71,7 +71,7 @@ typedef int __bitwise snd_device_state_t;
  339.  
  340. typedef int __bitwise snd_device_cmd_t;
  341. #define SNDRV_DEV_CMD_PRE ((__force snd_device_cmd_t) 0)
  342. -#define SNDRV_DEV_CMD_NORMAL ((__force snd_device_cmd_t) 1)
  343. +#define SNDRV_DEV_CMD_NORMAL ((__force snd_device_cmd_t) 1)
  344. #define SNDRV_DEV_CMD_POST ((__force snd_device_cmd_t) 2)
  345.  
  346. struct snd_device;
  347. @@ -140,6 +140,8 @@ struct snd_card {
  348. unsigned int power_state; /* power state */
  349. struct mutex power_lock; /* power lock */
  350. wait_queue_head_t power_sleep;
  351. + struct task_struct *power_owner;
  352. + unsigned int power_count;
  353. #endif
  354.  
  355. #if defined(CONFIG_SND_MIXER_OSS) || defined(CONFIG_SND_MIXER_OSS_MODULE)
  356. @@ -151,12 +153,19 @@ struct snd_card {
  357. #ifdef CONFIG_PM
  358. static inline void snd_power_lock(struct snd_card *card)
  359. {
  360. - mutex_lock(&card->power_lock);
  361. + if (card->power_owner != current) {
  362. + mutex_lock(&card->power_lock);
  363. + card->power_owner = current;
  364. + }
  365. + card->power_count++;
  366. }
  367.  
  368. static inline void snd_power_unlock(struct snd_card *card)
  369. {
  370. - mutex_unlock(&card->power_lock);
  371. + if (--card->power_count == 0) {
  372. + card->power_owner = NULL;
  373. + mutex_unlock(&card->power_lock);
  374. + }
  375. }
  376.  
  377. static inline unsigned int snd_power_get_state(struct snd_card *card)
  378. diff --git a/include/sound/rt5670.h b/include/sound/rt5670.h
  379. new file mode 100644
  380. index 0000000..aa65b8d
  381. --- /dev/null
  382. +++ b/include/sound/rt5670.h
  383. @@ -0,0 +1,30 @@
  384. +/*
  385. + * linux/sound/rt5670.h -- Platform data for RT5670
  386. + *
  387. + * Copyright 2011 Realtek Microelectronics
  388. + * Copyright (C) 2016 XiaoMi, Inc.
  389. + *
  390. + * This program is free software; you can redistribute it and/or modify
  391. + * it under the terms of the GNU General Public License version 2 as
  392. + * published by the Free Software Foundation.
  393. + */
  394. +
  395. +#ifndef __LINUX_SND_RT5670_H
  396. +#define __LINUX_SND_RT5670_H
  397. +
  398. +struct rt5670_platform_data {
  399. + int jd_mode;
  400. + int codec_gpio;
  401. + /*
  402. + 0: disable,
  403. + 1: 3.3v, 2 port,
  404. + 2: 1.8v, 1 port,
  405. + 3: 3.3v, 1 port,
  406. + */
  407. + bool in2_diff;
  408. + bool in3_diff;
  409. + bool in4_diff;
  410. + bool bclk_32fs[4];
  411. +};
  412. +
  413. +#endif
  414. diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
  415. index 385c632..a1ed4e5 100644
  416. --- a/include/sound/soc-dapm.h
  417. +++ b/include/sound/soc-dapm.h
  418. @@ -368,10 +368,8 @@ int snd_soc_dapm_new_controls(struct snd_soc_dapm_context *dapm,
  419. int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
  420. struct snd_soc_dai *dai);
  421. int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card);
  422. -int snd_soc_dapm_new_pcm(struct snd_soc_card *card,
  423. - const struct snd_soc_pcm_stream *params,
  424. - struct snd_soc_dapm_widget *source,
  425. - struct snd_soc_dapm_widget *sink);
  426. +int snd_soc_dapm_new_dai_link_widgets(struct snd_soc_dapm_context *dapm,
  427. + struct snd_soc_pcm_runtime *rtd);
  428.  
  429. /* dapm path setup */
  430. int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm);
  431. @@ -512,7 +510,7 @@ struct snd_soc_dapm_widget {
  432.  
  433. void *priv; /* widget specific data */
  434. struct regulator *regulator; /* attached regulator */
  435. - const struct snd_soc_pcm_stream *params; /* params for dai links */
  436. + struct snd_soc_pcm_runtime *rtd; /* rtd for dai links */
  437.  
  438. /* dapm control */
  439. int reg; /* negative reg = no direct dapm */
  440. diff --git a/include/sound/soc.h b/include/sound/soc.h
  441. index 5bbdc65..7a9c07e 100644
  442. --- a/include/sound/soc.h
  443. +++ b/include/sound/soc.h
  444. @@ -612,7 +612,7 @@ struct snd_soc_jack_gpio {
  445. struct snd_soc_jack *jack;
  446. struct delayed_work work;
  447.  
  448. - int (*jack_status_check)(void);
  449. + int (*jack_status_check)(struct snd_soc_jack_gpio *gpio);
  450. };
  451. #endif
  452.  
  453. diff --git a/sound/core/pcm.c b/sound/core/pcm.c
  454. index e1e9e0c..314530d 100644
  455. --- a/sound/core/pcm.c
  456. +++ b/sound/core/pcm.c
  457. @@ -903,7 +903,7 @@ int snd_pcm_attach_substream(struct snd_pcm *pcm, int stream,
  458. return -EINVAL;
  459. }
  460.  
  461. - if (file->f_flags & O_APPEND) {
  462. + if (file && (file->f_flags & O_APPEND)) {
  463. if (prefer_subdevice < 0) {
  464. if (pstr->substream_count > 1)
  465. return -EINVAL; /* must be unique */
  466. @@ -965,7 +965,7 @@ int snd_pcm_attach_substream(struct snd_pcm *pcm, int stream,
  467. substream->runtime = runtime;
  468. substream->private_data = pcm->private_data;
  469. substream->ref_count = 1;
  470. - substream->f_flags = file->f_flags;
  471. + substream->f_flags = file ? file->f_flags : 0;
  472. substream->pid = get_pid(task_pid(current));
  473. pstr->substream_opened++;
  474. *rsubstream = substream;
  475. diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
  476. index 3284940..6eaeb00 100644
  477. --- a/sound/core/pcm_lib.c
  478. +++ b/sound/core/pcm_lib.c
  479. @@ -1885,12 +1885,11 @@ static int wait_for_avail(struct snd_pcm_substream *substream,
  480. if (runtime->no_period_wakeup)
  481. wait_time = MAX_SCHEDULE_TIMEOUT;
  482. else {
  483. - wait_time = 10;
  484. + wait_time = 10000;
  485. if (runtime->rate) {
  486. - long t = runtime->period_size * 2 / runtime->rate;
  487. - wait_time = max(t, wait_time);
  488. + wait_time = DIV_ROUND_UP(runtime->buffer_size * 1000, runtime->rate);
  489. }
  490. - wait_time = msecs_to_jiffies(wait_time * 1000);
  491. + wait_time = msecs_to_jiffies(wait_time);
  492. }
  493.  
  494. for (;;) {
  495. diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
  496. index f928181..df14820 100644
  497. --- a/sound/core/pcm_native.c
  498. +++ b/sound/core/pcm_native.c
  499. @@ -852,9 +852,6 @@ static int snd_pcm_pre_start(struct snd_pcm_substream *substream, int state)
  500. struct snd_pcm_runtime *runtime = substream->runtime;
  501. if (runtime->status->state != SNDRV_PCM_STATE_PREPARED)
  502. return -EBADFD;
  503. - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  504. - !snd_pcm_playback_data(substream))
  505. - return -EPIPE;
  506. runtime->trigger_master = substream;
  507. return 0;
  508. }
  509. diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
  510. index 3684f0c..55c1ff2 100644
  511. --- a/sound/soc/codecs/Kconfig
  512. +++ b/sound/soc/codecs/Kconfig
  513. @@ -62,6 +62,7 @@ config SND_SOC_ALL_CODECS
  514. select SND_SOC_RT5639 if I2C
  515. select SND_SOC_RT5640 if I2C
  516. select SND_SOC_RT5645 if I2C
  517. + select SND_SOC_RT5671 if I2C
  518. select SND_SOC_SGTL5000 if I2C
  519. select SND_SOC_SI476X if MFD_SI476X_CORE
  520. select SND_SOC_SN95031 if INTEL_SCU_IPC
  521. @@ -71,6 +72,7 @@ config SND_SOC_ALL_CODECS
  522. select SND_SOC_STA529 if I2C
  523. select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
  524. select SND_SOC_TAS5086 if I2C
  525. + select SND_SOC_TFA98XX if I2C
  526. select SND_SOC_TLV320AIC23 if I2C
  527. select SND_SOC_TLV320AIC26 if SPI_MASTER
  528. select SND_SOC_TLV320AIC32X4 if I2C
  529. @@ -316,6 +318,9 @@ config SND_SOC_RT5640
  530. config SND_SOC_RT5645
  531. tristate
  532.  
  533. +config SND_SOC_RT5671
  534. + tristate
  535. +
  536. #Freescale sgtl5000 codec
  537. config SND_SOC_SGTL5000
  538. tristate
  539. @@ -348,6 +353,9 @@ config SND_SOC_STAC9766
  540. config SND_SOC_TAS5086
  541. tristate
  542.  
  543. +config SND_SOC_TFA98XX
  544. + tristate
  545. +
  546. config SND_SOC_TLV320AIC23
  547. tristate
  548.  
  549. diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
  550. index 5d3fed8..c1519c9 100644
  551. --- a/sound/soc/codecs/Makefile
  552. +++ b/sound/soc/codecs/Makefile
  553. @@ -58,6 +58,7 @@ snd-soc-sta32x-objs := sta32x.o
  554. snd-soc-sta529-objs := sta529.o
  555. snd-soc-stac9766-objs := stac9766.o
  556. snd-soc-tas5086-objs := tas5086.o
  557. +snd-soc-tfa98xx-objs := tfa98xx.o
  558. snd-soc-tlv320aic23-objs := tlv320aic23.o
  559. snd-soc-tlv320aic26-objs := tlv320aic26.o
  560. snd-soc-tlv320aic3x-objs := tlv320aic3x.o
  561. @@ -125,6 +126,7 @@ snd-soc-wm-hubs-objs := wm_hubs.o
  562. snd-soc-rt5639-objs := rt5639.o rt56xx_ioctl.o rt5639_ioctl.o
  563. snd-soc-rt5640-objs := rt5640.o
  564. snd-soc-rt5645-objs := rt5645.o rt5645_ioctl.o rt_codec_ioctl.o
  565. +snd-soc-rt5671-objs := rt5671.o rt5671_ioctl.o rt_codec_ioctl.o rt5671-dsp.o
  566.  
  567. # Amp
  568. snd-soc-max9877-objs := max9877.o
  569. @@ -190,6 +192,7 @@ obj-$(CONFIG_SND_SOC_STA32X) += snd-soc-sta32x.o
  570. obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o
  571. obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
  572. obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
  573. +obj-$(CONFIG_SND_SOC_TFA98XX) += snd-soc-tfa98xx.o
  574. obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
  575. obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
  576. obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
  577. @@ -257,6 +260,7 @@ obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
  578. obj-$(CONFIG_SND_SOC_RT5639) += snd-soc-rt5639.o
  579. obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
  580. obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
  581. +obj-$(CONFIG_SND_SOC_RT5671) += snd-soc-rt5671.o
  582.  
  583. # Amp
  584. obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
  585. diff --git a/sound/soc/codecs/rt5639.c b/sound/soc/codecs/rt5639.c
  586. index c11dcc2..8ac8c37 100644
  587. --- a/sound/soc/codecs/rt5639.c
  588. +++ b/sound/soc/codecs/rt5639.c
  589. @@ -3131,7 +3131,7 @@ static int rt5639_probe(struct snd_soc_codec *codec)
  590. ioctl_ops->index_read = rt5639_index_read;
  591. ioctl_ops->index_update_bits = rt5639_index_update_bits;
  592. ioctl_ops->ioctl_common = rt5639_ioctl_common;
  593. - realtek_ce_init_hwdep(codec);
  594. + rt56xx_init_hwdep(codec);
  595. #endif
  596. #endif
  597.  
  598. diff --git a/sound/soc/codecs/rt5639_ioctl.c b/sound/soc/codecs/rt5639_ioctl.c
  599. index b168756..04b9a9f 100644
  600. --- a/sound/soc/codecs/rt5639_ioctl.c
  601. +++ b/sound/soc/codecs/rt5639_ioctl.c
  602. @@ -18,7 +18,7 @@
  603. #include "rt5639-dsp.h"
  604. #endif
  605.  
  606. -hweq_t hweq_param[] = {
  607. +static hweq_t hweq_param[] = {
  608. {/* NORMAL */
  609. {0},
  610. {0},
  611. diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
  612. index 65d213b..bfaed59 100644
  613. --- a/sound/soc/codecs/rt5640.c
  614. +++ b/sound/soc/codecs/rt5640.c
  615. @@ -1312,7 +1312,7 @@ static int spk_event(struct snd_soc_dapm_widget *w,
  616. }
  617.  
  618. #if USE_ONEBIT_DEPOP
  619. -void hp_amp_power(struct snd_soc_codec *codec, int on)
  620. +static void hp_amp_power(struct snd_soc_codec *codec, int on)
  621. {
  622. static int hp_amp_power_count;
  623. // printk("one bit hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
  624. @@ -1397,8 +1397,8 @@ static void rt5640_pmd_depop(struct snd_soc_codec *codec)
  625. hp_amp_power(codec, 0);
  626. }
  627.  
  628. -#else //seq
  629. -void hp_amp_power(struct snd_soc_codec *codec, int on)
  630. +#else
  631. +static void hp_amp_power(struct snd_soc_codec *codec, int on)
  632. {
  633. static int hp_amp_power_count;
  634. // printk("hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
  635. diff --git a/sound/soc/codecs/rt5645_ioctl.c b/sound/soc/codecs/rt5645_ioctl.c
  636. index 37f0b8f..c67c3de 100644
  637. --- a/sound/soc/codecs/rt5645_ioctl.c
  638. +++ b/sound/soc/codecs/rt5645_ioctl.c
  639. @@ -15,7 +15,7 @@
  640. #include "rt5645_ioctl.h"
  641. #include "rt5645.h"
  642.  
  643. -hweq_t hweq_param[] = {
  644. +static hweq_t hweq_param[] = {
  645. {/* NORMAL */
  646. {0},
  647. {0},
  648. diff --git a/sound/soc/codecs/rt5671-dsp.c b/sound/soc/codecs/rt5671-dsp.c
  649. new file mode 100644
  650. index 0000000..60bcd99
  651. --- /dev/null
  652. +++ b/sound/soc/codecs/rt5671-dsp.c
  653. @@ -0,0 +1,1966 @@
  654. +/*
  655. + * rt5671.c -- RT5671 ALSA SoC DSP driver
  656. + *
  657. + * Copyright 2011 Realtek Semiconductor Corp.
  658. + * Copyright (C) 2016 XiaoMi, Inc.
  659. + * Author: Johnny Hsu <johnnyhsu@realtek.com>
  660. + *
  661. + * This program is free software; you can redistribute it and/or modify
  662. + * it under the terms of the GNU General Public License version 2 as
  663. + * published by the Free Software Foundation.
  664. + */
  665. +
  666. +#include <linux/delay.h>
  667. +#include <linux/i2c.h>
  668. +#include <linux/platform_device.h>
  669. +#include <sound/soc.h>
  670. +#include <sound/soc-dapm.h>
  671. +
  672. +#define RTK_IOCTL
  673. +#ifdef RTK_IOCTL
  674. +#include <linux/spi/spi.h>
  675. +#include "rt_codec_ioctl.h"
  676. +#endif
  677. +
  678. +#include "rt5671.h"
  679. +#include "rt5671-dsp.h"
  680. +
  681. +#define DSP_CLK_RATE RT5671_DSP_CLK_96K
  682. +
  683. +static unsigned short rt5671_dsp_init_patch_code[][2] = {
  684. + {0xe1, 0x0010}, {0xe2, 0x0000}, {0xe0, 0x6ac9},
  685. + {0xe1, 0x0064}, {0xe2, 0x0000}, {0xe0, 0x68c5},
  686. + {0xe1, 0x3f00}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  687. + {0xe1, 0x3f01}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  688. + {0xe1, 0x3f02}, {0xe2, 0x830f}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  689. + {0xe1, 0x3f03}, {0xe2, 0x9301}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  690. + {0xe1, 0x3f04}, {0xe2, 0x81cc}, {0xe3, 0x008c}, {0xe0, 0x0dcf},
  691. + {0xe1, 0x3f05}, {0xe2, 0x4009}, {0xe3, 0x000a}, {0xe0, 0x0dcf},
  692. + {0xe1, 0x3f06}, {0xe2, 0x267c}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  693. + {0xe1, 0x3f07}, {0xe2, 0x23a2}, {0xe3, 0x00d0}, {0xe0, 0x0dcf},
  694. + {0xe1, 0x3f08}, {0xe2, 0x9212}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  695. + {0xe1, 0x3f09}, {0xe2, 0x93ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  696. + {0xe1, 0x3f0a}, {0xe2, 0x83ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  697. + {0xe1, 0x3f0b}, {0xe2, 0x278a}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  698. + {0xe1, 0x3f0c}, {0xe2, 0x1bf0}, {0xe3, 0x00a1}, {0xe0, 0x0dcf},
  699. + {0xe1, 0x3f0d}, {0xe2, 0x8212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  700. + {0xe1, 0x3f0e}, {0xe2, 0x9301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  701. + {0xe1, 0x3f0f}, {0xe2, 0x81cc}, {0xe3, 0x008c}, {0xe0, 0x0dcf},
  702. + {0xe1, 0x3f10}, {0xe2, 0x1918}, {0xe3, 0x004f}, {0xe0, 0x0dcf},
  703. + {0xe1, 0x3f11}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  704. + {0xe1, 0x3f12}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  705. + {0xe1, 0x3f13}, {0xe2, 0x830f}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  706. + {0xe1, 0x3f14}, {0xe2, 0x9301}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  707. + {0xe1, 0x3f15}, {0xe2, 0x8212}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  708. + {0xe1, 0x3f16}, {0xe2, 0x93ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  709. + {0xe1, 0x3f17}, {0xe2, 0x83ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  710. + {0xe1, 0x3f18}, {0xe2, 0x278a}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  711. + {0xe1, 0x3f19}, {0xe2, 0x1bf1}, {0xe3, 0x0071}, {0xe0, 0x0dcf},
  712. + {0xe1, 0x3f1a}, {0xe2, 0x8212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  713. + {0xe1, 0x3f1b}, {0xe2, 0x9301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  714. + {0xe1, 0x3f1c}, {0xe2, 0x8117}, {0xe3, 0x00e5}, {0xe0, 0x0dcf},
  715. + {0xe1, 0x3f1d}, {0xe2, 0x191b}, {0xe3, 0x004f}, {0xe0, 0x0dcf},
  716. + {0xe1, 0x3f1e}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  717. + {0xe1, 0x3f1f}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  718. + {0xe1, 0x3f20}, {0xe2, 0x830f}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  719. + {0xe1, 0x3f21}, {0xe2, 0x9301}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  720. + {0xe1, 0x3f22}, {0xe2, 0x8212}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  721. + {0xe1, 0x3f23}, {0xe2, 0x93ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  722. + {0xe1, 0x3f24}, {0xe2, 0x83ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  723. + {0xe1, 0x3f25}, {0xe2, 0x278a}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  724. + {0xe1, 0x3f26}, {0xe2, 0x1bf2}, {0xe3, 0x0041}, {0xe0, 0x0dcf},
  725. + {0xe1, 0x3f27}, {0xe2, 0x8212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  726. + {0xe1, 0x3f28}, {0xe2, 0x9301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  727. + {0xe1, 0x3f29}, {0xe2, 0x8117}, {0xe3, 0x00e5}, {0xe0, 0x0dcf},
  728. + {0xe1, 0x3f2a}, {0xe2, 0x1921}, {0xe3, 0x007f}, {0xe0, 0x0dcf},
  729. + {0xe1, 0x3f2b}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  730. + {0xe1, 0x3f2c}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  731. + {0xe1, 0x3f2d}, {0xe2, 0x8307}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  732. + {0xe1, 0x3f2e}, {0xe2, 0x9301}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  733. + {0xe1, 0x3f2f}, {0xe2, 0x81cc}, {0xe3, 0x008c}, {0xe0, 0x0dcf},
  734. + {0xe1, 0x3f30}, {0xe2, 0x4009}, {0xe3, 0x000a}, {0xe0, 0x0dcf},
  735. + {0xe1, 0x3f31}, {0xe2, 0x267c}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  736. + {0xe1, 0x3f32}, {0xe2, 0x23a2}, {0xe3, 0x00d0}, {0xe0, 0x0dcf},
  737. + {0xe1, 0x3f33}, {0xe2, 0x9212}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  738. + {0xe1, 0x3f34}, {0xe2, 0x93ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  739. + {0xe1, 0x3f35}, {0xe2, 0x83ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  740. + {0xe1, 0x3f36}, {0xe2, 0x278a}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  741. + {0xe1, 0x3f37}, {0xe2, 0x1bf3}, {0xe3, 0x0051}, {0xe0, 0x0dcf},
  742. + {0xe1, 0x3f38}, {0xe2, 0x8212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  743. + {0xe1, 0x3f39}, {0xe2, 0x9301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  744. + {0xe1, 0x3f3a}, {0xe2, 0x81cc}, {0xe3, 0x008c}, {0xe0, 0x0dcf},
  745. + {0xe1, 0x3f3b}, {0xe2, 0x3400}, {0xe3, 0x004e}, {0xe0, 0x0dcf},
  746. + {0xe1, 0x3f3c}, {0xe2, 0x1a09}, {0xe3, 0x00ef}, {0xe0, 0x0dcf},
  747. + {0xe1, 0x3f3d}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  748. + {0xe1, 0x3f3e}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  749. + {0xe1, 0x3f3f}, {0xe2, 0x8307}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  750. + {0xe1, 0x3f40}, {0xe2, 0x9301}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  751. + {0xe1, 0x3f41}, {0xe2, 0x8212}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  752. + {0xe1, 0x3f42}, {0xe2, 0x93ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  753. + {0xe1, 0x3f43}, {0xe2, 0x83ff}, {0xe3, 0x00ea}, {0xe0, 0x0dcf},
  754. + {0xe1, 0x3f44}, {0xe2, 0x278a}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  755. + {0xe1, 0x3f45}, {0xe2, 0x1bf4}, {0xe3, 0x0031}, {0xe0, 0x0dcf},
  756. + {0xe1, 0x3f46}, {0xe2, 0x8212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
  757. + {0xe1, 0x3f47}, {0xe2, 0x9301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  758. + {0xe1, 0x3f48}, {0xe2, 0x8117}, {0xe3, 0x00e5}, {0xe0, 0x0dcf},
  759. + {0xe1, 0x3f49}, {0xe2, 0x3400}, {0xe3, 0x004e}, {0xe0, 0x0dcf},
  760. + {0xe1, 0x3f4a}, {0xe2, 0x1a0c}, {0xe3, 0x00ef}, {0xe0, 0x0dcf},
  761. + {0xe1, 0x3f4b}, {0xe2, 0x8301}, {0xe3, 0x00f8}, {0xe0, 0x0dcf},
  762. + {0xe1, 0x3f4c}, {0xe2, 0x9212}, {0xe3, 0x0098}, {0xe0, 0x0dcf},
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  933. + {0xe1, 0x3f0b}, {0xe2, 0x90f5}, {0xe3, 0x00bc}, {0xe0, 0x0dcf},
  934. + {0xe1, 0x3f0c}, {0xe2, 0x8101}, {0xe3, 0x00b3}, {0xe0, 0x0dcf},
  935. + {0xe1, 0x3f0d}, {0xe2, 0x2029}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  936. + {0xe1, 0x3f0e}, {0xe2, 0x9101}, {0xe3, 0x00bc}, {0xe0, 0x0dcf},
  937. + {0xe1, 0x3f0f}, {0xe2, 0x0c30}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  938. + {0xe1, 0x3f10}, {0xe2, 0x198e}, {0xe3, 0x009f}, {0xe0, 0x0dcf},
  939. + {0xe1, 0x3f11}, {0xe2, 0x9433}, {0xe3, 0x0006}, {0xe0, 0x0dcf},
  940. + {0xe1, 0x3f12}, {0xe2, 0x9433}, {0xe3, 0x0016}, {0xe0, 0x0dcf},
  941. + {0xe1, 0x3f13}, {0xe2, 0x4001}, {0xe3, 0x009a}, {0xe0, 0x0dcf},
  942. + {0xe1, 0x3f14}, {0xe2, 0x9033}, {0xe3, 0x002a}, {0xe0, 0x0dcf},
  943. + {0xe1, 0x3f15}, {0xe2, 0x3527}, {0xe3, 0x0041}, {0xe0, 0x0dcf},
  944. + {0xe1, 0x3f16}, {0xe2, 0x3527}, {0xe3, 0x0012}, {0xe0, 0x0dcf},
  945. + {0xe1, 0x3f17}, {0xe2, 0x3527}, {0xe3, 0x0070}, {0xe0, 0x0dcf},
  946. + {0xe1, 0x3f18}, {0xe2, 0x3c00}, {0xe3, 0x00c5}, {0xe0, 0x0dcf},
  947. + {0xe1, 0x3f19}, {0xe2, 0x0c0c}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  948. + {0xe1, 0x3f1a}, {0xe2, 0x17f2}, {0xe3, 0x00ee}, {0xe0, 0x0dcf},
  949. + {0xe1, 0x3f1b}, {0xe2, 0x6000}, {0xe3, 0x00a5}, {0xe0, 0x0dcf},
  950. + {0xe1, 0x3f1c}, {0xe2, 0x22fa}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  951. + {0xe1, 0x3f1d}, {0xe2, 0x6000}, {0xe3, 0x0049}, {0xe0, 0x0dcf},
  952. + {0xe1, 0x3f1e}, {0xe2, 0x66e2}, {0xe3, 0x0051}, {0xe0, 0x0dcf},
  953. + {0xe1, 0x3f1f}, {0xe2, 0x1bf2}, {0xe3, 0x00c3}, {0xe0, 0x0dcf},
  954. + {0xe1, 0x3f20}, {0xe2, 0x26ea}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  955. + {0xe1, 0x3f21}, {0xe2, 0x1bf2}, {0xe3, 0x00c3}, {0xe0, 0x0dcf},
  956. + {0xe1, 0x3f22}, {0xe2, 0x8033}, {0xe3, 0x001a}, {0xe0, 0x0dcf},
  957. + {0xe1, 0x3f23}, {0xe2, 0x2262}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  958. + {0xe1, 0x3f24}, {0xe2, 0x8033}, {0xe3, 0x0024}, {0xe0, 0x0dcf},
  959. + {0xe1, 0x3f25}, {0xe2, 0x26e2}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  960. + {0xe1, 0x3f26}, {0xe2, 0x1bf2}, {0xe3, 0x00a0}, {0xe0, 0x0dcf},
  961. + {0xe1, 0x3f27}, {0xe2, 0x8033}, {0xe3, 0x000a}, {0xe0, 0x0dcf},
  962. + {0xe1, 0x3f28}, {0xe2, 0x2262}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  963. + {0xe1, 0x3f29}, {0xe2, 0x9033}, {0xe3, 0x000a}, {0xe0, 0x0dcf},
  964. + {0xe1, 0x3f2a}, {0xe2, 0x8033}, {0xe3, 0x002a}, {0xe0, 0x0dcf},
  965. + {0xe1, 0x3f2b}, {0xe2, 0x9033}, {0xe3, 0x001a}, {0xe0, 0x0dcf},
  966. + {0xe1, 0x3f2c}, {0xe2, 0x8033}, {0xe3, 0x002a}, {0xe0, 0x0dcf},
  967. + {0xe1, 0x3f2d}, {0xe2, 0x2262}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  968. + {0xe1, 0x3f2e}, {0xe2, 0x9033}, {0xe3, 0x002a}, {0xe0, 0x0dcf},
  969. + {0xe1, 0x3f2f}, {0xe2, 0x0c08}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  970. + {0xe1, 0x3f30}, {0xe2, 0x82f5}, {0xe3, 0x0060}, {0xe0, 0x0dcf},
  971. + {0xe1, 0x3f31}, {0xe2, 0x2398}, {0xe3, 0x005f}, {0xe0, 0x0dcf},
  972. + {0xe1, 0x3f32}, {0xe2, 0x1bf4}, {0xe3, 0x0020}, {0xe0, 0x0dcf},
  973. + {0xe1, 0x3f33}, {0xe2, 0x8033}, {0xe3, 0x000a}, {0xe0, 0x0dcf},
  974. + {0xe1, 0x3f34}, {0xe2, 0x8033}, {0xe3, 0x0054}, {0xe0, 0x0dcf},
  975. + {0xe1, 0x3f35}, {0xe2, 0x26e2}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  976. + {0xe1, 0x3f36}, {0xe2, 0x1bf3}, {0xe3, 0x00e5}, {0xe0, 0x0dcf},
  977. + {0xe1, 0x3f37}, {0xe2, 0x8033}, {0xe3, 0x003a}, {0xe0, 0x0dcf},
  978. + {0xe1, 0x3f38}, {0xe2, 0x22e2}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  979. + {0xe1, 0x3f39}, {0xe2, 0x9033}, {0xe3, 0x003a}, {0xe0, 0x0dcf},
  980. + {0xe1, 0x3f3a}, {0xe2, 0x1bf4}, {0xe3, 0x0022}, {0xe0, 0x0dcf},
  981. + {0xe1, 0x3f3b}, {0xe2, 0x9433}, {0xe3, 0x0036}, {0xe0, 0x0dcf},
  982. + {0xe1, 0x3f3c}, {0xe2, 0x9433}, {0xe3, 0x0046}, {0xe0, 0x0dcf},
  983. + {0xe1, 0x3f3d}, {0xe2, 0x1bf4}, {0xe3, 0x002f}, {0xe0, 0x0dcf},
  984. + {0xe1, 0x3f3e}, {0xe2, 0x4100}, {0xe3, 0x0014}, {0xe0, 0x0dcf},
  985. + {0xe1, 0x3f3f}, {0xe2, 0x9033}, {0xe3, 0x0044}, {0xe0, 0x0dcf},
  986. + {0xe1, 0x3f40}, {0xe2, 0x4001}, {0xe3, 0x0044}, {0xe0, 0x0dcf},
  987. + {0xe1, 0x3f41}, {0xe2, 0x9033}, {0xe3, 0x0034}, {0xe0, 0x0dcf},
  988. + {0xe1, 0x3f42}, {0xe2, 0x3c00}, {0xe3, 0x0075}, {0xe0, 0x0dcf},
  989. + {0xe1, 0x3f43}, {0xe2, 0x192f}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  990. + {0xe1, 0x3f44}, {0xe2, 0x82f5}, {0xe3, 0x0060}, {0xe0, 0x0dcf},
  991. + {0xe1, 0x3f45}, {0xe2, 0x2398}, {0xe3, 0x005f}, {0xe0, 0x0dcf},
  992. + {0xe1, 0x3f46}, {0xe2, 0x1bf5}, {0xe3, 0x0050}, {0xe0, 0x0dcf},
  993. + {0xe1, 0x3f47}, {0xe2, 0x8033}, {0xe3, 0x004a}, {0xe0, 0x0dcf},
  994. + {0xe1, 0x3f48}, {0xe2, 0x267a}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  995. + {0xe1, 0x3f49}, {0xe2, 0x1bf5}, {0xe3, 0x0050}, {0xe0, 0x0dcf},
  996. + {0xe1, 0x3f4a}, {0xe2, 0x82f5}, {0xe3, 0x005a}, {0xe0, 0x0dcf},
  997. + {0xe1, 0x3f4b}, {0xe2, 0x267a}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  998. + {0xe1, 0x3f4c}, {0xe2, 0x4001}, {0xe3, 0x006a}, {0xe0, 0x0dcf},
  999. + {0xe1, 0x3f4d}, {0xe2, 0x4001}, {0xe3, 0x00f1}, {0xe0, 0x0dcf},
  1000. + {0xe1, 0x3f4e}, {0xe2, 0x2279}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1001. + {0xe1, 0x3f4f}, {0xe2, 0x0d04}, {0xe3, 0x007a}, {0xe0, 0x0dcf},
  1002. + {0xe1, 0x3f50}, {0xe2, 0x3549}, {0xe3, 0x00b1}, {0xe0, 0x0dcf},
  1003. + {0xe1, 0x3f51}, {0xe2, 0x0900}, {0xe3, 0x0007}, {0xe0, 0x0dcf},
  1004. + {0xe1, 0x3f52}, {0xe2, 0xa7ff}, {0xe3, 0x00f5}, {0xe0, 0x0dcf},
  1005. + {0xe1, 0x3f53}, {0xe2, 0xa7ff}, {0xe3, 0x00f5}, {0xe0, 0x0dcf},
  1006. + {0xe1, 0x3f54}, {0xe2, 0xa7ff}, {0xe3, 0x00f5}, {0xe0, 0x0dcf},
  1007. + {0xe1, 0x3f55}, {0xe2, 0x3949}, {0xe3, 0x00b0}, {0xe0, 0x0dcf},
  1008. + {0xe1, 0x3f56}, {0xe2, 0x1984}, {0xe3, 0x003f}, {0xe0, 0x0dcf},
  1009. + {0xe1, 0x3f57}, {0xe2, 0x82b6}, {0xe3, 0x0061}, {0xe0, 0x0dcf},
  1010. + {0xe1, 0x3f58}, {0xe2, 0x17f8}, {0xe3, 0x006e}, {0xe0, 0x0dcf},
  1011. + {0xe1, 0x3f59}, {0xe2, 0x8291}, {0xe3, 0x006a}, {0xe0, 0x0dcf},
  1012. + {0xe1, 0x3f5a}, {0xe2, 0x602a}, {0xe3, 0x0065}, {0xe0, 0x0dcf},
  1013. + {0xe1, 0x3f5b}, {0xe2, 0x2084}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1014. + {0xe1, 0x3f5c}, {0xe2, 0x0d00}, {0xe3, 0x00fc}, {0xe0, 0x0dcf},
  1015. + {0xe1, 0x3f5d}, {0xe2, 0x0d00}, {0xe3, 0x00eb}, {0xe0, 0x0dcf},
  1016. + {0xe1, 0x3f5e}, {0xe2, 0x2058}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1017. + {0xe1, 0x3f5f}, {0xe2, 0x1067}, {0xe3, 0x00be}, {0xe0, 0x0dcf},
  1018. + {0xe1, 0x3f60}, {0xe2, 0x1073}, {0xe3, 0x0087}, {0xe0, 0x0dcf},
  1019. + {0xe1, 0x3f61}, {0xe2, 0x1047}, {0xe3, 0x00a9}, {0xe0, 0x0dcf},
  1020. + {0xe1, 0x3f62}, {0xe2, 0x0e5b}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1021. + {0xe1, 0x3f63}, {0xe2, 0x2262}, {0xe3, 0x009f}, {0xe0, 0x0dcf},
  1022. + {0xe1, 0x3f64}, {0xe2, 0x902f}, {0xe3, 0x009f}, {0xe0, 0x0dcf},
  1023. + {0xe1, 0x3f65}, {0xe2, 0x902f}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  1024. + {0xe1, 0x3f66}, {0xe2, 0x1c95}, {0xe3, 0x00cf}, {0xe0, 0x0dcf},
  1025. + {0xe1, 0x3f67}, {0xe2, 0x1c50}, {0xe3, 0x00cf}, {0xe0, 0x0dcf},
  1026. + {0xe1, 0x3f68}, {0xe2, 0x0f22}, {0xe3, 0x00ff}, {0xe0, 0x0dcf},
  1027. + {0xe1, 0x3f69}, {0xe2, 0x802f}, {0xe3, 0x009a}, {0xe0, 0x0dcf},
  1028. + {0xe1, 0x3f6a}, {0xe2, 0x0d00}, {0xe3, 0x005f}, {0xe0, 0x0dcf},
  1029. + {0xe1, 0x3f6b}, {0xe2, 0x4000}, {0xe3, 0x0004}, {0xe0, 0x0dcf},
  1030. + {0xe1, 0x3f6c}, {0xe2, 0x060a}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1031. + {0xe1, 0x3f6d}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1032. + {0xe1, 0x3f6e}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1033. + {0xe1, 0x3f6f}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1034. + {0xe1, 0x3f70}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1035. + {0xe1, 0x3f71}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1036. + {0xe1, 0x3f72}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1037. + {0xe1, 0x3f73}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1038. + {0xe1, 0x3f74}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1039. + {0xe1, 0x3f75}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1040. + {0xe1, 0x3f76}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1041. + {0xe1, 0x3f77}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1042. + {0xe1, 0x3f78}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1043. + {0xe1, 0x3f79}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1044. + {0xe1, 0x3f7a}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1045. + {0xe1, 0x3f7b}, {0xe2, 0x0712}, {0xe3, 0x0000}, {0xe0, 0x0dcf},
  1046. + {0xe1, 0x3f7c}, {0xe2, 0x802f}, {0xe3, 0x00aa}, {0xe0, 0x0dcf},
  1047. + {0xe1, 0x3f7d}, {0xe2, 0x2b3a}, {0xe3, 0x00b4}, {0xe0, 0x0dcf},
  1048. + {0xe1, 0x3f7e}, {0xe2, 0x2262}, {0xe3, 0x001f}, {0xe0, 0x0dcf},
  1049. + {0xe1, 0x3f7f}, {0xe2, 0x0d00}, {0xe3, 0x009a}, {0xe0, 0x0dcf},
  1050. + {0xe1, 0x3f80}, {0xe2, 0x1023}, {0xe3, 0x0061}, {0xe0, 0x0dcf},
  1051. + {0xe1, 0x3f81}, {0xe2, 0x2027}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1052. + {0xe1, 0x3f82}, {0xe2, 0x428b}, {0xe3, 0x00e6}, {0xe0, 0x0dcf},
  1053. + {0xe1, 0x3f83}, {0xe2, 0x2024}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1054. + {0xe1, 0x3f84}, {0xe2, 0x82b7}, {0xe3, 0x0084}, {0xe0, 0x0dcf},
  1055. + {0xe1, 0x3f85}, {0xe2, 0x2b24}, {0xe3, 0x0078}, {0xe0, 0x0dcf},
  1056. + {0xe1, 0x3f86}, {0xe2, 0x92b7}, {0xe3, 0x008a}, {0xe0, 0x0dcf},
  1057. + {0xe1, 0x3f87}, {0xe2, 0x1a20}, {0xe3, 0x007f}, {0xe0, 0x0dcf},
  1058. + {0xe1, 0x3f88}, {0xe2, 0x47ff}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  1059. + {0xe1, 0x3f89}, {0xe2, 0x92b5}, {0xe3, 0x00fa}, {0xe0, 0x0dcf},
  1060. + {0xe1, 0x3f8a}, {0xe2, 0x356d}, {0xe3, 0x00b1}, {0xe0, 0x0dcf},
  1061. + {0xe1, 0x3f8b}, {0xe2, 0x19e4}, {0xe3, 0x000f}, {0xe0, 0x0dcf},
  1062. + {0xe1, 0x0064}, {0xe2, 0x0000}, {0xe0, 0x68c5},
  1063. + {0xe1, 0x3fa0}, {0xe2, 0x9248}, {0xe0, 0x3bcb},
  1064. + {0xe1, 0x3fb0}, {0xe2, 0x3f00}, {0xe0, 0x3bcb},
  1065. + {0xe1, 0x3fa1}, {0xe2, 0x98e2}, {0xe0, 0x3bcb},
  1066. + {0xe1, 0x3fb1}, {0xe2, 0x3f02}, {0xe0, 0x3bcb},
  1067. + {0xe1, 0x3fa2}, {0xe2, 0x92f0}, {0xe0, 0x3bcb},
  1068. + {0xe1, 0x3fb2}, {0xe2, 0x3f11}, {0xe0, 0x3bcb},
  1069. + {0xe1, 0x3fa3}, {0xe2, 0x9842}, {0xe0, 0x3bcb},
  1070. + {0xe1, 0x3fb3}, {0xe2, 0x3f44}, {0xe0, 0x3bcb},
  1071. + {0xe1, 0x0335}, {0xe2, 0x0001}, {0xe0, 0x3bcb},
  1072. + {0xe1, 0x3fa4}, {0xe2, 0xa1d6}, {0xe0, 0x3bcb},
  1073. + {0xe1, 0x3fb4}, {0xe2, 0x3f57}, {0xe0, 0x3bcb},
  1074. + {0xe1, 0x3fa5}, {0xe2, 0x9e3f}, {0xe0, 0x3bcb},
  1075. + {0xe1, 0x3fb5}, {0xe2, 0x3f88}, {0xe0, 0x3bcb},
  1076. + {0xe1, 0x0010}, {0xe2, 0x0000}, {0xe0, 0x6ac9},
  1077. +};
  1078. +#define RT5671_DSP_INIT_PATCH_NUM \
  1079. + (sizeof(rt5671_dsp_init_patch_code) / sizeof(rt5671_dsp_init_patch_code[0]))
  1080. +
  1081. +static unsigned short rt5671_dsp_reset_patch_code[][2] = {
  1082. + {0xe1, 0x0010}, {0xe2, 0x0000}, {0xe0, 0x6ac9},
  1083. + {0xe1, 0x0064}, {0xe2, 0x0000}, {0xe0, 0x68c5},
  1084. + {0xe1, 0x3fa0}, {0xe2, 0x9183}, {0xe0, 0x3bcb},
  1085. + {0xe1, 0x3fb0}, {0xe2, 0x3f00}, {0xe0, 0x3bcb},
  1086. + {0xe1, 0x3fa1}, {0xe2, 0x91b3}, {0xe0, 0x3bcb},
  1087. + {0xe1, 0x3fb1}, {0xe2, 0x3f11}, {0xe0, 0x3bcb},
  1088. + {0xe1, 0x3fa2}, {0xe2, 0x9216}, {0xe0, 0x3bcb},
  1089. + {0xe1, 0x3fb2}, {0xe2, 0x3f1e}, {0xe0, 0x3bcb},
  1090. + {0xe1, 0x3fa3}, {0xe2, 0xe09d}, {0xe0, 0x3bcb},
  1091. + {0xe1, 0x3fb3}, {0xe2, 0x3f2b}, {0xe0, 0x3bcb},
  1092. + {0xe1, 0x3fa4}, {0xe2, 0xe0cd}, {0xe0, 0x3bcb},
  1093. + {0xe1, 0x3fb4}, {0xe2, 0x3f3d}, {0xe0, 0x3bcb},
  1094. + {0xe1, 0x3fa5}, {0xe2, 0xe130}, {0xe0, 0x3bcb},
  1095. + {0xe1, 0x3fb5}, {0xe2, 0x3f4b}, {0xe0, 0x3bcb},
  1096. + {0xe1, 0x3fa6}, {0xe2, 0x859a}, {0xe0, 0x3bcb},
  1097. + {0xe1, 0x3fb6}, {0xe2, 0x3f59}, {0xe0, 0x3bcb},
  1098. + {0xe1, 0x3fa7}, {0xe2, 0x94fc}, {0xe0, 0x3bcb},
  1099. + {0xe1, 0x3fb7}, {0xe2, 0x3f62}, {0xe0, 0x3bcb},
  1100. + {0xe1, 0x3fa8}, {0xe2, 0x93c9}, {0xe0, 0x3bcb},
  1101. + {0xe1, 0x3fb8}, {0xe2, 0x3f71}, {0xe0, 0x3bcb},
  1102. + {0xe1, 0x3fa9}, {0xe2, 0x94f2}, {0xe0, 0x3bcb},
  1103. + {0xe1, 0x3fb9}, {0xe2, 0x3fa4}, {0xe0, 0x3bcb},
  1104. + {0xe1, 0x22cc}, {0xe2, 0x0001}, {0xe0, 0x3bcb},
  1105. + {0xe1, 0x3faa}, {0xe2, 0x823a}, {0xe0, 0x3bcb},
  1106. + {0xe1, 0x3fba}, {0xe2, 0x023e}, {0xe0, 0x3bcb},
  1107. + {0xe1, 0x3fab}, {0xe2, 0x8351}, {0xe0, 0x3bcb},
  1108. + {0xe1, 0x3fbb}, {0xe2, 0x0355}, {0xe0, 0x3bcb},
  1109. + {0xe1, 0x3fac}, {0xe2, 0x838d}, {0xe0, 0x3bcb},
  1110. + {0xe1, 0x3fbc}, {0xe2, 0x0391}, {0xe0, 0x3bcb},
  1111. + {0xe1, 0x3fad}, {0xe2, 0x8342}, {0xe0, 0x3bcb},
  1112. + {0xe1, 0x3fbd}, {0xe2, 0x0346}, {0xe0, 0x3bcb},
  1113. + {0xe1, 0x3fae}, {0xe2, 0x8382}, {0xe0, 0x3bcb},
  1114. + {0xe1, 0x3fbe}, {0xe2, 0x0386}, {0xe0, 0x3bcb},
  1115. + {0xe1, 0x3faf}, {0xe2, 0x831c}, {0xe0, 0x3bcb},
  1116. + {0xe1, 0x3fbf}, {0xe2, 0x3fb7}, {0xe0, 0x3bcb},
  1117. +
  1118. + {0xe1, 0x0010}, {0xe2, 0x0001}, {0xe0, 0x6ac9},
  1119. + {0xe1, 0x0064}, {0xe2, 0x0000}, {0xe0, 0x68c5},
  1120. + {0xe1, 0x3fa0}, {0xe2, 0x9248}, {0xe0, 0x3bcb},
  1121. + {0xe1, 0x3fb0}, {0xe2, 0x3f00}, {0xe0, 0x3bcb},
  1122. + {0xe1, 0x3fa1}, {0xe2, 0x98e2}, {0xe0, 0x3bcb},
  1123. + {0xe1, 0x3fb1}, {0xe2, 0x3f02}, {0xe0, 0x3bcb},
  1124. + {0xe1, 0x3fa2}, {0xe2, 0x92f0}, {0xe0, 0x3bcb},
  1125. + {0xe1, 0x3fb2}, {0xe2, 0x3f11}, {0xe0, 0x3bcb},
  1126. + {0xe1, 0x3fa3}, {0xe2, 0x9842}, {0xe0, 0x3bcb},
  1127. + {0xe1, 0x3fb3}, {0xe2, 0x3f44}, {0xe0, 0x3bcb},
  1128. + {0xe1, 0x0335}, {0xe2, 0x0001}, {0xe0, 0x3bcb},
  1129. + {0xe1, 0x3fa4}, {0xe2, 0xa1d6}, {0xe0, 0x3bcb},
  1130. + {0xe1, 0x3fb4}, {0xe2, 0x3f57}, {0xe0, 0x3bcb},
  1131. + {0xe1, 0x3fa5}, {0xe2, 0x9e3f}, {0xe0, 0x3bcb},
  1132. + {0xe1, 0x3fb5}, {0xe2, 0x3f88}, {0xe0, 0x3bcb},
  1133. + {0xe1, 0x0010}, {0xe2, 0x0000}, {0xe0, 0x6ac9},
  1134. +};
  1135. +#define RT5671_DSP_RESET_PATCH_NUM \
  1136. + (sizeof(rt5671_dsp_reset_patch_code) / sizeof(rt5671_dsp_reset_patch_code[0]))
  1137. +
  1138. +/* DSP init */
  1139. +static unsigned short rt5671_dsp_init[][2] = {
  1140. + {0x2260, 0x30d9}, {0x2260, 0x30d9}, /*{0x2261, 0x30d9},*/ {0x2289, 0x7fff}, {0x2290, 0x7fff},
  1141. + {0x2288, 0x0002}, {0x22b2, 0x0002}, {0x2295, 0x0001}, {0x22b3, 0x0001},
  1142. + /*{0x22d7, 0x0008}, {0x22d8, 0x0009},*/ {0x22d9, 0x0000}, {0x22da, 0x0001},
  1143. + {0x22fd, 0x001e}, {0x22c1, 0x1006}, {0x22c2, 0x1006}, {0x22c3, 0x1007},
  1144. + {0x22c4, 0x1007}
  1145. +};
  1146. +#define RT5671_DSP_INIT_NUM \
  1147. + (sizeof(rt5671_dsp_init) / sizeof(rt5671_dsp_init[0]))
  1148. +
  1149. +/* Data Source */
  1150. +#define RT5671_DSP_TDM_SRC_PAR_NUM 5
  1151. +
  1152. +static unsigned short rt5671_dsp_data_src[][2] = {
  1153. + /*For Stereo ADC mixer*/
  1154. + {0x2261, 0x30d9}, {0x2282, 0x0008}, {0x2283, 0x0009},
  1155. + {0x22d7, 0x0008}, {0x22d8, 0x0009},
  1156. + /*For Mono ADC mixer*/
  1157. + {0x2261, 0x30df}, {0x2282, 0x000a}, {0x2283, 0x000b},
  1158. + {0x22d7, 0x000a}, {0x22d8, 0x000b},
  1159. +};
  1160. +
  1161. +static unsigned short rt5671_dsp_rate_par[] = {
  1162. + 0x226c, 0x226d, 0x226e, 0x22f2, 0x2301, 0x2306,
  1163. +};
  1164. +#define RT5671_DSP_RATE_NUM \
  1165. + (sizeof(rt5671_dsp_rate_par) / sizeof(rt5671_dsp_rate_par[0]))
  1166. +
  1167. +/* MCLK rate */
  1168. +static unsigned short rt5671_dsp_4096000[][2] = {
  1169. + {0x226c, 0x000c}, {0x226d, 0x000c}, {0x226e, 0x0022},
  1170. +};
  1171. +#define RT5671_DSP_4096000_NUM \
  1172. + (sizeof(rt5671_dsp_4096000) / sizeof(rt5671_dsp_4096000[0]))
  1173. +
  1174. +static unsigned short rt5671_dsp_12288000[][2] = {
  1175. + {0x226c, 0x000c}, {0x226d, 0x000c}, {0x226e, 0x0026},
  1176. +};
  1177. +#define RT5671_DSP_12288000_NUM \
  1178. + (sizeof(rt5671_dsp_12288000) / sizeof(rt5671_dsp_12288000[0]))
  1179. +
  1180. +static unsigned short rt5671_dsp_11289600[][2] = {
  1181. + {0x226c, 0x0031}, {0x226d, 0x0050}, {0x226e, 0x0009},
  1182. +};
  1183. +#define RT5671_DSP_11289600_NUM \
  1184. + (sizeof(rt5671_dsp_11289600) / sizeof(rt5671_dsp_11289600[0]))
  1185. +
  1186. +static unsigned short rt5671_dsp_24576000[][2] = {
  1187. + {0x226c, 0x000c}, {0x226d, 0x000c}, {0x226e, 0x002c},
  1188. +};
  1189. +#define RT5671_DSP_24576000_NUM \
  1190. + (sizeof(rt5671_dsp_24576000) / sizeof(rt5671_dsp_24576000[0]))
  1191. +
  1192. +/* sample rate */
  1193. +static unsigned short rt5671_dsp_48_441[][2] = {
  1194. + {0x22f2, 0x005c}, {0x2301, 0x0016}
  1195. +};
  1196. +#define RT5671_DSP_48_441_NUM \
  1197. + (sizeof(rt5671_dsp_48_441) / sizeof(rt5671_dsp_48_441[0]))
  1198. +
  1199. +static unsigned short rt5671_dsp_24[][2] = {
  1200. + {0x22f2, 0x005c}, {0x2301, 0x0004}
  1201. +};
  1202. +#define RT5671_DSP_24_NUM (sizeof(rt5671_dsp_24) / sizeof(rt5671_dsp_24[0]))
  1203. +
  1204. +static unsigned short rt5671_dsp_16[][2] = {
  1205. + {0x22f2, 0x0058}, {0x2301, 0x0002}
  1206. +};
  1207. +#define RT5671_DSP_16_NUM (sizeof(rt5671_dsp_16) / sizeof(rt5671_dsp_16[0]))
  1208. +
  1209. +static unsigned short rt5671_dsp_8[][2] = {
  1210. + {0x22f2, 0x004c}, {0x2301, 0x0000}
  1211. +};
  1212. +#define RT5671_DSP_8_NUM (sizeof(rt5671_dsp_8) / sizeof(rt5671_dsp_8[0]))
  1213. +
  1214. +/* DSP mode */
  1215. +static unsigned short rt5671_dsp_hs_aec[][2] = {
  1216. + /* AEC_WB_HP_VOIP */
  1217. + {0x22f8, 0x8005},
  1218. + {0x229d, 0x0000},
  1219. + {0x232f, 0x0010},
  1220. + {0x2355, 0x0800},
  1221. + {0x2356, 0x0800},
  1222. + {0x2357, 0x1000},
  1223. + {0x2358, 0x2000},
  1224. + {0x2359, 0x4000},
  1225. + {0x235a, 0x6000},
  1226. + {0x235b, 0x7fff},
  1227. + {0x235c, 0x7fff},
  1228. + {0x235d, 0x7fff},
  1229. + {0x235e, 0x7fff},
  1230. + {0x235f, 0x7fff},
  1231. + {0x2360, 0x7fff},
  1232. + {0x2361, 0x7fff},
  1233. + {0x2362, 0x1000},
  1234. + {0x2367, 0x0008},
  1235. + {0x2368, 0x2000},
  1236. + {0x2369, 0x0010},
  1237. + {0x236a, 0x0200},
  1238. + {0x236b, 0x0000},
  1239. + {0x236d, 0x0000},
  1240. + {0x236f, 0x0200},
  1241. + {0x2375, 0x7ff0},
  1242. + {0x2376, 0x7990},
  1243. + {0x2377, 0x7330},
  1244. + {0x238a, 0x0400},
  1245. + {0x238b, 0x1800},
  1246. + {0x238c, 0x1800},
  1247. + {0x23a3, 0x2000},
  1248. + {0x23ad, 0x2000},
  1249. + {0x23ae, 0x2000},
  1250. + {0x23af, 0x2000},
  1251. + {0x23b0, 0x2000},
  1252. + {0x23b1, 0x2000},
  1253. + {0x23b4, 0x0800},
  1254. + {0x23b5, 0x0800},
  1255. + {0x23b6, 0x0800},
  1256. + {0x23b7, 0x0800},
  1257. + {0x23b8, 0x0800},
  1258. + {0x23bb, 0x2000},
  1259. + {0x23e7, 0x0400},
  1260. + {0x23e8, 0x0c00},
  1261. + {0x23e9, 0x5000},
  1262. + {0x23ea, 0x7800},
  1263. + {0x23c4, 0x1000},
  1264. + {0x2304, 0x0332},
  1265. + {0x230c, 0x05a0},
  1266. + {0x230d, 0x0020},
  1267. + {0x2310, 0x0001},
  1268. +
  1269. + {0x22fb, 0x0000},
  1270. +};
  1271. +#define RT5671_DSP_HS_AEC_NUM \
  1272. + (sizeof(rt5671_dsp_hs_aec) / sizeof(rt5671_dsp_hs_aec[0]))
  1273. +
  1274. +static unsigned short rt5671_dsp_bt_ezaec[][2] = {
  1275. + /* ezAEC_WB_1mic_BT */
  1276. + {0x22f8, 0x8005},
  1277. + {0x229d, 0x0000},
  1278. + {0x232f, 0x0008},
  1279. + {0x2355, 0x0800},
  1280. + {0x2356, 0x0800},
  1281. + {0x2357, 0x0800},
  1282. + {0x2358, 0x0800},
  1283. + {0x2359, 0x0800},
  1284. + {0x235a, 0x0800},
  1285. + {0x235b, 0x1000},
  1286. + {0x235c, 0x2000},
  1287. + {0x235d, 0x2000},
  1288. + {0x235e, 0x2000},
  1289. + {0x235f, 0x2000},
  1290. + {0x2360, 0x7fff},
  1291. + {0x2361, 0x7fff},
  1292. + {0x2362, 0x0200},
  1293. + {0x2367, 0x000c},
  1294. + {0x2368, 0x0400},
  1295. + {0x2369, 0x0010},
  1296. + {0x2375, 0x7ff0},
  1297. + {0x2376, 0x7990},
  1298. + {0x2377, 0x7330},
  1299. + {0x238a, 0x0400},
  1300. + {0x238b, 0x2000},
  1301. + {0x238c, 0x2000},
  1302. + {0x23a3, 0x2000},
  1303. + {0x23ad, 0x1000},
  1304. + {0x23ae, 0x1000},
  1305. + {0x23af, 0x1000},
  1306. + {0x23b0, 0x1000},
  1307. + {0x23b1, 0x1000},
  1308. + {0x23b4, 0x0200},
  1309. + {0x23b5, 0x0200},
  1310. + {0x23b6, 0x0200},
  1311. + {0x23b7, 0x0200},
  1312. + {0x23b8, 0x0200},
  1313. + {0x23bb, 0x0800},
  1314. + {0x23c4, 0x2000},
  1315. + {0x23e7, 0x1000},
  1316. + {0x23e8, 0x1800},
  1317. + {0x23e9, 0x5000},
  1318. + {0x23ea, 0x7800},
  1319. + {0x230c, 0x0100},
  1320. + {0x230d, 0x0080},
  1321. + {0x2304, 0x0332},
  1322. + {0x2310, 0x0001},
  1323. +
  1324. + {0x22fb, 0x0000},
  1325. +};
  1326. +#define RT5671_DSP_BT_EZAEC_NUM \
  1327. + (sizeof(rt5671_dsp_bt_ezaec) / sizeof(rt5671_dsp_bt_ezaec[0]))
  1328. +
  1329. +static unsigned short rt5671_dsp_bt_aec[][2] = {
  1330. + /* (AEC mode)~[1mic][WB][for BT & headphone]*/
  1331. + {0x22f8, 0x8005},
  1332. + {0x229d, 0x0000},
  1333. + {0x232f, 0x0020},
  1334. + {0x2355, 0x0800},
  1335. + {0x2356, 0x0800},
  1336. + {0x2357, 0x0800},
  1337. + {0x2358, 0x1000},
  1338. + {0x2359, 0x1000},
  1339. + {0x235a, 0x1000},
  1340. + {0x235b, 0x1000},
  1341. + {0x235c, 0x2000},
  1342. + {0x235d, 0x2000},
  1343. + {0x235e, 0x4000},
  1344. + {0x235f, 0x4000},
  1345. + {0x2360, 0x7fff},
  1346. + {0x2361, 0x7fff},
  1347. + {0x2362, 0x0400},
  1348. + {0x2367, 0x0008},
  1349. + {0x2368, 0x1000},
  1350. + {0x2369, 0x0010},
  1351. + {0x2375, 0x7ff0},
  1352. + {0x2376, 0x7990},
  1353. + {0x2377, 0x7330},
  1354. + {0x238a, 0x0400},
  1355. + {0x238b, 0x1000},
  1356. + {0x238c, 0x1000},
  1357. + {0x23a3, 0x2000},
  1358. + {0x23ad, 0x2000},
  1359. + {0x23ae, 0x2000},
  1360. + {0x23af, 0x2000},
  1361. + {0x23b0, 0x2000},
  1362. + {0x23b1, 0x2000},
  1363. + {0x23b4, 0x0800},
  1364. + {0x23b5, 0x0800},
  1365. + {0x23b6, 0x0800},
  1366. + {0x23b7, 0x0800},
  1367. + {0x23b8, 0x0800},
  1368. + {0x23bb, 0x1000},
  1369. + {0x23c4, 0x1800},
  1370. + {0x23e7, 0x1000},
  1371. + {0x23e8, 0x1800},
  1372. + {0x23e9, 0x5000},
  1373. + {0x23ea, 0x7800},
  1374. + {0x230c, 0x0100},
  1375. + {0x230d, 0x0080},
  1376. + {0x2304, 0x0332},
  1377. + {0x2310, 0x0001},
  1378. +
  1379. + {0x22fb, 0x0000},
  1380. +};
  1381. +#define RT5671_DSP_BT_AEC_NUM \
  1382. + (sizeof(rt5671_dsp_bt_aec) / sizeof(rt5671_dsp_bt_aec[0]))
  1383. +
  1384. +static unsigned short rt5671_dsp_1mic_aec[][2] = {
  1385. + /* (AEC mode)~[1mic][WB][VOIP] */
  1386. + {0x22f8, 0x8005},
  1387. + {0x229d, 0x0000},
  1388. + {0x232b, 0x0006},
  1389. + {0x232f, 0x0180},
  1390. + {0x2355, 0x2666},
  1391. + {0x2356, 0x2666},
  1392. + {0x2357, 0x6666},
  1393. + {0x2358, 0x6666},
  1394. + {0x2359, 0x7fff},
  1395. + {0x235a, 0x7fff},
  1396. + {0x235b, 0x7fff},
  1397. + {0x235c, 0x7fff},
  1398. + {0x235d, 0x7fff},
  1399. + {0x235e, 0x7fff},
  1400. + {0x235f, 0x7fff},
  1401. + {0x2360, 0x7fff},
  1402. + {0x2361, 0x7fff},
  1403. + {0x2362, 0x4000},
  1404. + {0x2368, 0x6000},
  1405. + {0x2369, 0x0006},
  1406. + {0x236a, 0x2000},
  1407. + {0x236b, 0x000a},
  1408. + {0x236c, 0x0040},
  1409. + {0x236d, 0x0000},
  1410. + {0x236f, 0x2000},
  1411. + {0x2375, 0x7ff0},
  1412. + {0x2376, 0x7332},
  1413. + {0x2377, 0x6666},
  1414. + {0x237e, 0x0001},
  1415. + {0x2388, 0x4000},
  1416. + {0x238a, 0x2000},
  1417. + {0x238b, 0x1000},
  1418. + {0x238c, 0x1000},
  1419. + {0x23a3, 0x2000},
  1420. + {0x23ad, 0x2000},
  1421. + {0x23ae, 0x7000},
  1422. + {0x23af, 0x7000},
  1423. + {0x23b0, 0x7000},
  1424. + {0x23b1, 0x7fff},
  1425. + {0x23b4, 0x0800},
  1426. + {0x23b5, 0x1000},
  1427. + {0x23b6, 0x4000},
  1428. + {0x23b7, 0x4000},
  1429. + {0x23b8, 0x7fff},
  1430. + {0x23bb, 0x2000},
  1431. + {0x23c4, 0x2800},
  1432. + {0x23df, 0x4210},
  1433. + {0x23e0, 0x1374},
  1434. + {0x23e4, 0x5677},
  1435. + {0x2304, 0x0332},
  1436. + {0x230c, 0x05a0},
  1437. + {0x230d, 0x0200},
  1438. + {0x23e7, 0x0e00},
  1439. + {0x23e8, 0x1200},
  1440. + {0x23e9, 0x6000},
  1441. + {0x23ea, 0x7800},
  1442. + {0x2310, 0x0008},
  1443. +
  1444. + {0x22fb, 0x0000},
  1445. +};
  1446. +#define RT5671_DSP_1MIC_AEC_NUM \
  1447. + (sizeof(rt5671_dsp_1mic_aec) / sizeof(rt5671_dsp_1mic_aec[0]))
  1448. +
  1449. +static unsigned short rt5671_dsp_1mic_ezaec[][2] = {
  1450. + /* (AEC mode)~[1mic][WB][VOIP] with SW-AEC */
  1451. + {0x22f8, 0x8005},
  1452. + {0x229d, 0x0000},
  1453. + {0x232b, 0x0006},
  1454. + {0x232f, 0x0180},
  1455. + {0x2355, 0x2666},
  1456. + {0x2356, 0x2666},
  1457. + {0x2357, 0x6666},
  1458. + {0x2358, 0x6666},
  1459. + {0x2359, 0x7fff},
  1460. + {0x235a, 0x7fff},
  1461. + {0x235b, 0x7fff},
  1462. + {0x235c, 0x7fff},
  1463. + {0x235d, 0x7fff},
  1464. + {0x235e, 0x7fff},
  1465. + {0x235f, 0x7fff},
  1466. + {0x2360, 0x7fff},
  1467. + {0x2361, 0x7fff},
  1468. + {0x2362, 0x4000},
  1469. + {0x2368, 0x6000},
  1470. + {0x2369, 0x000c},
  1471. + {0x236a, 0x1000},
  1472. + {0x236b, 0x000a},
  1473. + {0x236c, 0x0040},
  1474. + {0x236d, 0x0000},
  1475. + {0x236f, 0x1000},
  1476. + {0x2375, 0x7ff0},
  1477. + {0x2376, 0x7332},
  1478. + {0x2377, 0x6666},
  1479. + {0x237e, 0x0001},
  1480. + {0x2388, 0x4000},
  1481. + {0x238a, 0x1000},
  1482. + {0x238b, 0x1000},
  1483. + {0x238c, 0x1000},
  1484. + {0x23a3, 0x2000},
  1485. + {0x23ad, 0x2000},
  1486. + {0x23ae, 0x2000},
  1487. + {0x23af, 0x4000},
  1488. + {0x23b0, 0x6000},
  1489. + {0x23b1, 0x7fff},
  1490. + {0x23b4, 0x0800},
  1491. + {0x23b5, 0x1000},
  1492. + {0x23b6, 0x2000},
  1493. + {0x23b7, 0x4000},
  1494. + {0x23b8, 0x6000},
  1495. + {0x23bb, 0x2000},
  1496. + {0x23c4, 0x2800},
  1497. + {0x23df, 0x4210},
  1498. + {0x23e0, 0x1374},
  1499. + {0x23e4, 0x5677},
  1500. + {0x2304, 0x0332},
  1501. + {0x230c, 0x05a0},
  1502. + {0x230d, 0x0200},
  1503. + {0x23e7, 0x0e00},
  1504. + {0x23e8, 0x1200},
  1505. + {0x23e9, 0x6000},
  1506. + {0x23ea, 0x7800},
  1507. + {0x2310, 0x0008},
  1508. +
  1509. + {0x22fb, 0x0000},
  1510. +
  1511. +
  1512. +};
  1513. +#define RT5671_DSP_1MIC_EZAEC_NUM \
  1514. + (sizeof(rt5671_dsp_1mic_ezaec) / sizeof(rt5671_dsp_1mic_ezaec[0]))
  1515. +
  1516. +static unsigned short rt5671_dsp_aec[][2] = {
  1517. + /* (AEC mode)~[2mic][WB][VT] for VOIP without SW-AEC */
  1518. + {0x22f8, 0x8003},
  1519. + {0x229d, 0x0000},
  1520. + {0x232b, 0x0006},
  1521. + {0x232f, 0x0180},
  1522. + {0x2355, 0x2666},
  1523. + {0x2356, 0x2666},
  1524. + {0x2357, 0x6666},
  1525. + {0x2358, 0x6666},
  1526. + {0x2359, 0x7fff},
  1527. + {0x235a, 0x7fff},
  1528. + {0x235b, 0x7fff},
  1529. + {0x235c, 0x7fff},
  1530. + {0x235d, 0x7fff},
  1531. + {0x235e, 0x7fff},
  1532. + {0x235f, 0x7fff},
  1533. + {0x2360, 0x7fff},
  1534. + {0x2361, 0x7fff},
  1535. + {0x2362, 0x4000},
  1536. + {0x2368, 0x6000},
  1537. + {0x2369, 0x0006},
  1538. + {0x236a, 0x2000},
  1539. + {0x236b, 0x000a},
  1540. + {0x236c, 0x0040},
  1541. + {0x236d, 0x0000},
  1542. + {0x236f, 0x2000},
  1543. + {0x2371, 0x0005},
  1544. + {0x2375, 0x7999},
  1545. + {0x2376, 0x6ccc},
  1546. + {0x2377, 0x5fff},
  1547. + {0x2379, 0x1800},
  1548. + {0x237a, 0x1800},
  1549. + {0x237e, 0x0001},
  1550. + {0x2388, 0x6800},
  1551. + {0x2389, 0x7000},
  1552. + {0x238a, 0x2000},
  1553. + {0x238b, 0x0800},
  1554. + {0x238c, 0x0800},
  1555. + {0x2393, 0x8222},
  1556. + {0x2394, 0x2104},
  1557. + {0x2395, 0x4444},
  1558. + {0x2396, 0x2222},
  1559. + {0x2397, 0x3344},
  1560. + {0x2398, 0x88aa},
  1561. + {0x23a1, 0x1000},
  1562. + {0x23a3, 0x1000},
  1563. + {0x23ad, 0x2000},
  1564. + {0x23ae, 0x7000},
  1565. + {0x23af, 0x7000},
  1566. + {0x23b0, 0x7000},
  1567. + {0x23b1, 0x7fff},
  1568. + {0x23b4, 0x0800},
  1569. + {0x23b5, 0x1000},
  1570. + {0x23b6, 0x4000},
  1571. + {0x23b7, 0x4000},
  1572. + {0x23b8, 0x7fff},
  1573. + {0x23bb, 0x2000},
  1574. + {0x23c4, 0x2800},
  1575. + {0x23df, 0x4210},
  1576. + {0x23e0, 0x1374},
  1577. + {0x23e4, 0x5677},
  1578. + {0x2304, 0x0332},
  1579. + {0x230c, 0x0600},
  1580. + {0x230d, 0x0200},
  1581. + {0x23e7, 0x0e00},
  1582. + {0x23e8, 0x1200},
  1583. + {0x23e9, 0x6000},
  1584. + {0x23ea, 0x7800},
  1585. + {0x2310, 0x0008},
  1586. +
  1587. + {0x22fb, 0x0000},
  1588. +};
  1589. +#define RT5671_DSP_AEC_NUM \
  1590. + (sizeof(rt5671_dsp_aec) / sizeof(rt5671_dsp_aec[0]))
  1591. +
  1592. +static unsigned short rt5671_dsp_ezaec[][2] = {
  1593. + /* (AEC mode)~[2mic][WB][VT] for VOIP with SW-AEC */
  1594. + {0x22f8, 0x8003},
  1595. + {0x229d, 0x0000},
  1596. + {0x232b, 0x0006},
  1597. + {0x232f, 0x0180},
  1598. + {0x2355, 0x2666},
  1599. + {0x2356, 0x2666},
  1600. + {0x2357, 0x6666},
  1601. + {0x2358, 0x6666},
  1602. + {0x2359, 0x7fff},
  1603. + {0x235a, 0x7fff},
  1604. + {0x235b, 0x7fff},
  1605. + {0x235c, 0x7fff},
  1606. + {0x235d, 0x7fff},
  1607. + {0x235e, 0x7fff},
  1608. + {0x235f, 0x7fff},
  1609. + {0x2360, 0x7fff},
  1610. + {0x2361, 0x7fff},
  1611. + {0x2362, 0x4000},
  1612. + {0x2368, 0x6000},
  1613. + {0x2369, 0x000c},
  1614. + {0x236a, 0x1000},
  1615. + {0x236b, 0x000a},
  1616. + {0x236c, 0x0040},
  1617. + {0x236d, 0x0000},
  1618. + {0x236f, 0x1000},
  1619. + {0x2371, 0x0005},
  1620. + {0x2375, 0x7999},
  1621. + {0x2376, 0x6ccc},
  1622. + {0x2377, 0x5fff},
  1623. + {0x2379, 0x1800},
  1624. + {0x237a, 0x1800},
  1625. + {0x237e, 0x0001},
  1626. + {0x2388, 0x6800},
  1627. + {0x2389, 0x7000},
  1628. + {0x238a, 0x1000},
  1629. + {0x238b, 0x0800},
  1630. + {0x238c, 0x0800},
  1631. + {0x2393, 0x8222},
  1632. + {0x2394, 0x2104},
  1633. + {0x2395, 0x4444},
  1634. + {0x2396, 0x2222},
  1635. + {0x2397, 0x3344},
  1636. + {0x2398, 0x88aa},
  1637. + {0x23a1, 0x1000},
  1638. + {0x23a3, 0x1000},
  1639. + {0x23ad, 0x2000},
  1640. + {0x23ae, 0x2000},
  1641. + {0x23af, 0x4000},
  1642. + {0x23b0, 0x6000},
  1643. + {0x23b1, 0x7fff},
  1644. + {0x23b4, 0x0800},
  1645. + {0x23b5, 0x1000},
  1646. + {0x23b6, 0x2000},
  1647. + {0x23b7, 0x4000},
  1648. + {0x23b8, 0x6000},
  1649. + {0x23bb, 0x2000},
  1650. + {0x23c4, 0x2800},
  1651. + {0x23df, 0x4210},
  1652. + {0x23e0, 0x1374},
  1653. + {0x23e4, 0x5677},
  1654. + {0x2304, 0x0332},
  1655. + {0x230c, 0x0680},
  1656. + {0x230d, 0x0200},
  1657. + {0x23e7, 0x0e00},
  1658. + {0x23e8, 0x1200},
  1659. + {0x23e9, 0x6000},
  1660. + {0x23ea, 0x7800},
  1661. + {0x2310, 0x0008},
  1662. +
  1663. + {0x22fb, 0x0000},
  1664. +};
  1665. +#define RT5671_DSP_EZAEC_NUM \
  1666. + (sizeof(rt5671_dsp_ezaec) / sizeof(rt5671_dsp_ezaec[0]))
  1667. +
  1668. +static unsigned short rt5671_dsp_48k_sto[][2] = {
  1669. + /* (48Khz-stereo-recording) [with NS] */
  1670. + {0x22c1, 0x1025},
  1671. + {0x22c2, 0x1026},
  1672. + {0x2278, 0xe4e4},
  1673. + {0x22f8, 0x8004},
  1674. + {0x22ea, 0x0001},
  1675. + {0x230c, 0x0100},
  1676. + {0x230d, 0x0100},
  1677. + {0x2301, 0x0010},
  1678. + {0x2303, 0x0200},
  1679. + {0x2304, 0x0000},
  1680. + {0x2305, 0x0000},
  1681. + {0x2388, 0x6800},
  1682. + {0x238b, 0x3000},
  1683. + {0x238c, 0x3000},
  1684. + {0x23c4, 0x3000},
  1685. +
  1686. + {0x22fb, 0x0000},
  1687. +};
  1688. +#define RT5671_DSP_48K_STO_REC_NUM \
  1689. + (sizeof(rt5671_dsp_48k_sto) / sizeof(rt5671_dsp_48k_sto[0]))
  1690. +
  1691. +/**
  1692. + * rt5671_dsp_done - Wait until DSP is ready.
  1693. + * @codec: SoC Audio Codec device.
  1694. + *
  1695. + * To check voice DSP status and confirm it's ready for next work.
  1696. + *
  1697. + * Returns 0 for success or negative error code.
  1698. + */
  1699. +static int rt5671_dsp_done(struct snd_soc_codec *codec)
  1700. +{
  1701. + unsigned int count = 0, dsp_val;
  1702. +
  1703. + dsp_val = snd_soc_read(codec, RT5671_DSP_CTRL1);
  1704. + while (dsp_val & RT5671_DSP_BUSY_MASK) {
  1705. + if (count > 10)
  1706. + return -EBUSY;
  1707. + dsp_val = snd_soc_read(codec, RT5671_DSP_CTRL1);
  1708. + count++;
  1709. + }
  1710. +
  1711. + return 0;
  1712. +}
  1713. +
  1714. +/**
  1715. + * rt5671_dsp_write - Write DSP register.
  1716. + * @codec: SoC audio codec device.
  1717. + * @param: DSP parameters.
  1718. + *
  1719. + * Modify voice DSP register for sound effect. The DSP can be controlled
  1720. + * through DSP command format (0xfc), addr (0xc4), data (0xc5) and cmd (0xc6)
  1721. + * register. It has to wait until the DSP is ready.
  1722. + *
  1723. + * Returns 0 for success or negative error code.
  1724. + */
  1725. +int rt5671_dsp_write(struct snd_soc_codec *codec,
  1726. + unsigned int addr, unsigned int data)
  1727. +{
  1728. + unsigned int dsp_val;
  1729. + int ret;
  1730. +
  1731. + ret = snd_soc_write(codec, RT5671_DSP_CTRL2, addr);
  1732. + if (ret < 0) {
  1733. + dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
  1734. + goto err;
  1735. + }
  1736. + ret = snd_soc_write(codec, RT5671_DSP_CTRL3, data);
  1737. + if (ret < 0) {
  1738. + dev_err(codec->dev, "Failed to write DSP data reg: %d\n", ret);
  1739. + goto err;
  1740. + }
  1741. + dsp_val = RT5671_DSP_I2C_AL_16 | RT5671_DSP_DL_2 |
  1742. + RT5671_DSP_CMD_MW | DSP_CLK_RATE | RT5671_DSP_CMD_EN;
  1743. +
  1744. + ret = snd_soc_write(codec, RT5671_DSP_CTRL1, dsp_val);
  1745. + if (ret < 0) {
  1746. + dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
  1747. + goto err;
  1748. + }
  1749. + ret = rt5671_dsp_done(codec);
  1750. + if (ret < 0) {
  1751. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  1752. + goto err;
  1753. + }
  1754. +
  1755. + return 0;
  1756. +
  1757. +err:
  1758. + return ret;
  1759. +}
  1760. +
  1761. +/**
  1762. + * rt5671_dsp_read - Read DSP register.
  1763. + * @codec: SoC audio codec device.
  1764. + * @reg: DSP register index.
  1765. + *
  1766. + * Read DSP setting value from voice DSP. The DSP can be controlled
  1767. + * through DSP addr (0xc4), data (0xc5) and cmd (0xc6) register. Each
  1768. + * command has to wait until the DSP is ready.
  1769. + *
  1770. + * Returns DSP register value or negative error code.
  1771. + */
  1772. +unsigned int rt5671_dsp_read(
  1773. + struct snd_soc_codec *codec, unsigned int reg)
  1774. +{
  1775. + unsigned int value;
  1776. + unsigned int dsp_val;
  1777. + int ret = 0;
  1778. +
  1779. + ret = rt5671_dsp_done(codec);
  1780. + if (ret < 0) {
  1781. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  1782. + goto err;
  1783. + }
  1784. +
  1785. + ret = snd_soc_write(codec, RT5671_DSP_CTRL2, reg);
  1786. + if (ret < 0) {
  1787. + dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
  1788. + goto err;
  1789. + }
  1790. + dsp_val = RT5671_DSP_I2C_AL_16 | RT5671_DSP_DL_0 | RT5671_DSP_RW_MASK |
  1791. + RT5671_DSP_CMD_MR | DSP_CLK_RATE | RT5671_DSP_CMD_EN;
  1792. +
  1793. + ret = snd_soc_write(codec, RT5671_DSP_CTRL1, dsp_val);
  1794. + if (ret < 0) {
  1795. + dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
  1796. + goto err;
  1797. + }
  1798. +
  1799. + ret = rt5671_dsp_done(codec);
  1800. + if (ret < 0) {
  1801. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  1802. + goto err;
  1803. + }
  1804. +
  1805. + ret = snd_soc_write(codec, RT5671_DSP_CTRL2, 0x26);
  1806. + if (ret < 0) {
  1807. + dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
  1808. + goto err;
  1809. + }
  1810. + dsp_val = RT5671_DSP_DL_1 | RT5671_DSP_CMD_RR | RT5671_DSP_RW_MASK |
  1811. + DSP_CLK_RATE | RT5671_DSP_CMD_EN;
  1812. +
  1813. + ret = snd_soc_write(codec, RT5671_DSP_CTRL1, dsp_val);
  1814. + if (ret < 0) {
  1815. + dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
  1816. + goto err;
  1817. + }
  1818. +
  1819. + ret = rt5671_dsp_done(codec);
  1820. + if (ret < 0) {
  1821. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  1822. + goto err;
  1823. + }
  1824. +
  1825. + ret = snd_soc_write(codec, RT5671_DSP_CTRL2, 0x25);
  1826. + if (ret < 0) {
  1827. + dev_err(codec->dev, "Failed to write DSP addr reg: %d\n", ret);
  1828. + goto err;
  1829. + }
  1830. +
  1831. + dsp_val = RT5671_DSP_DL_1 | RT5671_DSP_CMD_RR | RT5671_DSP_RW_MASK |
  1832. + DSP_CLK_RATE | RT5671_DSP_CMD_EN;
  1833. +
  1834. + ret = snd_soc_write(codec, RT5671_DSP_CTRL1, dsp_val);
  1835. + if (ret < 0) {
  1836. + dev_err(codec->dev, "Failed to write DSP cmd reg: %d\n", ret);
  1837. + goto err;
  1838. + }
  1839. +
  1840. + ret = rt5671_dsp_done(codec);
  1841. + if (ret < 0) {
  1842. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  1843. + goto err;
  1844. + }
  1845. +
  1846. + ret = snd_soc_read(codec, RT5671_DSP_CTRL5);
  1847. + if (ret < 0) {
  1848. + dev_err(codec->dev, "Failed to read DSP data reg: %d\n", ret);
  1849. + goto err;
  1850. + }
  1851. +
  1852. + value = ret;
  1853. + return value;
  1854. +
  1855. +err:
  1856. + return ret;
  1857. +}
  1858. +
  1859. +static int rt5671_dsp_get(struct snd_kcontrol *kcontrol,
  1860. + struct snd_ctl_elem_value *ucontrol)
  1861. +{
  1862. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1863. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  1864. +
  1865. + ucontrol->value.integer.value[0] = rt5671->dsp_sw;
  1866. +
  1867. + return 0;
  1868. +}
  1869. +
  1870. +static int rt5671_dsp_snd_effect(struct snd_soc_codec *codec);
  1871. +
  1872. +static int rt5671_dsp_put(struct snd_kcontrol *kcontrol,
  1873. + struct snd_ctl_elem_value *ucontrol)
  1874. +{
  1875. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  1876. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  1877. +
  1878. + if (rt5671->dsp_sw != ucontrol->value.integer.value[0]) {
  1879. + rt5671->dsp_sw = ucontrol->value.integer.value[0];
  1880. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_I2S_DSP)
  1881. + rt5671_dsp_snd_effect(codec);
  1882. + }
  1883. +
  1884. + return 0;
  1885. +}
  1886. +
  1887. +/* DSP Path Control 1 */
  1888. +static const char * const rt5671_src_rxdp_mode[] = {
  1889. + "Normal", "Divided by 2", "Divided by 3"
  1890. +};
  1891. +
  1892. +static const SOC_ENUM_SINGLE_DECL(
  1893. + rt5671_src_rxdp_enum, RT5671_DSP_PATH1,
  1894. + RT5671_RXDP_SRC_SFT, rt5671_src_rxdp_mode);
  1895. +
  1896. +static const char * const rt5671_src_txdp_mode[] = {
  1897. + "Normal", "Multiplied by 2", "Multiplied by 3"
  1898. +};
  1899. +
  1900. +static const SOC_ENUM_SINGLE_DECL(
  1901. + rt5671_src_txdp_enum, RT5671_DSP_PATH1,
  1902. + RT5671_TXDP_SRC_SFT, rt5671_src_txdp_mode);
  1903. +
  1904. +/* Sound Effect */
  1905. +static const char *rt5671_dsp_mode[] = {
  1906. + "Disable",
  1907. + "BuiltinMic AEC-2mic",
  1908. + "BuiltinMic ezAEC-2mic",
  1909. + "BuiltinMic AEC-1mic",
  1910. + "BuiltinMic ezAEC-1mic",
  1911. + "BuiltinMic 48K-stereo+FFP+NS",
  1912. + "HeadsetMic AEC",
  1913. + "HeadsetMic 48K-stereo+FFP+NS",
  1914. + "BtMic AEC",
  1915. + "BtMic ezAEC",
  1916. +};
  1917. +
  1918. +static const SOC_ENUM_SINGLE_DECL(rt5671_dsp_enum, 0, 0,
  1919. + rt5671_dsp_mode);
  1920. +
  1921. +static const struct snd_kcontrol_new rt5671_dsp_snd_controls[] = {
  1922. + SOC_ENUM("RxDP SRC Switch", rt5671_src_rxdp_enum),
  1923. + SOC_ENUM("TxDP SRC Switch", rt5671_src_txdp_enum),
  1924. + /* AEC */
  1925. + SOC_ENUM_EXT("DSP Function Switch", rt5671_dsp_enum,
  1926. + rt5671_dsp_get, rt5671_dsp_put),
  1927. +};
  1928. +
  1929. +/**
  1930. + * rt5671_dsp_conf - Set DSP basic setting.
  1931. + *
  1932. + * @codec: SoC audio codec device.
  1933. + *
  1934. + * Set parameters of basic setting to DSP.
  1935. + *
  1936. + * Returns 0 for success or negative error code.
  1937. + */
  1938. +static int rt5671_dsp_conf(struct snd_soc_codec *codec)
  1939. +{
  1940. + int ret, i;
  1941. +
  1942. + for (i = 0; i < RT5671_DSP_INIT_NUM; i++) {
  1943. + ret = rt5671_dsp_write(codec, rt5671_dsp_init[i][0],
  1944. + rt5671_dsp_init[i][1]);
  1945. + if (ret < 0) {
  1946. + dev_err(codec->dev, "Fail to config Dsp: %d\n", ret);
  1947. + goto conf_err;
  1948. + }
  1949. + }
  1950. +
  1951. + return 0;
  1952. +
  1953. +conf_err:
  1954. +
  1955. + return ret;
  1956. +}
  1957. +
  1958. +/**
  1959. + * rt5671_dsp_rate - Set DSP rate setting.
  1960. + *
  1961. + * @codec: SoC audio codec device.
  1962. + * @sys_clk: System clock.
  1963. + * @srate: Sampling rate.
  1964. + *
  1965. + * Set parameters of system clock and sampling rate to DSP.
  1966. + *
  1967. + * Returns 0 for success or negative error code.
  1968. + */
  1969. +static int rt5671_dsp_rate(struct snd_soc_codec *codec, int sys_clk,
  1970. + int srate)
  1971. +{
  1972. + int ret, i, tab_num;
  1973. + unsigned short (*rate_tab)[2];
  1974. +
  1975. + dev_dbg(codec->dev, "rt5671_dsp_rate sys:%d srate:%d\n", sys_clk, srate);
  1976. +
  1977. + switch (sys_clk) {
  1978. + case 4096000:
  1979. + rate_tab = rt5671_dsp_4096000;
  1980. + tab_num = RT5671_DSP_4096000_NUM;
  1981. + break;
  1982. + case 11289600:
  1983. + rate_tab = rt5671_dsp_11289600;
  1984. + tab_num = RT5671_DSP_11289600_NUM;
  1985. + break;
  1986. + case 12288000:
  1987. + rate_tab = rt5671_dsp_12288000;
  1988. + tab_num = RT5671_DSP_12288000_NUM;
  1989. + break;
  1990. + case 24576000:
  1991. + rate_tab = rt5671_dsp_24576000;
  1992. + tab_num = RT5671_DSP_24576000_NUM;
  1993. + break;
  1994. + default:
  1995. + return -EINVAL;
  1996. + break;
  1997. + }
  1998. +
  1999. + for (i = 0; i < tab_num; i++) {
  2000. + ret = rt5671_dsp_write(codec, rate_tab[i][0], rate_tab[i][1]);
  2001. + if (ret < 0)
  2002. + goto rate_err;
  2003. + }
  2004. +
  2005. + switch (srate) {
  2006. + case 8000:
  2007. + rate_tab = rt5671_dsp_8;
  2008. + tab_num = RT5671_DSP_8_NUM;
  2009. + break;
  2010. + case 16000:
  2011. + rate_tab = rt5671_dsp_16;
  2012. + tab_num = RT5671_DSP_16_NUM;
  2013. + break;
  2014. + case 24000:
  2015. + rate_tab = rt5671_dsp_24;
  2016. + tab_num = RT5671_DSP_24_NUM;
  2017. + break;
  2018. + case 44100:
  2019. + case 48000:
  2020. + rate_tab = rt5671_dsp_48_441;
  2021. + tab_num = RT5671_DSP_48_441_NUM;
  2022. + break;
  2023. + default:
  2024. + return -EINVAL;
  2025. + break;
  2026. + }
  2027. +
  2028. + for (i = 0; i < tab_num; i++) {
  2029. + ret = rt5671_dsp_write(codec, rate_tab[i][0], rate_tab[i][1]);
  2030. + if (ret < 0)
  2031. + goto rate_err;
  2032. + }
  2033. +
  2034. + return 0;
  2035. +
  2036. +rate_err:
  2037. +
  2038. + dev_err(codec->dev, "Fail to set rate parameters: %d\n", ret);
  2039. + return ret;
  2040. +}
  2041. +
  2042. +/**
  2043. + * rt5671_dsp_do_patch - Write DSP patch code.
  2044. + *
  2045. + * @codec: SoC audio codec device.
  2046. + *
  2047. + * Write patch codes to DSP.
  2048. + *
  2049. + * mode:
  2050. + * 0: Init
  2051. + * 1: Reaset
  2052. + *
  2053. + * Returns 0 for success or negative error code.
  2054. + */
  2055. +static int rt5671_dsp_do_patch(struct snd_soc_codec *codec, int mode)
  2056. +{
  2057. + int ret, i;
  2058. +
  2059. + switch (mode) {
  2060. + case 0: /*Init*/
  2061. + for (i = 0; i < RT5671_DSP_INIT_PATCH_NUM; i++) {
  2062. + ret = snd_soc_write(codec, rt5671_dsp_init_patch_code[i][0],
  2063. + rt5671_dsp_init_patch_code[i][1]);
  2064. + if (ret < 0)
  2065. + goto patch_err;
  2066. +
  2067. +
  2068. + if (rt5671_dsp_init_patch_code[i][0] == 0xe0) {
  2069. + ret = rt5671_dsp_done(codec);
  2070. + if (ret < 0) {
  2071. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  2072. + goto patch_err;
  2073. + }
  2074. + }
  2075. + }
  2076. + break;
  2077. + case 1: /*Reset*/
  2078. + for (i = 0; i < RT5671_DSP_RESET_PATCH_NUM; i++) {
  2079. + ret = snd_soc_write(codec, rt5671_dsp_reset_patch_code[i][0],
  2080. + rt5671_dsp_reset_patch_code[i][1]);
  2081. + if (ret < 0)
  2082. + goto patch_err;
  2083. +
  2084. +
  2085. + if (rt5671_dsp_reset_patch_code[i][0] == 0xe0) {
  2086. + ret = rt5671_dsp_done(codec);
  2087. + if (ret < 0) {
  2088. + dev_err(codec->dev, "DSP is busy: %d\n", ret);
  2089. + goto patch_err;
  2090. + }
  2091. + }
  2092. + }
  2093. + break;
  2094. + default:
  2095. + pr_err("Invalid patch mode %d\n", mode);
  2096. + ret = -EINVAL;
  2097. + break;
  2098. + }
  2099. +
  2100. + return 0;
  2101. +
  2102. +patch_err:
  2103. + dev_err(codec->dev, "DSP patch error: %d\n", ret);
  2104. + return ret;
  2105. +}
  2106. +
  2107. +static int rt5671_dsp_set_data_source(struct snd_soc_codec *codec, int src)
  2108. +{
  2109. + int ret, i;
  2110. +
  2111. + pr_debug("%s: src=%d\n", __func__, src);
  2112. + for (i = src * RT5671_DSP_TDM_SRC_PAR_NUM;
  2113. + i < (src + 1) * RT5671_DSP_TDM_SRC_PAR_NUM; i++) {
  2114. + ret = rt5671_dsp_write(codec,
  2115. + rt5671_dsp_data_src[i][0], rt5671_dsp_data_src[i][1]);
  2116. + if (ret < 0)
  2117. + goto src_err;
  2118. + }
  2119. +
  2120. + return 0;
  2121. +
  2122. +src_err:
  2123. +
  2124. + dev_err(codec->dev, "Fail to set tdm source %d parameters: %d\n",
  2125. + src, ret);
  2126. + return ret;
  2127. +}
  2128. +
  2129. +/**
  2130. + * rt5671_dsp_set_mode - Set DSP mode parameters.
  2131. + *
  2132. + * @codec: SoC audio codec device.
  2133. + * @mode: DSP mode.
  2134. + *
  2135. + * Set parameters of mode to DSP.
  2136. + * There are three modes which includes " mic AEC + NS + FENS",
  2137. + * "HFBF" and "Far-field pickup".
  2138. + *
  2139. + * Returns 0 for success or negative error code.
  2140. + */
  2141. +static int rt5671_dsp_set_mode(struct snd_soc_codec *codec, int mode)
  2142. +{
  2143. + int ret, i, tab_num;
  2144. + unsigned short (*mode_tab)[2];
  2145. +
  2146. + switch (mode) {
  2147. + case RT5671_DSP_ONE_MIC_AEC:
  2148. + dev_info(codec->dev, "One Mic AEC\n");
  2149. + mode_tab = rt5671_dsp_1mic_aec;
  2150. + tab_num = RT5671_DSP_1MIC_AEC_NUM;
  2151. + break;
  2152. + case RT5671_DSP_ONE_MIC_EZAEC:
  2153. + dev_info(codec->dev, "One Mic ezAEC\n");
  2154. + mode_tab = rt5671_dsp_1mic_ezaec;
  2155. + tab_num = RT5671_DSP_1MIC_EZAEC_NUM;
  2156. + break;
  2157. + case RT5671_DSP_TWO_MIC_AEC:
  2158. + dev_info(codec->dev, "Two Mic AEC\n");
  2159. + mode_tab = rt5671_dsp_aec;
  2160. + tab_num = RT5671_DSP_AEC_NUM;
  2161. + break;
  2162. + case RT5671_DSP_TWO_MIC_EZAEC:
  2163. + dev_info(codec->dev, "Two Mic ezAEC\n");
  2164. + mode_tab = rt5671_dsp_ezaec;
  2165. + tab_num = RT5671_DSP_EZAEC_NUM;
  2166. + break;
  2167. + case RT5671_DSP_BT_AEC:
  2168. + dev_info(codec->dev, "BT AEC\n");
  2169. + mode_tab = rt5671_dsp_bt_aec;
  2170. + tab_num = RT5671_DSP_BT_AEC_NUM;
  2171. + break;
  2172. + case RT5671_DSP_BT_EZAEC:
  2173. + dev_info(codec->dev, "BT ezAEC\n");
  2174. + mode_tab = rt5671_dsp_bt_ezaec;
  2175. + tab_num = RT5671_DSP_BT_EZAEC_NUM;
  2176. + break;
  2177. + case RT5671_DSP_HS_AEC:
  2178. + dev_info(codec->dev, "HS AEC\n");
  2179. + mode_tab = rt5671_dsp_hs_aec;
  2180. + tab_num = RT5671_DSP_HS_AEC_NUM;
  2181. + break;
  2182. +
  2183. + case RT5671_DSP_BM_48K_STO_FFP_NS:
  2184. + case RT5671_DSP_HS_48K_STO_FFP_NS:
  2185. + dev_info(codec->dev, "48K_STO_REC\n");
  2186. + mode_tab = rt5671_dsp_48k_sto;
  2187. + tab_num = RT5671_DSP_48K_STO_REC_NUM;
  2188. + break;
  2189. +
  2190. + case RT5671_DSP_DIS:
  2191. + default:
  2192. + dev_info(codec->dev, "Disable\n");
  2193. + return 0;
  2194. + }
  2195. +
  2196. + for (i = 0; i < tab_num; i++) {
  2197. + ret = rt5671_dsp_write(codec, mode_tab[i][0], mode_tab[i][1]);
  2198. + if (ret < 0)
  2199. + goto mode_err;
  2200. + }
  2201. +
  2202. + return 0;
  2203. +
  2204. +mode_err:
  2205. +
  2206. + dev_err(codec->dev, "Fail to set mode %d parameters: %d\n", mode, ret);
  2207. + return ret;
  2208. +}
  2209. +
  2210. +/**
  2211. + * rt5671_dsp_snd_effect - Set DSP sound effect.
  2212. + *
  2213. + * Set parameters of sound effect to DSP.
  2214. + *
  2215. + * Returns 0 for success or negative error code.
  2216. + */
  2217. +static int rt5671_dsp_snd_effect(struct snd_soc_codec *codec)
  2218. +{
  2219. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  2220. + int ret, val, rate, src = 0;
  2221. +
  2222. + snd_soc_update_bits(codec, RT5671_GEN_CTRL1, RT5671_RST_DSP,
  2223. + RT5671_RST_DSP);
  2224. + mdelay(5);
  2225. + snd_soc_update_bits(codec, RT5671_GEN_CTRL1, RT5671_RST_DSP, 0);
  2226. +
  2227. + mdelay(10);
  2228. +
  2229. + if (!rt5671->dsp_inited) {
  2230. + ret = rt5671_dsp_do_patch(codec, 0);
  2231. + if (ret < 0)
  2232. + goto effect_err;
  2233. + rt5671->dsp_inited = true;
  2234. + }
  2235. +
  2236. + ret = rt5671_dsp_do_patch(codec, 1);
  2237. + if (ret < 0)
  2238. + goto effect_err;
  2239. +
  2240. + switch (rt5671->dsp_sw) {
  2241. + case RT5671_DSP_BM_48K_STO_FFP_NS:
  2242. + case RT5671_DSP_HS_48K_STO_FFP_NS:
  2243. + rate = 48000;
  2244. + break;
  2245. + default:
  2246. + rate = 16000;
  2247. + break;
  2248. + }
  2249. +
  2250. + ret = rt5671_dsp_rate(codec, 12288000, rate);
  2251. + if (ret < 0)
  2252. + goto effect_err;
  2253. +
  2254. + /*read MX-2d [3:2] to decide TDM source*/
  2255. + /*currently, support slot 0/1 and 2/3 only*/
  2256. + val = snd_soc_read(codec, RT5671_DSP_PATH1) & 0xc;
  2257. + if (val == 0x4) /*slot 2/3*/
  2258. + src = 1;
  2259. +
  2260. + ret = rt5671_dsp_set_data_source(codec, src);
  2261. + if (ret < 0)
  2262. + goto effect_err;
  2263. +
  2264. + ret = rt5671_dsp_conf(codec);
  2265. + if (ret < 0)
  2266. + goto effect_err;
  2267. +
  2268. + ret = rt5671_dsp_set_mode(codec, rt5671->dsp_sw);
  2269. + if (ret < 0)
  2270. + goto effect_err;
  2271. +
  2272. + return 0;
  2273. +
  2274. +effect_err:
  2275. +
  2276. + return ret;
  2277. +}
  2278. +
  2279. +static int rt5671_dsp_event(struct snd_soc_dapm_widget *w,
  2280. + struct snd_kcontrol *k, int event)
  2281. +{
  2282. + struct snd_soc_codec *codec = w->codec;
  2283. +
  2284. + switch (event) {
  2285. + case SND_SOC_DAPM_POST_PMD:
  2286. + dev_dbg(codec->dev, "%s(): PMD\n", __func__);
  2287. + rt5671_dsp_write(codec, 0x22f9, 1);
  2288. + break;
  2289. +
  2290. + case SND_SOC_DAPM_POST_PMU:
  2291. + dev_dbg(codec->dev, "%s(): PMU\n", __func__);
  2292. + rt5671_dsp_snd_effect(codec);
  2293. + break;
  2294. +
  2295. + default:
  2296. + return 0;
  2297. + }
  2298. +
  2299. + return 0;
  2300. +}
  2301. +
  2302. +static const struct snd_soc_dapm_widget rt5671_dsp_dapm_widgets[] = {
  2303. + SND_SOC_DAPM_SUPPLY_S("Voice DSP", 1, SND_SOC_NOPM,
  2304. + 0, 0, rt5671_dsp_event,
  2305. + SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
  2306. + SND_SOC_DAPM_PGA("DSP Downstream", SND_SOC_NOPM,
  2307. + 0, 0, NULL, 0),
  2308. + SND_SOC_DAPM_PGA("DSP Upstream", SND_SOC_NOPM,
  2309. + 0, 0, NULL, 0),
  2310. +};
  2311. +
  2312. +static const struct snd_soc_dapm_route rt5671_dsp_dapm_routes[] = {
  2313. + {"DSP Downstream", NULL, "Voice DSP"},
  2314. + {"DSP Downstream", NULL, "RxDP Mux"},
  2315. + {"DSP Upstream", NULL, "Voice DSP"},
  2316. + {"DSP Upstream", NULL, "TDM Data Mux"},
  2317. + {"DSP DL Mux", "DSP", "DSP Downstream"},
  2318. + {"DSP UL Mux", "DSP", "DSP Upstream"},
  2319. +};
  2320. +
  2321. +/**
  2322. + * rt5671_dsp_show - Dump DSP registers.
  2323. + * @dev: codec device.
  2324. + * @attr: device attribute.
  2325. + * @buf: buffer for display.
  2326. + *
  2327. + * To show non-zero values of all DSP registers.
  2328. + *
  2329. + * Returns buffer length.
  2330. + */
  2331. +static ssize_t rt5671_dsp_show(struct device *dev,
  2332. + struct device_attribute *attr, char *buf)
  2333. +{
  2334. + struct i2c_client *client = to_i2c_client(dev);
  2335. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  2336. + struct snd_soc_codec *codec = rt5671->codec;
  2337. + unsigned short (*rt5671_dsp_tab)[2];
  2338. + unsigned int val;
  2339. + int cnt = 0, i, tab_num;
  2340. +
  2341. + /*Check if DSP bypass*/
  2342. + if (!(snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_I2S_DSP) ||
  2343. + snd_soc_read(codec, RT5671_DSP_PATH1) & RT5671_DSP_UL_SEL) {
  2344. + cnt += sprintf(buf, "[ DSP Bypass ]\n");
  2345. + goto dsp_done;
  2346. + }
  2347. +
  2348. + switch (rt5671->dsp_sw) {
  2349. + case RT5671_DSP_ONE_MIC_AEC:
  2350. + cnt += sprintf(buf, "[ DSP 'One Mic AEC' ]\n");
  2351. + rt5671_dsp_tab = rt5671_dsp_1mic_aec;
  2352. + tab_num = RT5671_DSP_1MIC_AEC_NUM;
  2353. + break;
  2354. + case RT5671_DSP_ONE_MIC_EZAEC:
  2355. + cnt += sprintf(buf, "[ DSP 'One Mic ezAEC' ]\n");
  2356. + rt5671_dsp_tab = rt5671_dsp_1mic_ezaec;
  2357. + tab_num = RT5671_DSP_1MIC_EZAEC_NUM;
  2358. + break;
  2359. + case RT5671_DSP_TWO_MIC_AEC:
  2360. + cnt += sprintf(buf, "[ DSP 'Two Mic AEC' ]\n");
  2361. + rt5671_dsp_tab = rt5671_dsp_aec;
  2362. + tab_num = RT5671_DSP_AEC_NUM;
  2363. + break;
  2364. + case RT5671_DSP_TWO_MIC_EZAEC:
  2365. + cnt += sprintf(buf, "[ DSP 'Two Mic ezAEC' ]\n");
  2366. + rt5671_dsp_tab = rt5671_dsp_ezaec;
  2367. + tab_num = RT5671_DSP_EZAEC_NUM;
  2368. + break;
  2369. + case RT5671_DSP_BT_EZAEC:
  2370. + cnt += sprintf(buf, "[ DSP 'BT ezAEC' ]\n");
  2371. + rt5671_dsp_tab = rt5671_dsp_bt_ezaec;
  2372. + tab_num = RT5671_DSP_BT_EZAEC_NUM;
  2373. + break;
  2374. + case RT5671_DSP_BT_AEC:
  2375. + cnt += sprintf(buf, "[ DSP 'BT AEC' ]\n");
  2376. + rt5671_dsp_tab = rt5671_dsp_bt_aec;
  2377. + tab_num = RT5671_DSP_BT_AEC_NUM;
  2378. + break;
  2379. + case RT5671_DSP_HS_AEC:
  2380. + cnt += sprintf(buf, "[ DSP 'HS AEC' ]\n");
  2381. + rt5671_dsp_tab = rt5671_dsp_hs_aec;
  2382. + tab_num = RT5671_DSP_HS_AEC_NUM;
  2383. + break;
  2384. +
  2385. + case RT5671_DSP_BM_48K_STO_FFP_NS:
  2386. + case RT5671_DSP_HS_48K_STO_FFP_NS:
  2387. + cnt += sprintf(buf, "[ DSP '48K_STO_REC' ]\n");
  2388. + rt5671_dsp_tab = rt5671_dsp_48k_sto;
  2389. + tab_num = RT5671_DSP_48K_STO_REC_NUM;
  2390. + break;
  2391. +
  2392. + case RT5671_DSP_DIS:
  2393. + default:
  2394. + cnt += sprintf(buf, " DSP Disabled\n");
  2395. + goto dsp_done;
  2396. + }
  2397. +
  2398. + for (i = 0; i < tab_num; i++) {
  2399. + if (cnt + RT5671_DSP_REG_DISP_LEN >= PAGE_SIZE)
  2400. + break;
  2401. + val = rt5671_dsp_read(codec, rt5671_dsp_tab[i][0]);
  2402. + if (!val)
  2403. + continue;
  2404. + cnt += snprintf(buf + cnt, RT5671_DSP_REG_DISP_LEN,
  2405. + "%04x: %04x\n", rt5671_dsp_tab[i][0], val);
  2406. + }
  2407. +
  2408. + rt5671_dsp_tab = rt5671_dsp_init;
  2409. + tab_num = RT5671_DSP_INIT_NUM;
  2410. + for (i = 0; i < tab_num; i++) {
  2411. + if (cnt + RT5671_DSP_REG_DISP_LEN >= PAGE_SIZE)
  2412. + break;
  2413. + val = rt5671_dsp_read(codec, rt5671_dsp_tab[i][0]);
  2414. + if (!val)
  2415. + continue;
  2416. + cnt += snprintf(buf + cnt, RT5671_DSP_REG_DISP_LEN,
  2417. + "%04x: %04x\n",
  2418. + rt5671_dsp_tab[i][0], val);
  2419. + }
  2420. +
  2421. + rt5671_dsp_tab = rt5671_dsp_data_src;
  2422. + tab_num = RT5671_DSP_TDM_SRC_PAR_NUM;
  2423. + for (i = 0; i < tab_num; i++) {
  2424. + if (cnt + RT5671_DSP_REG_DISP_LEN >= PAGE_SIZE)
  2425. + break;
  2426. + val = rt5671_dsp_read(codec, rt5671_dsp_tab[i][0]);
  2427. + if (!val)
  2428. + continue;
  2429. + cnt += snprintf(buf + cnt, RT5671_DSP_REG_DISP_LEN,
  2430. + "%04x: %04x\n",
  2431. + rt5671_dsp_tab[i][0], val);
  2432. + }
  2433. +
  2434. + tab_num = RT5671_DSP_RATE_NUM;
  2435. + for (i = 0; i < tab_num; i++) {
  2436. + if (cnt + RT5671_DSP_REG_DISP_LEN >= PAGE_SIZE)
  2437. + break;
  2438. + val = rt5671_dsp_read(codec, rt5671_dsp_rate_par[i]);
  2439. + cnt += snprintf(buf + cnt, RT5671_DSP_REG_DISP_LEN,
  2440. + "%04x: %04x\n",
  2441. + rt5671_dsp_rate_par[i], val);
  2442. + }
  2443. + if (cnt + RT5671_DSP_REG_DISP_LEN < PAGE_SIZE) {
  2444. + val = rt5671_dsp_read(codec, 0x3fb5);
  2445. + cnt += snprintf(buf + cnt, RT5671_DSP_REG_DISP_LEN,
  2446. + "%04x: %04x\n",
  2447. + 0x3fb5, val);
  2448. + }
  2449. +dsp_done:
  2450. +
  2451. + if (cnt >= PAGE_SIZE)
  2452. + cnt = PAGE_SIZE - 1;
  2453. +
  2454. + return cnt;
  2455. +}
  2456. +
  2457. +static ssize_t dsp_reg_store(struct device *dev,
  2458. + struct device_attribute *attr, const char *buf, size_t count)
  2459. +{
  2460. + struct i2c_client *client = to_i2c_client(dev);
  2461. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  2462. + struct snd_soc_codec *codec = rt5671->codec;
  2463. + unsigned int val = 0, addr = 0;
  2464. + int i;
  2465. +
  2466. + pr_debug("register \"%s\" count = %d\n", buf, count);
  2467. +
  2468. + /* address */
  2469. + for (i = 0; i < count; i++)
  2470. + if (*(buf + i) <= '9' && *(buf + i) >= '0')
  2471. + addr = (addr << 4) | (*(buf + i) - '0');
  2472. + else if (*(buf + i) <= 'f' && *(buf + i) >= 'a')
  2473. + addr = (addr << 4) | ((*(buf + i) - 'a') + 0xa);
  2474. + else if (*(buf + i) <= 'A' && *(buf + i) >= 'A')
  2475. + addr = (addr << 4) | ((*(buf + i) - 'A') + 0xa);
  2476. + else
  2477. + break;
  2478. +
  2479. + /* Value*/
  2480. + for (i = i + 1; i < count; i++)
  2481. + if (*(buf + i) <= '9' && *(buf + i) >= '0')
  2482. + val = (val << 4) | (*(buf + i) - '0');
  2483. + else if (*(buf + i) <= 'f' && *(buf + i) >= 'a')
  2484. + val = (val << 4) | ((*(buf + i) - 'a') + 0xa);
  2485. + else if (*(buf + i) <= 'F' && *(buf + i) >= 'A')
  2486. + val = (val << 4) | ((*(buf + i) - 'A') + 0xa);
  2487. + else
  2488. + break;
  2489. +
  2490. + pr_debug("addr=0x%x val=0x%x\n", addr, val);
  2491. + if (i == count)
  2492. + pr_debug("0x%04x = 0x%04x\n",
  2493. + addr, rt5671_dsp_read(codec, addr));
  2494. + else
  2495. + rt5671_dsp_write(codec, addr, val);
  2496. +
  2497. + return count;
  2498. +}
  2499. +static DEVICE_ATTR(dsp_reg, 0664, rt5671_dsp_show, dsp_reg_store);
  2500. +
  2501. +/**
  2502. + * rt5671_dsp_probe - register DSP for rt5671
  2503. + * @codec: audio codec
  2504. + *
  2505. + * To register DSP function for rt5671.
  2506. + *
  2507. + * Returns 0 for success or negative error code.
  2508. + */
  2509. +int rt5671_dsp_probe(struct snd_soc_codec *codec)
  2510. +{
  2511. + int ret;
  2512. +
  2513. + if (codec == NULL)
  2514. + return -EINVAL;
  2515. +
  2516. + snd_soc_add_codec_controls(codec, rt5671_dsp_snd_controls,
  2517. + ARRAY_SIZE(rt5671_dsp_snd_controls));
  2518. + snd_soc_dapm_new_controls(&codec->dapm, rt5671_dsp_dapm_widgets,
  2519. + ARRAY_SIZE(rt5671_dsp_dapm_widgets));
  2520. + snd_soc_dapm_add_routes(&codec->dapm, rt5671_dsp_dapm_routes,
  2521. + ARRAY_SIZE(rt5671_dsp_dapm_routes));
  2522. +
  2523. + ret = device_create_file(codec->dev, &dev_attr_dsp_reg);
  2524. + if (ret != 0) {
  2525. + dev_err(codec->dev,
  2526. + "Failed to create dsp_reg sysfs files: %d\n", ret);
  2527. + return ret;
  2528. + }
  2529. +
  2530. + return 0;
  2531. +}
  2532. +EXPORT_SYMBOL_GPL(rt5671_dsp_probe);
  2533. +
  2534. +#ifdef RTK_IOCTL
  2535. +int rt5671_dsp_ioctl_common(struct snd_hwdep *hw,
  2536. + struct file *file, unsigned int cmd, unsigned long arg)
  2537. +{
  2538. + struct rt_codec_cmd rt_codec;
  2539. + int *buf;
  2540. + int *p;
  2541. + int ret;
  2542. +
  2543. + struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
  2544. + struct snd_soc_codec *codec = hw->private_data;
  2545. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  2546. +
  2547. + if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
  2548. + dev_err(codec->dev, "copy_from_user faild\n");
  2549. + return -EFAULT;
  2550. + }
  2551. + dev_dbg(codec->dev, "rt_codec.number=%d\n", rt_codec.number);
  2552. + buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
  2553. + if (buf == NULL)
  2554. + return -ENOMEM;
  2555. + if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number))
  2556. + goto err;
  2557. +
  2558. + ret = snd_soc_update_bits(codec, RT5671_PWR_DIG2,
  2559. + RT5671_PWR_I2S_DSP, RT5671_PWR_I2S_DSP);
  2560. + if (ret < 0) {
  2561. + dev_err(codec->dev,
  2562. + "Failed to power up DSP IIS interface: %d\n", ret);
  2563. + goto err;
  2564. + }
  2565. +
  2566. + switch (cmd) {
  2567. + case RT_READ_CODEC_DSP_IOCTL:
  2568. + for (p = buf; p < buf + rt_codec.number / 2; p++)
  2569. + *(p + rt_codec.number / 2) = rt5671_dsp_read(codec, *p);
  2570. + if (copy_to_user(rt_codec.buf, buf,
  2571. + sizeof(*buf) * rt_codec.number))
  2572. + goto err;
  2573. + break;
  2574. +
  2575. + case RT_WRITE_CODEC_DSP_IOCTL:
  2576. + if (codec == NULL) {
  2577. + dev_dbg(codec->dev, "codec is null\n");
  2578. + break;
  2579. + }
  2580. + for (p = buf; p < buf + rt_codec.number / 2; p++)
  2581. + rt5671_dsp_write(codec, *p, *(p + rt_codec.number / 2));
  2582. + break;
  2583. +
  2584. + case RT_GET_CODEC_DSP_MODE_IOCTL:
  2585. + *buf = rt5671->dsp_sw;
  2586. + if (copy_to_user(rt_codec.buf, buf,
  2587. + sizeof(*buf) * rt_codec.number))
  2588. + goto err;
  2589. + break;
  2590. +
  2591. + default:
  2592. + dev_info(codec->dev, "unsported dsp command\n");
  2593. + break;
  2594. + }
  2595. +
  2596. + kfree(buf);
  2597. + return 0;
  2598. +
  2599. +err:
  2600. + kfree(buf);
  2601. + return -EFAULT;
  2602. +}
  2603. +EXPORT_SYMBOL_GPL(rt5671_dsp_ioctl_common);
  2604. +#endif
  2605. +
  2606. +#ifdef CONFIG_PM
  2607. +int rt5671_dsp_suspend(struct snd_soc_codec *codec)
  2608. +{
  2609. + return 0;
  2610. +}
  2611. +EXPORT_SYMBOL_GPL(rt5671_dsp_suspend);
  2612. +
  2613. +int rt5671_dsp_resume(struct snd_soc_codec *codec)
  2614. +{
  2615. + return 0;
  2616. +}
  2617. +EXPORT_SYMBOL_GPL(rt5671_dsp_resume);
  2618. +#endif
  2619. +
  2620. diff --git a/sound/soc/codecs/rt5671-dsp.h b/sound/soc/codecs/rt5671-dsp.h
  2621. new file mode 100644
  2622. index 0000000..d4651b2
  2623. --- /dev/null
  2624. +++ b/sound/soc/codecs/rt5671-dsp.h
  2625. @@ -0,0 +1,82 @@
  2626. +/*
  2627. + * rt5671-dsp.h -- RT5671 ALSA SoC DSP driver
  2628. + *
  2629. + * Copyright 2011 Realtek Microelectronics
  2630. + * Copyright (C) 2016 XiaoMi, Inc.
  2631. + * Author: Johnny Hsu <johnnyhsu@realtek.com>
  2632. + *
  2633. + * This program is free software; you can redistribute it and/or modify
  2634. + * it under the terms of the GNU General Public License version 2 as
  2635. + * published by the Free Software Foundation.
  2636. + */
  2637. +
  2638. +#ifndef __RT5671_DSP_H__
  2639. +#define __RT5671_DSP_H__
  2640. +
  2641. +#define RT5671_DSP_CTRL1 0xe0
  2642. +#define RT5671_DSP_CTRL2 0xe1
  2643. +#define RT5671_DSP_CTRL3 0xe2
  2644. +#define RT5671_DSP_CTRL4 0xe3
  2645. +#define RT5671_DSP_CTRL5 0xe4
  2646. +
  2647. +/* DSP Control 1 (0xe0) */
  2648. +#define RT5671_DSP_CMD_MASK (0xff << 8)
  2649. +#define RT5671_DSP_CMD_PE (0x0d << 8) /* Patch Entry */
  2650. +#define RT5671_DSP_CMD_MW (0x3b << 8) /* Memory Write */
  2651. +#define RT5671_DSP_CMD_MR (0x37 << 8) /* Memory Read */
  2652. +#define RT5671_DSP_CMD_RR (0x60 << 8) /* Register Read */
  2653. +#define RT5671_DSP_CMD_RW (0x68 << 8) /* Register Write */
  2654. +#define RT5671_DSP_REG_DATHI (0x26 << 8) /* High Data Addr */
  2655. +#define RT5671_DSP_REG_DATLO (0x25 << 8) /* Low Data Addr */
  2656. +#define RT5671_DSP_CLK_MASK (0x3 << 6)
  2657. +#define RT5671_DSP_CLK_SFT 6
  2658. +#define RT5671_DSP_CLK_768K (0x0 << 6)
  2659. +#define RT5671_DSP_CLK_384K (0x1 << 6)
  2660. +#define RT5671_DSP_CLK_192K (0x2 << 6)
  2661. +#define RT5671_DSP_CLK_96K (0x3 << 6)
  2662. +#define RT5671_DSP_BUSY_MASK (0x1 << 5)
  2663. +#define RT5671_DSP_RW_MASK (0x1 << 4)
  2664. +#define RT5671_DSP_DL_MASK (0x3 << 2)
  2665. +#define RT5671_DSP_DL_0 (0x0 << 2)
  2666. +#define RT5671_DSP_DL_1 (0x1 << 2)
  2667. +#define RT5671_DSP_DL_2 (0x2 << 2)
  2668. +#define RT5671_DSP_DL_3 (0x3 << 2)
  2669. +#define RT5671_DSP_I2C_AL_16 (0x1 << 1)
  2670. +#define RT5671_DSP_CMD_EN (0x1)
  2671. +
  2672. +/* Debug String Length */
  2673. +#define RT5671_DSP_REG_DISP_LEN 25
  2674. +
  2675. +
  2676. +enum {
  2677. + RT5671_DSP_DIS,
  2678. + RT5671_DSP_TWO_MIC_AEC,
  2679. + RT5671_DSP_TWO_MIC_EZAEC,
  2680. + RT5671_DSP_ONE_MIC_AEC,
  2681. + RT5671_DSP_ONE_MIC_EZAEC,
  2682. + RT5671_DSP_BM_48K_STO_FFP_NS,
  2683. + RT5671_DSP_HS_AEC,
  2684. + RT5671_DSP_HS_48K_STO_FFP_NS,
  2685. + RT5671_DSP_BT_AEC,
  2686. + RT5671_DSP_BT_EZAEC,
  2687. +};
  2688. +
  2689. +struct rt5671_dsp_param {
  2690. + u16 cmd_fmt;
  2691. + u16 addr;
  2692. + u16 data;
  2693. + u8 cmd;
  2694. +};
  2695. +
  2696. +int rt5671_dsp_probe(struct snd_soc_codec *codec);
  2697. +int rt5671_dsp_ioctl_common(struct snd_hwdep *hw,
  2698. + struct file *file, unsigned int cmd, unsigned long arg);
  2699. +#ifdef CONFIG_PM
  2700. +int rt5671_dsp_suspend(struct snd_soc_codec *codec);
  2701. +int rt5671_dsp_resume(struct snd_soc_codec *codec);
  2702. +#endif
  2703. +unsigned int rt5671_dsp_read(struct snd_soc_codec *codec, unsigned int reg);
  2704. +int rt5671_dsp_write(struct snd_soc_codec *codec, unsigned int addr, unsigned int data);
  2705. +
  2706. +#endif /* __RT5671_DSP_H__ */
  2707. +
  2708. diff --git a/sound/soc/codecs/rt5671.c b/sound/soc/codecs/rt5671.c
  2709. new file mode 100755
  2710. index 0000000..70655507
  2711. --- /dev/null
  2712. +++ b/sound/soc/codecs/rt5671.c
  2713. @@ -0,0 +1,4513 @@
  2714. +/*
  2715. + * rt5671.c -- RT5671 ALSA SoC audio codec driver
  2716. + *
  2717. + * Copyright 2012 Realtek Semiconductor Corp.
  2718. + * Copyright (C) 2016 XiaoMi, Inc.
  2719. + * Author: Bard Liao <bardliao@realtek.com>
  2720. + *
  2721. + * This program is free software; you can redistribute it and/or modify
  2722. + * it under the terms of the GNU General Public License version 2 as
  2723. + * published by the Free Software Foundation.
  2724. + */
  2725. +
  2726. +#include <linux/module.h>
  2727. +#include <linux/moduleparam.h>
  2728. +#include <linux/init.h>
  2729. +#include <linux/delay.h>
  2730. +#include <linux/pm.h>
  2731. +#include <linux/i2c.h>
  2732. +#include <linux/platform_device.h>
  2733. +#include <linux/spi/spi.h>
  2734. +#include <sound/core.h>
  2735. +#include <sound/pcm.h>
  2736. +#include <sound/pcm_params.h>
  2737. +#include <sound/jack.h>
  2738. +#include <sound/soc.h>
  2739. +#include <sound/soc-dapm.h>
  2740. +#include <sound/initval.h>
  2741. +#include <sound/rt5670.h>
  2742. +#include <sound/tlv.h>
  2743. +
  2744. +#define RTK_IOCTL
  2745. +#ifdef RTK_IOCTL
  2746. +#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
  2747. +#include "rt_codec_ioctl.h"
  2748. +#include "rt5671_ioctl.h"
  2749. +#endif
  2750. +#endif
  2751. +
  2752. +#include "rt5671.h"
  2753. +#include "rt5671-dsp.h"
  2754. +
  2755. +static int pmu_depop_time = 80;
  2756. +module_param(pmu_depop_time, int, 0644);
  2757. +
  2758. +static int hp_amp_time = 20;
  2759. +module_param(hp_amp_time, int, 0644);
  2760. +
  2761. +#define RT5671_DET_EXT_MIC 0
  2762. +/*#define USE_INT_CLK*/
  2763. +/*#define ALC_DRC_FUNC*/
  2764. +/*#define USE_TDM*/
  2765. +/*#define NVIDIA_DALMORE*/
  2766. +
  2767. +#define VERSION "0.0.5 alsa 1.0.25"
  2768. +
  2769. +struct rt5671_init_reg {
  2770. + u8 reg;
  2771. + u16 val;
  2772. +};
  2773. +
  2774. +static struct rt5671_init_reg init_list[] = {
  2775. + { RT5671_GEN_CTRL3 , 0x0084 },
  2776. + { RT5671_IL_CMD1 , 0x0000 },
  2777. + { RT5671_IL_CMD2 , 0x0010 }, /* set Inline Command Window */
  2778. + { RT5671_IL_CMD3 , 0x0014 },
  2779. + { RT5671_PRIV_INDEX , 0x0014 },
  2780. + { RT5671_PRIV_DATA , 0x9a8a },
  2781. + { RT5671_PRIV_INDEX , 0x003d },
  2782. + { RT5671_PRIV_DATA , 0x3e40 },
  2783. + { RT5671_PRIV_INDEX , 0x0038 },
  2784. + { RT5671_PRIV_DATA , 0x1fe1 },
  2785. + { RT5671_TDM_CTRL_3 , 0x0101 }, /* enable IF1_DAC2 */
  2786. + { RT5671_CHARGE_PUMP , 0x0c00 },
  2787. + /* for stereo SPK */
  2788. + { RT5671_GPIO_CTRL2 , 0x8000 },
  2789. + { RT5671_GPIO_CTRL3 , 0x0d00 },
  2790. + /* Mute STO1 ADC for depop */
  2791. + { RT5671_STO1_ADC_DIG_VOL, 0xafaf },
  2792. + { RT5671_ASRC_4 , 0x8020 },
  2793. +};
  2794. +#define RT5671_INIT_REG_LEN ARRAY_SIZE(init_list)
  2795. +
  2796. +#ifdef ALC_DRC_FUNC
  2797. +static struct rt5671_init_reg alc_drc_list[] = {
  2798. + { RT5671_ALC_DRC_CTRL1 , 0x0000 },
  2799. + { RT5671_ALC_DRC_CTRL2 , 0x0000 },
  2800. + { RT5671_ALC_CTRL_2 , 0x0000 },
  2801. + { RT5671_ALC_CTRL_3 , 0x0000 },
  2802. + { RT5671_ALC_CTRL_4 , 0x0000 },
  2803. + { RT5671_ALC_CTRL_1 , 0x0000 },
  2804. +};
  2805. +#define RT5671_ALC_DRC_REG_LEN ARRAY_SIZE(alc_drc_list)
  2806. +#endif
  2807. +
  2808. +static int rt5671_reg_init(struct snd_soc_codec *codec)
  2809. +{
  2810. + int i;
  2811. +
  2812. + for (i = 0; i < RT5671_INIT_REG_LEN; i++)
  2813. + snd_soc_write(codec, init_list[i].reg, init_list[i].val);
  2814. +#ifdef ALC_DRC_FUNC
  2815. + for (i = 0; i < RT5671_ALC_DRC_REG_LEN; i++)
  2816. + snd_soc_write(codec, alc_drc_list[i].reg, alc_drc_list[i].val);
  2817. +#endif
  2818. +
  2819. + return 0;
  2820. +}
  2821. +
  2822. +static int rt5671_index_sync(struct snd_soc_codec *codec)
  2823. +{
  2824. + int i;
  2825. +
  2826. + for (i = 0; i < RT5671_INIT_REG_LEN; i++)
  2827. + if (RT5671_PRIV_INDEX == init_list[i].reg ||
  2828. + RT5671_PRIV_DATA == init_list[i].reg)
  2829. + snd_soc_write(codec, init_list[i].reg,
  2830. + init_list[i].val);
  2831. + return 0;
  2832. +}
  2833. +
  2834. +static const u16 rt5671_reg[RT5671_VENDOR_ID2 + 1] = {
  2835. + [RT5671_HP_VOL] = 0x8888,
  2836. + [RT5671_LOUT1] = 0x8888,
  2837. + [RT5671_MONO_OUT] = 0x8800,
  2838. + [RT5671_CJ_CTRL1] = 0x0001,
  2839. + [RT5671_CJ_CTRL2] = 0x0827,
  2840. + [RT5671_IN2] = 0x0008,
  2841. + [RT5671_INL1_INR1_VOL] = 0x0808,
  2842. + [RT5671_SIDETONE_CTRL] = 0x018b,
  2843. + [RT5671_DAC1_DIG_VOL] = 0xafaf,
  2844. + [RT5671_DAC2_DIG_VOL] = 0xafaf,
  2845. + [RT5671_DAC_CTRL] = 0x0011,
  2846. + [RT5671_STO1_ADC_DIG_VOL] = 0x2f2f,
  2847. + [RT5671_MONO_ADC_DIG_VOL] = 0x2f2f,
  2848. + [RT5671_STO2_ADC_DIG_VOL] = 0x2f2f,
  2849. + [RT5671_STO2_ADC_MIXER] = 0x7860,
  2850. + [RT5671_STO1_ADC_MIXER] = 0x7860,
  2851. + [RT5671_MONO_ADC_MIXER] = 0x7871,
  2852. + [RT5671_AD_DA_MIXER] = 0x8080,
  2853. + [RT5671_STO_DAC_MIXER] = 0x5656,
  2854. + [RT5671_MONO_DAC_MIXER] = 0x5454,
  2855. + [RT5671_DIG_MIXER] = 0xaaa0,
  2856. + [RT5671_DSP_PATH2] = 0x2f2f,
  2857. + [RT5671_DIG_INF1_DATA] = 0x1002,
  2858. + [RT5671_PDM_OUT_CTRL] = 0x5f00,
  2859. + [RT5671_REC_L2_MIXER] = 0x007f,
  2860. + [RT5671_REC_R2_MIXER] = 0x007f,
  2861. + [RT5671_REC_MONO2_MIXER] = 0x001f,
  2862. + [RT5671_HPO_MIXER] = 0xe00f,
  2863. + [RT5671_MONO_MIXER] = 0x5380,
  2864. + [RT5671_OUT_L1_MIXER] = 0x0073,
  2865. + [RT5671_OUT_R1_MIXER] = 0x00d3,
  2866. + [RT5671_LOUT_MIXER] = 0xf0f0,
  2867. + [RT5671_PWR_DIG2] = 0x0001,
  2868. + [RT5671_PWR_ANLG1] = 0x00c3,
  2869. + [RT5671_I2S4_SDP] = 0x8000,
  2870. + [RT5671_I2S1_SDP] = 0x8000,
  2871. + [RT5671_I2S2_SDP] = 0x8000,
  2872. + [RT5671_I2S3_SDP] = 0x8000,
  2873. + [RT5671_ADDA_CLK1] = 0x7770,
  2874. + [RT5671_ADDA_HPF] = 0x0e00,
  2875. + [RT5671_DMIC_CTRL1] = 0x1505,
  2876. + [RT5671_DMIC_CTRL2] = 0x0015,
  2877. + [RT5671_TDM_CTRL_1] = 0x0c00,
  2878. + [RT5671_TDM_CTRL_2] = 0x4000,
  2879. + [RT5671_TDM_CTRL_3] = 0x0123,
  2880. + [RT5671_DSP_CLK] = 0x1100,
  2881. + [RT5671_ASRC_5] = 0x0003,
  2882. + [RT5671_DEPOP_M1] = 0x0004,
  2883. + [RT5671_DEPOP_M2] = 0x1100,
  2884. + [RT5671_DEPOP_M3] = 0x0646,
  2885. + [RT5671_CHARGE_PUMP] = 0x0c06,
  2886. + [RT5671_VAD_CTRL1] = 0x2184,
  2887. + [RT5671_VAD_CTRL2] = 0x010a,
  2888. + [RT5671_VAD_CTRL3] = 0x0aea,
  2889. + [RT5671_VAD_CTRL4] = 0x000c,
  2890. + [RT5671_VAD_CTRL5] = 0x0400,
  2891. + [RT5671_ADC_EQ_CTRL1] = 0x7000,
  2892. + [RT5671_EQ_CTRL1] = 0x7000,
  2893. + [RT5671_ALC_DRC_CTRL2] = 0x001f,
  2894. + [RT5671_ALC_CTRL_1] = 0x220c,
  2895. + [RT5671_ALC_CTRL_2] = 0x1f00,
  2896. + [RT5671_BASE_BACK] = 0x1813,
  2897. + [RT5671_MP3_PLUS1] = 0x0690,
  2898. + [RT5671_MP3_PLUS2] = 0x1c17,
  2899. + [RT5671_ADJ_HPF1] = 0xa220,
  2900. + [RT5671_HP_CALIB_AMP_DET] = 0x0400,
  2901. + [RT5671_SV_ZCD1] = 0x0809,
  2902. + [RT5671_IL_CMD1] = 0x0001,
  2903. + [RT5671_IL_CMD2] = 0x0049,
  2904. + [RT5671_IL_CMD3] = 0x0024,
  2905. + [RT5671_DRC_HL_CTRL1] = 0x8000,
  2906. + [RT5671_ADC_MONO_HP_CTRL1] = 0xa200,
  2907. + [RT5671_ADC_STO2_HP_CTRL1] = 0xa200,
  2908. + [RT5671_GEN_CTRL1] = 0x8010,
  2909. + [RT5671_GEN_CTRL2] = 0x0033,
  2910. + [RT5671_GEN_CTRL3] = 0x0080,
  2911. +};
  2912. +
  2913. +static int rt5671_reset(struct snd_soc_codec *codec)
  2914. +{
  2915. + return snd_soc_write(codec, RT5671_RESET, 0);
  2916. +}
  2917. +
  2918. +/**
  2919. + * rt5671_index_write - Write private register.
  2920. + * @codec: SoC audio codec device.
  2921. + * @reg: Private register index.
  2922. + * @value: Private register Data.
  2923. + *
  2924. + * Modify private register for advanced setting. It can be written through
  2925. + * private index (0x6a) and data (0x6c) register.
  2926. + *
  2927. + * Returns 0 for success or negative error code.
  2928. + */
  2929. +static int rt5671_index_write(struct snd_soc_codec *codec,
  2930. + unsigned int reg, unsigned int value)
  2931. +{
  2932. + int ret;
  2933. +
  2934. + ret = snd_soc_write(codec, RT5671_PRIV_INDEX, reg);
  2935. + if (ret < 0) {
  2936. + dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
  2937. + goto err;
  2938. + }
  2939. + ret = snd_soc_write(codec, RT5671_PRIV_DATA, value);
  2940. + if (ret < 0) {
  2941. + dev_err(codec->dev, "Failed to set private value: %d\n", ret);
  2942. + goto err;
  2943. + }
  2944. + return 0;
  2945. +
  2946. +err:
  2947. + return ret;
  2948. +}
  2949. +
  2950. +/**
  2951. + * rt5671_index_read - Read private register.
  2952. + * @codec: SoC audio codec device.
  2953. + * @reg: Private register index.
  2954. + *
  2955. + * Read advanced setting from private register. It can be read through
  2956. + * private index (0x6a) and data (0x6c) register.
  2957. + *
  2958. + * Returns private register value or negative error code.
  2959. + */
  2960. +static unsigned int rt5671_index_read(
  2961. + struct snd_soc_codec *codec, unsigned int reg)
  2962. +{
  2963. + int ret;
  2964. +
  2965. + ret = snd_soc_write(codec, RT5671_PRIV_INDEX, reg);
  2966. + if (ret < 0) {
  2967. + dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
  2968. + return ret;
  2969. + }
  2970. + return snd_soc_read(codec, RT5671_PRIV_DATA);
  2971. +}
  2972. +
  2973. +/**
  2974. + * rt5671_index_update_bits - update private register bits
  2975. + * @codec: audio codec
  2976. + * @reg: Private register index.
  2977. + * @mask: register mask
  2978. + * @value: new value
  2979. + *
  2980. + * Writes new register value.
  2981. + *
  2982. + * Returns 1 for change, 0 for no change, or negative error code.
  2983. + */
  2984. +static int rt5671_index_update_bits(struct snd_soc_codec *codec,
  2985. + unsigned int reg, unsigned int mask, unsigned int value)
  2986. +{
  2987. + unsigned int old, new;
  2988. + int change, ret;
  2989. +
  2990. + ret = rt5671_index_read(codec, reg);
  2991. + if (ret < 0) {
  2992. + dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
  2993. + goto err;
  2994. + }
  2995. +
  2996. + old = ret;
  2997. + new = (old & ~mask) | (value & mask);
  2998. + change = old != new;
  2999. + if (change) {
  3000. + ret = rt5671_index_write(codec, reg, new);
  3001. + if (ret < 0) {
  3002. + dev_err(codec->dev,
  3003. + "Failed to write private reg: %d\n", ret);
  3004. + goto err;
  3005. + }
  3006. + }
  3007. + return change;
  3008. +
  3009. +err:
  3010. + return ret;
  3011. +}
  3012. +
  3013. +static int rt5671_volatile_register(
  3014. + struct snd_soc_codec *codec, unsigned int reg)
  3015. +{
  3016. + switch (reg) {
  3017. + case RT5671_RESET:
  3018. + case RT5671_PDM_DATA_CTRL1:
  3019. + case RT5671_PDM1_DATA_CTRL4:
  3020. + case RT5671_PDM2_DATA_CTRL4:
  3021. + case RT5671_PRIV_DATA:
  3022. + case RT5671_CJ_CTRL1:
  3023. + case RT5671_CJ_CTRL2:
  3024. + case RT5671_CJ_CTRL3:
  3025. + case RT5671_A_JD_CTRL1:
  3026. + case RT5671_A_JD_CTRL2:
  3027. + case RT5671_VAD_CTRL5:
  3028. + case RT5671_ADC_EQ_CTRL1:
  3029. + case RT5671_EQ_CTRL1:
  3030. + case RT5671_ALC_CTRL_1:
  3031. + case RT5671_IRQ_CTRL1:
  3032. + case RT5671_IRQ_CTRL2:
  3033. + case RT5671_IRQ_CTRL3:
  3034. + case RT5671_IL_CMD1:
  3035. + case RT5671_DSP_CTRL1:
  3036. + case RT5671_DSP_CTRL2:
  3037. + case RT5671_DSP_CTRL3:
  3038. + case RT5671_DSP_CTRL4:
  3039. + case RT5671_DSP_CTRL5:
  3040. + case RT5671_JD_CTRL3:
  3041. + case RT5671_VENDOR_ID:
  3042. + case RT5671_VENDOR_ID1:
  3043. + case RT5671_VENDOR_ID2:
  3044. + return 1;
  3045. + default:
  3046. + return 0;
  3047. + }
  3048. +}
  3049. +
  3050. +static int rt5671_readable_register(
  3051. + struct snd_soc_codec *codec, unsigned int reg)
  3052. +{
  3053. + switch (reg) {
  3054. + case RT5671_RESET:
  3055. + case RT5671_HP_VOL:
  3056. + case RT5671_LOUT1:
  3057. + case RT5671_MONO_OUT:
  3058. + case RT5671_CJ_CTRL1:
  3059. + case RT5671_CJ_CTRL2:
  3060. + case RT5671_CJ_CTRL3:
  3061. + case RT5671_IN2:
  3062. + case RT5671_IN3_IN4:
  3063. + case RT5671_INL1_INR1_VOL:
  3064. + case RT5671_SIDETONE_CTRL:
  3065. + case RT5671_DAC1_DIG_VOL:
  3066. + case RT5671_DAC2_DIG_VOL:
  3067. + case RT5671_DAC_CTRL:
  3068. + case RT5671_STO1_ADC_DIG_VOL:
  3069. + case RT5671_MONO_ADC_DIG_VOL:
  3070. + case RT5671_STO2_ADC_DIG_VOL:
  3071. + case RT5671_ADC_BST_VOL1:
  3072. + case RT5671_ADC_BST_VOL2:
  3073. + case RT5671_STO2_ADC_MIXER:
  3074. + case RT5671_STO1_ADC_MIXER:
  3075. + case RT5671_MONO_ADC_MIXER:
  3076. + case RT5671_AD_DA_MIXER:
  3077. + case RT5671_STO_DAC_MIXER:
  3078. + case RT5671_MONO_DAC_MIXER:
  3079. + case RT5671_DIG_MIXER:
  3080. + case RT5671_DSP_PATH1:
  3081. + case RT5671_DSP_PATH2:
  3082. + case RT5671_DIG_INF1_DATA:
  3083. + case RT5671_DIG_INF2_DATA:
  3084. + case RT5671_PDM_OUT_CTRL:
  3085. + case RT5671_PDM_DATA_CTRL1:
  3086. + case RT5671_PDM1_DATA_CTRL2:
  3087. + case RT5671_PDM1_DATA_CTRL3:
  3088. + case RT5671_PDM1_DATA_CTRL4:
  3089. + case RT5671_PDM2_DATA_CTRL2:
  3090. + case RT5671_PDM2_DATA_CTRL3:
  3091. + case RT5671_PDM2_DATA_CTRL4:
  3092. + case RT5671_REC_L1_MIXER:
  3093. + case RT5671_REC_L2_MIXER:
  3094. + case RT5671_REC_R1_MIXER:
  3095. + case RT5671_REC_R2_MIXER:
  3096. + case RT5671_REC_MONO1_MIXER:
  3097. + case RT5671_REC_MONO2_MIXER:
  3098. + case RT5671_HPO_MIXER:
  3099. + case RT5671_MONO_MIXER:
  3100. + case RT5671_OUT_L1_MIXER:
  3101. + case RT5671_OUT_R1_MIXER:
  3102. + case RT5671_LOUT_MIXER:
  3103. + case RT5671_PWR_DIG1:
  3104. + case RT5671_PWR_DIG2:
  3105. + case RT5671_PWR_ANLG1:
  3106. + case RT5671_PWR_ANLG2:
  3107. + case RT5671_PWR_MIXER:
  3108. + case RT5671_PWR_VOL:
  3109. + case RT5671_PRIV_INDEX:
  3110. + case RT5671_PRIV_DATA:
  3111. + case RT5671_I2S4_SDP:
  3112. + case RT5671_I2S1_SDP:
  3113. + case RT5671_I2S2_SDP:
  3114. + case RT5671_I2S3_SDP:
  3115. + case RT5671_ADDA_CLK1:
  3116. + case RT5671_ADDA_HPF:
  3117. + case RT5671_DMIC_CTRL1:
  3118. + case RT5671_DMIC_CTRL2:
  3119. + case RT5671_TDM_CTRL_1:
  3120. + case RT5671_TDM_CTRL_2:
  3121. + case RT5671_TDM_CTRL_3:
  3122. + case RT5671_DSP_CLK:
  3123. + case RT5671_GLB_CLK:
  3124. + case RT5671_PLL_CTRL1:
  3125. + case RT5671_PLL_CTRL2:
  3126. + case RT5671_ASRC_1:
  3127. + case RT5671_ASRC_2:
  3128. + case RT5671_ASRC_3:
  3129. + case RT5671_ASRC_4:
  3130. + case RT5671_ASRC_5:
  3131. + case RT5671_ASRC_I2S1:
  3132. + case RT5671_ASRC_I2S2:
  3133. + case RT5671_ASRC_I2S3:
  3134. + case RT5671_DEPOP_M1:
  3135. + case RT5671_DEPOP_M2:
  3136. + case RT5671_DEPOP_M3:
  3137. + case RT5671_CHARGE_PUMP:
  3138. + case RT5671_MICBIAS:
  3139. + case RT5671_A_JD_CTRL1:
  3140. + case RT5671_A_JD_CTRL2:
  3141. + case RT5671_VAD_CTRL1:
  3142. + case RT5671_VAD_CTRL2:
  3143. + case RT5671_VAD_CTRL3:
  3144. + case RT5671_VAD_CTRL4:
  3145. + case RT5671_VAD_CTRL5:
  3146. + case RT5671_ADC_EQ_CTRL1:
  3147. + case RT5671_ADC_EQ_CTRL2:
  3148. + case RT5671_EQ_CTRL1:
  3149. + case RT5671_EQ_CTRL2:
  3150. + case RT5671_ALC_DRC_CTRL1:
  3151. + case RT5671_ALC_DRC_CTRL2:
  3152. + case RT5671_ALC_CTRL_1:
  3153. + case RT5671_ALC_CTRL_2:
  3154. + case RT5671_ALC_CTRL_3:
  3155. + case RT5671_ALC_CTRL_4:
  3156. + case RT5671_JD_CTRL1:
  3157. + case RT5671_JD_CTRL2:
  3158. + case RT5671_IRQ_CTRL1:
  3159. + case RT5671_IRQ_CTRL2:
  3160. + case RT5671_IRQ_CTRL3:
  3161. + case RT5671_GPIO_CTRL1:
  3162. + case RT5671_GPIO_CTRL2:
  3163. + case RT5671_GPIO_CTRL3:
  3164. + case RT5671_SCRABBLE_FUN:
  3165. + case RT5671_SCRABBLE_CTRL:
  3166. + case RT5671_BASE_BACK:
  3167. + case RT5671_MP3_PLUS1:
  3168. + case RT5671_MP3_PLUS2:
  3169. + case RT5671_ADJ_HPF1:
  3170. + case RT5671_ADJ_HPF2:
  3171. + case RT5671_HP_CALIB_AMP_DET:
  3172. + case RT5671_SV_ZCD1:
  3173. + case RT5671_SV_ZCD2:
  3174. + case RT5671_IL_CMD1:
  3175. + case RT5671_IL_CMD2:
  3176. + case RT5671_IL_CMD3:
  3177. + case RT5671_DRC_HL_CTRL1:
  3178. + case RT5671_DRC_HL_CTRL2:
  3179. + case RT5671_ADC_MONO_HP_CTRL1:
  3180. + case RT5671_ADC_MONO_HP_CTRL2:
  3181. + case RT5671_ADC_STO2_HP_CTRL1:
  3182. + case RT5671_ADC_STO2_HP_CTRL2:
  3183. + case RT5671_JD_CTRL3:
  3184. + case RT5671_JD_CTRL4:
  3185. + case RT5671_GEN_CTRL1:
  3186. + case RT5671_DSP_CTRL1:
  3187. + case RT5671_DSP_CTRL2:
  3188. + case RT5671_DSP_CTRL3:
  3189. + case RT5671_DSP_CTRL4:
  3190. + case RT5671_DSP_CTRL5:
  3191. + case RT5671_GEN_CTRL2:
  3192. + case RT5671_GEN_CTRL3:
  3193. + case RT5671_VENDOR_ID:
  3194. + case RT5671_VENDOR_ID1:
  3195. + case RT5671_VENDOR_ID2:
  3196. + return 1;
  3197. + default:
  3198. + return 0;
  3199. + }
  3200. +}
  3201. +
  3202. +/**
  3203. + * rt5671_headset_detect - Detect headset.
  3204. + * @codec: SoC audio codec device.
  3205. + * @jack_insert: Jack insert or not.
  3206. + *
  3207. + * Detect whether is headset or not when jack inserted.
  3208. + *
  3209. + * Returns detect status.
  3210. + */
  3211. +
  3212. +int rt5671_headset_detect(struct snd_soc_codec *codec, int jack_insert)
  3213. +{
  3214. + int val;
  3215. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3216. +
  3217. + if (jack_insert) {
  3218. + snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
  3219. + snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
  3220. + snd_soc_dapm_sync(&codec->dapm);
  3221. + snd_soc_update_bits(codec, RT5671_GEN_CTRL2,
  3222. + 0x0400, 0x0400);
  3223. + snd_soc_update_bits(codec, RT5671_CJ_CTRL2,
  3224. + RT5671_CBJ_DET_MODE, RT5671_CBJ_DET_MODE);
  3225. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  3226. + RT5671_PWR_JD1, RT5671_PWR_JD1);
  3227. + snd_soc_update_bits(codec, RT5671_CJ_CTRL1, 0x20, 0x20);
  3228. + msleep(300);
  3229. + val = snd_soc_read(codec, RT5671_JD_CTRL3) & 0x7000;
  3230. + if (val == 0x7000) {
  3231. + rt5671->jack_type = SND_JACK_HEADSET;
  3232. +
  3233. + snd_soc_update_bits(codec, RT5671_CJ_CTRL1, 0x0180, 0x0180);
  3234. + snd_soc_update_bits(codec, RT5671_JD_CTRL3, 0x00c0, 0x00c0);
  3235. +
  3236. + snd_soc_update_bits(codec, RT5671_IRQ_CTRL3, 0x8, 0x8);
  3237. + snd_soc_update_bits(codec, RT5671_IL_CMD1, 0x40, 0x40);
  3238. + snd_soc_read(codec, RT5671_IL_CMD1);
  3239. + } else {
  3240. + rt5671->jack_type = SND_JACK_HEADPHONE;
  3241. + snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
  3242. + snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
  3243. + snd_soc_dapm_sync(&codec->dapm);
  3244. + }
  3245. + } else {
  3246. + snd_soc_update_bits(codec, RT5671_IL_CMD1, 0x40, 0x0);
  3247. + snd_soc_update_bits(codec, RT5671_IRQ_CTRL3, 0x8, 0x0);
  3248. + snd_soc_update_bits(codec, RT5671_CJ_CTRL1, 0x0180, 0x0);
  3249. + snd_soc_update_bits(codec, RT5671_JD_CTRL3, 0x00c0, 0x0);
  3250. + rt5671->jack_type = 0;
  3251. + snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
  3252. + snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
  3253. + snd_soc_dapm_sync(&codec->dapm);
  3254. + }
  3255. +
  3256. + pr_debug("jack_type = %d\n", rt5671->jack_type);
  3257. + return rt5671->jack_type;
  3258. +}
  3259. +EXPORT_SYMBOL(rt5671_headset_detect);
  3260. +
  3261. +int rt5671_button_detect(struct snd_soc_codec *codec)
  3262. +{
  3263. + int btn_type, val;
  3264. +
  3265. + val = snd_soc_read(codec, RT5671_IL_CMD1);
  3266. + btn_type = val & 0xff80;
  3267. + snd_soc_write(codec, RT5671_IL_CMD1, val);
  3268. + if (btn_type != 0) {
  3269. + msleep(20);
  3270. + val = snd_soc_read(codec, RT5671_IL_CMD1);
  3271. + snd_soc_write(codec, RT5671_IL_CMD1, val);
  3272. + }
  3273. + return btn_type;
  3274. +}
  3275. +EXPORT_SYMBOL(rt5671_button_detect);
  3276. +
  3277. +int rt5671_check_interrupt_event(struct snd_soc_codec *codec, int *data)
  3278. +{
  3279. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3280. + int val, event_type;
  3281. +
  3282. + if (snd_soc_read(codec, 0xbe) & 0x0080)
  3283. + return RT5671_VAD_EVENT;
  3284. +
  3285. + if (1 == rt5671->pdata.jd_mode) /* 2 port */
  3286. + val = snd_soc_read(codec, RT5671_A_JD_CTRL1) & 0x0070;
  3287. + else
  3288. + val = snd_soc_read(codec, RT5671_A_JD_CTRL1) & 0x0020;
  3289. +
  3290. + *data = 0;
  3291. + switch (val) {
  3292. + case 0x30: /* 2 port */
  3293. + case 0x0: /* 1 port or 2 port */
  3294. + /* jack insert */
  3295. + if (rt5671->jack_type == 0) {
  3296. + rt5671_headset_detect(codec, 1);
  3297. + *data = rt5671->jack_type;
  3298. + return RT5671_J_IN_EVENT;
  3299. + }
  3300. + event_type = 0;
  3301. + if (snd_soc_read(codec, RT5671_IRQ_CTRL3) & 0x4) {
  3302. + /* button event */
  3303. + event_type = RT5671_BTN_EVENT;
  3304. + *data = rt5671_button_detect(codec);
  3305. + }
  3306. + if (*data == 0) {
  3307. + event_type = RT5671_BR_EVENT;
  3308. + }
  3309. + return (event_type == 0 ? RT5671_UN_EVENT : event_type);
  3310. + case 0x70: /* 2 port */
  3311. + case 0x10: /* 2 port */
  3312. + case 0x20: /* 1 port */
  3313. + snd_soc_update_bits(codec, RT5671_IRQ_CTRL3, 0x1, 0x0);
  3314. + rt5671_headset_detect(codec, 0);
  3315. + return RT5671_J_OUT_EVENT;
  3316. + default:
  3317. + return RT5671_UN_EVENT;
  3318. + }
  3319. +
  3320. + return RT5671_UN_EVENT;
  3321. +
  3322. +}
  3323. +EXPORT_SYMBOL(rt5671_check_interrupt_event);
  3324. +
  3325. +static int rt5671_irq_detection(struct snd_soc_jack_gpio *gpio)
  3326. +{
  3327. + struct snd_soc_jack *jack = gpio->jack;
  3328. + struct snd_soc_codec *codec = jack->codec;
  3329. + int status, jack_type = jack->status;
  3330. + int data;
  3331. +
  3332. + pr_debug("Enter:%s", __func__);
  3333. + status = rt5671_check_interrupt_event(codec, &data);
  3334. + switch (status) {
  3335. + case RT5671_J_IN_EVENT:
  3336. + pr_debug("Jack insert intr");
  3337. + jack_type = data;
  3338. + pr_debug("Jack type detected:%d", jack_type);
  3339. + gpio->debounce_time = 25; /* for push button and jack out */
  3340. + break;
  3341. + case RT5671_J_OUT_EVENT:
  3342. + pr_debug("Jack remove intr");
  3343. + gpio->debounce_time = 150; /* for jack in */
  3344. + jack_type = 0;
  3345. + break;
  3346. + case RT5671_BR_EVENT:
  3347. + pr_debug("BR event received");
  3348. + jack_type = SND_JACK_HEADSET;
  3349. + break;
  3350. + case RT5671_BTN_EVENT:
  3351. + pr_debug("BP event received");
  3352. + jack_type = SND_JACK_HEADSET;
  3353. + pr_debug("button code 0x%04x\n", data);
  3354. + switch (data) {
  3355. + case 0x2000: /* up */
  3356. + jack_type |= SND_JACK_BTN_1;
  3357. + break;
  3358. + case 0x0400: /* center */
  3359. + jack_type |= SND_JACK_BTN_0;
  3360. + break;
  3361. + case 0x0080: /* down */
  3362. + jack_type |= SND_JACK_BTN_2;
  3363. + break;
  3364. + default:
  3365. + dev_err(codec->dev, "Unexpected button code 0x%04x\n", data);
  3366. + break;
  3367. + }
  3368. + break;
  3369. + case RT5671_UN_EVENT:
  3370. + pr_debug("Reported invalid/RT5671_UN_EVENT");
  3371. + break;
  3372. + default:
  3373. + dev_err(codec->dev, "Error: Invalid event");
  3374. + }
  3375. + return jack_type;
  3376. +}
  3377. +
  3378. +static const DECLARE_TLV_DB_SCALE(drc_limiter_tlv, 0, 375, 0);
  3379. +static const DECLARE_TLV_DB_SCALE(drc_pre_tlv, 0, 750, 0);
  3380. +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
  3381. +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
  3382. +static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
  3383. +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
  3384. +static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  3385. +
  3386. +/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  3387. +static unsigned int bst_tlv[] = {
  3388. + TLV_DB_RANGE_HEAD(7),
  3389. + 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  3390. + 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  3391. + 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  3392. + 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  3393. + 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  3394. + 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  3395. + 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
  3396. +};
  3397. +
  3398. +/* Interface data select */
  3399. +static const char * const rt5671_data_select[] = {
  3400. + "Normal", "Swap", "left copy to right", "right copy to left"
  3401. +};
  3402. +
  3403. +static const SOC_ENUM_SINGLE_DECL(rt5671_if2_dac_enum, RT5671_DIG_INF1_DATA,
  3404. + RT5671_IF2_DAC_SEL_SFT, rt5671_data_select);
  3405. +
  3406. +static const SOC_ENUM_SINGLE_DECL(rt5671_if2_adc_enum, RT5671_DIG_INF1_DATA,
  3407. + RT5671_IF2_ADC_SEL_SFT, rt5671_data_select);
  3408. +
  3409. +static const SOC_ENUM_SINGLE_DECL(rt5671_if3_dac_enum, RT5671_DIG_INF1_DATA,
  3410. + RT5671_IF3_DAC_SEL_SFT, rt5671_data_select);
  3411. +
  3412. +static const SOC_ENUM_SINGLE_DECL(rt5671_if3_adc_enum, RT5671_DIG_INF1_DATA,
  3413. + RT5671_IF3_ADC_SEL_SFT, rt5671_data_select);
  3414. +
  3415. +static const char * const rt5671_asrc_clk_source[] = {
  3416. + "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track",
  3417. + "clk_i2s3_track", "clk_i2s4_track", "clk_sys2", "clk_sys3",
  3418. + "clk_sys4", "clk_sys5"
  3419. +};
  3420. +
  3421. +static const SOC_ENUM_SINGLE_DECL(rt5671_da_sto_asrc_enum, RT5671_ASRC_2,
  3422. + 12, rt5671_asrc_clk_source);
  3423. +
  3424. +static const SOC_ENUM_SINGLE_DECL(rt5671_da_monol_asrc_enum, RT5671_ASRC_2,
  3425. + 8, rt5671_asrc_clk_source);
  3426. +
  3427. +static const SOC_ENUM_SINGLE_DECL(rt5671_da_monor_asrc_enum, RT5671_ASRC_2,
  3428. + 4, rt5671_asrc_clk_source);
  3429. +
  3430. +static const SOC_ENUM_SINGLE_DECL(rt5671_ad_sto1_asrc_enum, RT5671_ASRC_2,
  3431. + 0, rt5671_asrc_clk_source);
  3432. +
  3433. +static const SOC_ENUM_SINGLE_DECL(rt5671_up_filter_asrc_enum, RT5671_ASRC_3,
  3434. + 12, rt5671_asrc_clk_source);
  3435. +
  3436. +static const SOC_ENUM_SINGLE_DECL(rt5671_down_filter_asrc_enum, RT5671_ASRC_3,
  3437. + 8, rt5671_asrc_clk_source);
  3438. +
  3439. +static const SOC_ENUM_SINGLE_DECL(rt5671_ad_monol_asrc_enum, RT5671_ASRC_3,
  3440. + 4, rt5671_asrc_clk_source);
  3441. +
  3442. +static const SOC_ENUM_SINGLE_DECL(rt5671_ad_monor_asrc_enum, RT5671_ASRC_3,
  3443. + 0, rt5671_asrc_clk_source);
  3444. +
  3445. +static const SOC_ENUM_SINGLE_DECL(rt5671_ad_sto2_asrc_enum, RT5671_ASRC_5,
  3446. + 12, rt5671_asrc_clk_source);
  3447. +
  3448. +static const SOC_ENUM_SINGLE_DECL(rt5671_dsp_asrc_enum, RT5671_DSP_CLK,
  3449. + 0, rt5671_asrc_clk_source);
  3450. +
  3451. +static int rt5671_ad_sto1_asrc_put(struct snd_kcontrol *kcontrol,
  3452. + struct snd_ctl_elem_value *ucontrol)
  3453. +{
  3454. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3455. +
  3456. + switch (ucontrol->value.integer.value[0]) {
  3457. + case 1 ... 4: /*enable*/
  3458. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_ADC_S1F)
  3459. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x8, 0x8);
  3460. + break;
  3461. + default: /*disable*/
  3462. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x8, 0);
  3463. + break;
  3464. + }
  3465. +
  3466. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3467. +}
  3468. +
  3469. +static int rt5671_ad_sto2_asrc_put(struct snd_kcontrol *kcontrol,
  3470. + struct snd_ctl_elem_value *ucontrol)
  3471. +{
  3472. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3473. +
  3474. + switch (ucontrol->value.integer.value[0]) {
  3475. + case 1 ... 4: /*enable*/
  3476. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_ADC_S2F)
  3477. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x4, 0x4);
  3478. + break;
  3479. + default: /*disable*/
  3480. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x4, 0);
  3481. + break;
  3482. + }
  3483. +
  3484. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3485. +}
  3486. +
  3487. +static int rt5671_ad_monol_asrc_put(struct snd_kcontrol *kcontrol,
  3488. + struct snd_ctl_elem_value *ucontrol)
  3489. +{
  3490. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3491. +
  3492. + switch (ucontrol->value.integer.value[0]) {
  3493. + case 1 ... 4: /*enable*/
  3494. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_ADC_MF_L)
  3495. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x2, 0x2);
  3496. + break;
  3497. + default: /*disable*/
  3498. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x2, 0);
  3499. + break;
  3500. + }
  3501. +
  3502. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3503. +}
  3504. +
  3505. +static int rt5671_ad_monor_asrc_put(struct snd_kcontrol *kcontrol,
  3506. + struct snd_ctl_elem_value *ucontrol)
  3507. +{
  3508. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3509. +
  3510. + switch (ucontrol->value.integer.value[0]) {
  3511. + case 1 ... 4: /*enable*/
  3512. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_ADC_MF_R)
  3513. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x1, 0x1);
  3514. + break;
  3515. + default: /*disable*/
  3516. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x1, 0);
  3517. + break;
  3518. + }
  3519. +
  3520. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3521. +}
  3522. +
  3523. +static int rt5671_da_monol_asrc_put(struct snd_kcontrol *kcontrol,
  3524. + struct snd_ctl_elem_value *ucontrol)
  3525. +{
  3526. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3527. +
  3528. + switch (ucontrol->value.integer.value[0]) {
  3529. + case 1 ... 4: /*enable*/
  3530. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_DAC_MF_L)
  3531. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x200, 0x200);
  3532. + break;
  3533. + default: /*disable*/
  3534. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x200, 0);
  3535. + break;
  3536. + }
  3537. +
  3538. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3539. +}
  3540. +
  3541. +static int rt5671_da_monor_asrc_put(struct snd_kcontrol *kcontrol,
  3542. + struct snd_ctl_elem_value *ucontrol)
  3543. +{
  3544. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3545. +
  3546. + switch (ucontrol->value.integer.value[0]) {
  3547. + case 1 ... 4: /*enable*/
  3548. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_DAC_MF_R)
  3549. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x100, 0x100);
  3550. + break;
  3551. + default: /*disable*/
  3552. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x100, 0);
  3553. + break;
  3554. + }
  3555. +
  3556. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3557. +}
  3558. +
  3559. +static int rt5671_da_sto_asrc_put(struct snd_kcontrol *kcontrol,
  3560. + struct snd_ctl_elem_value *ucontrol)
  3561. +{
  3562. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3563. +
  3564. + switch (ucontrol->value.integer.value[0]) {
  3565. + case 1 ... 4: /*enable*/
  3566. + if (snd_soc_read(codec, RT5671_PWR_DIG2) & RT5671_PWR_DAC_S1F)
  3567. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x400, 0x400);
  3568. + break;
  3569. + default: /*disable*/
  3570. + snd_soc_update_bits(codec, RT5671_ASRC_1, 0x400, 0);
  3571. + break;
  3572. + }
  3573. +
  3574. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  3575. +}
  3576. +
  3577. +static const char *rt5671_push_btn_mode[] = {
  3578. + "Disable", "read"
  3579. +};
  3580. +
  3581. +static const SOC_ENUM_SINGLE_DECL(rt5671_push_btn_enum, 0, 0, rt5671_push_btn_mode);
  3582. +
  3583. +static int rt5671_push_btn_get(struct snd_kcontrol *kcontrol,
  3584. + struct snd_ctl_elem_value *ucontrol)
  3585. +{
  3586. + ucontrol->value.integer.value[0] = 0;
  3587. +
  3588. + return 0;
  3589. +}
  3590. +
  3591. +static int rt5671_push_btn_put(struct snd_kcontrol *kcontrol,
  3592. + struct snd_ctl_elem_value *ucontrol)
  3593. +{
  3594. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3595. +
  3596. + printk(KERN_INFO "ret=0x%x\n", rt5671_button_detect(codec));
  3597. +
  3598. + return 0;
  3599. +}
  3600. +
  3601. +static const char *rt5671_jack_type_mode[] = {
  3602. + "Disable", "read"
  3603. +};
  3604. +
  3605. +static const SOC_ENUM_SINGLE_DECL(rt5671_jack_type_enum, 0, 0, rt5671_jack_type_mode);
  3606. +
  3607. +static int rt5671_jack_type_get(struct snd_kcontrol *kcontrol,
  3608. + struct snd_ctl_elem_value *ucontrol)
  3609. +{
  3610. + ucontrol->value.integer.value[0] = 0;
  3611. +
  3612. + return 0;
  3613. +}
  3614. +
  3615. +static int rt5671_jack_type_put(struct snd_kcontrol *kcontrol,
  3616. + struct snd_ctl_elem_value *ucontrol)
  3617. +{
  3618. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3619. + int jack_insert = ucontrol->value.integer.value[0];
  3620. +
  3621. + printk(KERN_INFO "ret=0x%x\n", rt5671_headset_detect(codec, jack_insert));
  3622. +
  3623. + return 0;
  3624. +}
  3625. +
  3626. +static const char *rt5671_drc_mode[] = {
  3627. + "Disable", "Enable"
  3628. +};
  3629. +
  3630. +static const SOC_ENUM_SINGLE_DECL(rt5671_drc_enum, 0, 0, rt5671_drc_mode);
  3631. +
  3632. +static int rt5671_drc_get(struct snd_kcontrol *kcontrol,
  3633. + struct snd_ctl_elem_value *ucontrol)
  3634. +{
  3635. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3636. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3637. +
  3638. + ucontrol->value.integer.value[0] = rt5671->drc_mode;
  3639. +
  3640. + return 0;
  3641. +}
  3642. +
  3643. +static int rt5671_drc_put(struct snd_kcontrol *kcontrol,
  3644. + struct snd_ctl_elem_value *ucontrol)
  3645. +{
  3646. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  3647. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3648. +
  3649. + rt5671->drc_mode = ucontrol->value.integer.value[0];
  3650. +
  3651. + return 0;
  3652. +}
  3653. +
  3654. +static const struct snd_kcontrol_new rt5671_snd_controls[] = {
  3655. + /* Headphone Output Volume */
  3656. + SOC_DOUBLE_TLV("HP Playback Volume", RT5671_HP_VOL,
  3657. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT, 39, 1, out_vol_tlv),
  3658. + /* OUTPUT Control */
  3659. + SOC_SINGLE("OUT Channel Switch", RT5671_LOUT1,
  3660. + RT5671_VOL_L_SFT, 1, 0),
  3661. + SOC_DOUBLE_TLV("OUT Playback Volume", RT5671_LOUT1,
  3662. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT, 39, 1, out_vol_tlv),
  3663. + /* DAC Digital Volume */
  3664. + SOC_DOUBLE("DAC2 Playback Switch", RT5671_DAC_CTRL,
  3665. + RT5671_M_DAC_L2_VOL_SFT, RT5671_M_DAC_R2_VOL_SFT, 1, 1),
  3666. + SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5671_DAC1_DIG_VOL,
  3667. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT,
  3668. + 175, 0, dac_vol_tlv),
  3669. + SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5671_DAC2_DIG_VOL,
  3670. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT,
  3671. + 175, 0, dac_vol_tlv),
  3672. + /* DRC Gain */
  3673. + SOC_SINGLE_TLV("DRC Pre Boost", RT5671_ALC_DRC_CTRL2,
  3674. + 6, 0x27, 0, drc_pre_tlv),
  3675. + SOC_SINGLE_TLV("DRC Limiter Th", RT5671_ALC_CTRL_4,
  3676. + 0, 0x3f, 0, drc_limiter_tlv),
  3677. + /* IN1/IN2 Control */
  3678. + SOC_SINGLE_TLV("IN1 Boost", RT5671_CJ_CTRL1,
  3679. + RT5671_CBJ_BST1_SFT, 8, 0, bst_tlv),
  3680. + SOC_SINGLE_TLV("IN2 Boost", RT5671_IN2,
  3681. + RT5671_BST_SFT2, 8, 0, bst_tlv),
  3682. + SOC_SINGLE_TLV("IN3 Boost", RT5671_IN3_IN4,
  3683. + RT5671_BST_SFT1, 8, 0, bst_tlv),
  3684. + SOC_SINGLE_TLV("IN4 Boost", RT5671_IN3_IN4,
  3685. + RT5671_BST_SFT2, 8, 0, bst_tlv),
  3686. + /* INL/INR Volume Control */
  3687. + SOC_DOUBLE_TLV("IN Capture Volume", RT5671_INL1_INR1_VOL,
  3688. + RT5671_INL_VOL_SFT, RT5671_INR_VOL_SFT,
  3689. + 31, 1, in_vol_tlv),
  3690. + /* ADC Digital Volume Control */
  3691. + SOC_DOUBLE_TLV("ADC Capture Volume", RT5671_STO1_ADC_DIG_VOL,
  3692. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT,
  3693. + 127, 0, adc_vol_tlv),
  3694. +
  3695. + SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5671_MONO_ADC_DIG_VOL,
  3696. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT,
  3697. + 127, 0, adc_vol_tlv),
  3698. +
  3699. + SOC_DOUBLE_TLV("TxDP Capture Volume", RT5671_DSP_PATH2,
  3700. + RT5671_L_VOL_SFT, RT5671_R_VOL_SFT,
  3701. + 127, 0, adc_vol_tlv),
  3702. +
  3703. + /* ADC Boost Volume Control */
  3704. + SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5671_ADC_BST_VOL1,
  3705. + RT5671_STO1_ADC_L_BST_SFT, RT5671_STO1_ADC_R_BST_SFT,
  3706. + 3, 0, adc_bst_tlv),
  3707. +
  3708. + SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5671_ADC_BST_VOL1,
  3709. + RT5671_STO2_ADC_L_BST_SFT, RT5671_STO2_ADC_R_BST_SFT,
  3710. + 3, 0, adc_bst_tlv),
  3711. +
  3712. + SOC_ENUM("ADC IF2 Data Switch", rt5671_if2_adc_enum),
  3713. + SOC_ENUM("DAC IF2 Data Switch", rt5671_if2_dac_enum),
  3714. + SOC_ENUM("ADC IF3 Data Switch", rt5671_if3_adc_enum),
  3715. + SOC_ENUM("DAC IF3 Data Switch", rt5671_if3_dac_enum),
  3716. +
  3717. + SOC_ENUM_EXT("DA STO ASRC Switch", rt5671_da_sto_asrc_enum,
  3718. + snd_soc_get_enum_double, rt5671_da_sto_asrc_put),
  3719. + SOC_ENUM_EXT("DA MONOL ASRC Switch", rt5671_da_monol_asrc_enum,
  3720. + snd_soc_get_enum_double, rt5671_da_monol_asrc_put),
  3721. + SOC_ENUM_EXT("DA MONOR ASRC Switch", rt5671_da_monor_asrc_enum,
  3722. + snd_soc_get_enum_double, rt5671_da_monor_asrc_put),
  3723. + SOC_ENUM_EXT("AD STO1 ASRC Switch", rt5671_ad_sto1_asrc_enum,
  3724. + snd_soc_get_enum_double, rt5671_ad_sto1_asrc_put),
  3725. + SOC_ENUM_EXT("AD MONOL ASRC Switch", rt5671_ad_monol_asrc_enum,
  3726. + snd_soc_get_enum_double, rt5671_ad_monol_asrc_put),
  3727. + SOC_ENUM_EXT("AD MONOR ASRC Switch", rt5671_ad_monor_asrc_enum,
  3728. + snd_soc_get_enum_double, rt5671_ad_monor_asrc_put),
  3729. + SOC_ENUM("UP ASRC Switch", rt5671_up_filter_asrc_enum),
  3730. + SOC_ENUM("DOWN ASRC Switch", rt5671_down_filter_asrc_enum),
  3731. + SOC_ENUM_EXT("AD STO2 ASRC Switch", rt5671_ad_sto2_asrc_enum,
  3732. + snd_soc_get_enum_double, rt5671_ad_sto2_asrc_put),
  3733. + SOC_ENUM("DSP ASRC Switch", rt5671_dsp_asrc_enum),
  3734. +
  3735. + SOC_ENUM_EXT("DRC Switch", rt5671_drc_enum,
  3736. + rt5671_drc_get, rt5671_drc_put),
  3737. +
  3738. + SOC_ENUM_EXT("push button", rt5671_push_btn_enum,
  3739. + rt5671_push_btn_get, rt5671_push_btn_put),
  3740. + SOC_ENUM_EXT("jack type", rt5671_jack_type_enum,
  3741. + rt5671_jack_type_get, rt5671_jack_type_put),
  3742. +};
  3743. +
  3744. +/**
  3745. + * set_dmic_clk - Set parameter of dmic.
  3746. + *
  3747. + * @w: DAPM widget.
  3748. + * @kcontrol: The kcontrol of this widget.
  3749. + * @event: Event id.
  3750. + *
  3751. + * Choose dmic clock between 1MHz and 3MHz.
  3752. + * It is better for clock to approximate 3MHz.
  3753. + */
  3754. +static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  3755. + struct snd_kcontrol *kcontrol, int event)
  3756. +{
  3757. + struct snd_soc_codec *codec = w->codec;
  3758. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3759. + int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i;
  3760. + int rate, red, bound, temp;
  3761. +
  3762. + rate = rt5671->lrck[rt5671->aif_pu] << 8;
  3763. + red = 2000000 * 12;
  3764. + for (i = 0; i < ARRAY_SIZE(div); i++) {
  3765. + bound = div[i] * 2000000;
  3766. + if (rate > bound)
  3767. + continue;
  3768. + temp = bound - rate;
  3769. + if (temp < red) {
  3770. + red = temp;
  3771. + idx = i;
  3772. + }
  3773. + }
  3774. +
  3775. + if (idx < 0)
  3776. + dev_err(codec->dev, "Failed to set DMIC clock\n");
  3777. + else
  3778. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  3779. + RT5671_DMIC_CLK_MASK, idx << RT5671_DMIC_CLK_SFT);
  3780. + return idx;
  3781. +}
  3782. +
  3783. +static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
  3784. + struct snd_soc_dapm_widget *sink)
  3785. +{
  3786. + struct snd_soc_codec *codec = source->codec;
  3787. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  3788. +
  3789. + return rt5671->sysclk_src == RT5671_SCLK_S_PLL1;
  3790. +}
  3791. +
  3792. +static int is_using_asrc(struct snd_soc_codec *codec,
  3793. + unsigned int reg, unsigned int shift)
  3794. +{
  3795. + unsigned int val;
  3796. +
  3797. + val = (snd_soc_read(codec, reg) >> shift) & 0xf;
  3798. + pr_debug("%s: val = 0x%x\n", __func__, val);
  3799. + switch (val) {
  3800. + case 1:
  3801. + case 2:
  3802. + case 3:
  3803. + case 4:
  3804. + return 1;
  3805. + default:
  3806. + return 0;
  3807. + }
  3808. +}
  3809. +
  3810. +static int check_adc_sto1_asrc_source(struct snd_soc_dapm_widget *source,
  3811. + struct snd_soc_dapm_widget *sink)
  3812. +{
  3813. + struct snd_soc_codec *codec = source->codec;
  3814. +
  3815. + return is_using_asrc(codec, RT5671_ASRC_2, 0);
  3816. +}
  3817. +
  3818. +static int check_adc_sto2_asrc_source(struct snd_soc_dapm_widget *source,
  3819. + struct snd_soc_dapm_widget *sink)
  3820. +{
  3821. + struct snd_soc_codec *codec = source->codec;
  3822. +
  3823. + return is_using_asrc(codec, RT5671_ASRC_5, 12);
  3824. +}
  3825. +
  3826. +static int check_adc_monol_asrc_source(struct snd_soc_dapm_widget *source,
  3827. + struct snd_soc_dapm_widget *sink)
  3828. +{
  3829. + struct snd_soc_codec *codec = source->codec;
  3830. +
  3831. + return is_using_asrc(codec, RT5671_ASRC_3, 4);
  3832. +}
  3833. +
  3834. +static int check_adc_monor_asrc_source(struct snd_soc_dapm_widget *source,
  3835. + struct snd_soc_dapm_widget *sink)
  3836. +{
  3837. + struct snd_soc_codec *codec = source->codec;
  3838. +
  3839. + return is_using_asrc(codec, RT5671_ASRC_3, 0);
  3840. +}
  3841. +
  3842. +static int check_dac_sto_asrc_source(struct snd_soc_dapm_widget *source,
  3843. + struct snd_soc_dapm_widget *sink)
  3844. +{
  3845. + struct snd_soc_codec *codec = source->codec;
  3846. +
  3847. + return is_using_asrc(codec, RT5671_ASRC_2, 12);
  3848. +}
  3849. +
  3850. +static int check_dac_monol_asrc_source(struct snd_soc_dapm_widget *source,
  3851. + struct snd_soc_dapm_widget *sink)
  3852. +{
  3853. + struct snd_soc_codec *codec = source->codec;
  3854. +
  3855. + return is_using_asrc(codec, RT5671_ASRC_2, 8);
  3856. +}
  3857. +
  3858. +static int check_dac_monor_asrc_source(struct snd_soc_dapm_widget *source,
  3859. + struct snd_soc_dapm_widget *sink)
  3860. +{
  3861. + struct snd_soc_codec *codec = source->codec;
  3862. +
  3863. + return is_using_asrc(codec, RT5671_ASRC_2, 4);
  3864. +}
  3865. +
  3866. +/* Digital Mixer */
  3867. +static const struct snd_kcontrol_new rt5671_sto1_adc_l_mix[] = {
  3868. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_STO1_ADC_MIXER,
  3869. + RT5671_M_ADC_L1_SFT, 1, 1),
  3870. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_STO1_ADC_MIXER,
  3871. + RT5671_M_ADC_L2_SFT, 1, 1),
  3872. +};
  3873. +
  3874. +static const struct snd_kcontrol_new rt5671_sto1_adc_r_mix[] = {
  3875. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_STO1_ADC_MIXER,
  3876. + RT5671_M_ADC_R1_SFT, 1, 1),
  3877. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_STO1_ADC_MIXER,
  3878. + RT5671_M_ADC_R2_SFT, 1, 1),
  3879. +};
  3880. +
  3881. +static const struct snd_kcontrol_new rt5671_sto2_adc_l_mix[] = {
  3882. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_STO2_ADC_MIXER,
  3883. + RT5671_M_ADC_L1_SFT, 1, 1),
  3884. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_STO2_ADC_MIXER,
  3885. + RT5671_M_ADC_L2_SFT, 1, 1),
  3886. +};
  3887. +
  3888. +static const struct snd_kcontrol_new rt5671_sto2_adc_r_mix[] = {
  3889. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_STO2_ADC_MIXER,
  3890. + RT5671_M_ADC_R1_SFT, 1, 1),
  3891. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_STO2_ADC_MIXER,
  3892. + RT5671_M_ADC_R2_SFT, 1, 1),
  3893. +};
  3894. +
  3895. +static const struct snd_kcontrol_new rt5671_mono_adc_l_mix[] = {
  3896. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_MONO_ADC_MIXER,
  3897. + RT5671_M_MONO_ADC_L1_SFT, 1, 1),
  3898. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_MONO_ADC_MIXER,
  3899. + RT5671_M_MONO_ADC_L2_SFT, 1, 1),
  3900. +};
  3901. +
  3902. +static const struct snd_kcontrol_new rt5671_mono_adc_r_mix[] = {
  3903. + SOC_DAPM_SINGLE("ADC1 Switch", RT5671_MONO_ADC_MIXER,
  3904. + RT5671_M_MONO_ADC_R1_SFT, 1, 1),
  3905. + SOC_DAPM_SINGLE("ADC2 Switch", RT5671_MONO_ADC_MIXER,
  3906. + RT5671_M_MONO_ADC_R2_SFT, 1, 1),
  3907. +};
  3908. +
  3909. +static const struct snd_kcontrol_new rt5671_dac_l_mix[] = {
  3910. + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5671_AD_DA_MIXER,
  3911. + RT5671_M_ADCMIX_L_SFT, 1, 1),
  3912. + SOC_DAPM_SINGLE("DAC1 Switch", RT5671_AD_DA_MIXER,
  3913. + RT5671_M_DAC1_L_SFT, 1, 1),
  3914. +};
  3915. +
  3916. +static const struct snd_kcontrol_new rt5671_dac_r_mix[] = {
  3917. + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5671_AD_DA_MIXER,
  3918. + RT5671_M_ADCMIX_R_SFT, 1, 1),
  3919. + SOC_DAPM_SINGLE("DAC1 Switch", RT5671_AD_DA_MIXER,
  3920. + RT5671_M_DAC1_R_SFT, 1, 1),
  3921. +};
  3922. +
  3923. +static const struct snd_kcontrol_new rt5671_sto_dac_l_mix[] = {
  3924. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_STO_DAC_MIXER,
  3925. + RT5671_M_DAC_L1_SFT, 1, 1),
  3926. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_STO_DAC_MIXER,
  3927. + RT5671_M_DAC_L2_SFT, 1, 1),
  3928. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_STO_DAC_MIXER,
  3929. + RT5671_M_DAC_R1_STO_L_SFT, 1, 1),
  3930. + SOC_DAPM_SINGLE("ANC Switch", RT5671_STO_DAC_MIXER,
  3931. + RT5671_M_ANC_DAC_L_SFT, 1, 1),
  3932. +};
  3933. +
  3934. +static const struct snd_kcontrol_new rt5671_sto_dac_r_mix[] = {
  3935. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_STO_DAC_MIXER,
  3936. + RT5671_M_DAC_R1_SFT, 1, 1),
  3937. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_STO_DAC_MIXER,
  3938. + RT5671_M_DAC_R2_SFT, 1, 1),
  3939. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_STO_DAC_MIXER,
  3940. + RT5671_M_DAC_L1_STO_R_SFT, 1, 1),
  3941. + SOC_DAPM_SINGLE("ANC Switch", RT5671_STO_DAC_MIXER,
  3942. + RT5671_M_ANC_DAC_R_SFT, 1, 1),
  3943. +};
  3944. +
  3945. +static const struct snd_kcontrol_new rt5671_mono_dac_l_mix[] = {
  3946. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_MONO_DAC_MIXER,
  3947. + RT5671_M_DAC_L1_MONO_L_SFT, 1, 1),
  3948. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_MONO_DAC_MIXER,
  3949. + RT5671_M_DAC_L2_MONO_L_SFT, 1, 1),
  3950. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_MONO_DAC_MIXER,
  3951. + RT5671_M_DAC_R2_MONO_L_SFT, 1, 1),
  3952. + SOC_DAPM_SINGLE("Sidetone Switch", RT5671_SIDETONE_CTRL,
  3953. + RT5671_M_ST_DACL2_SFT, 1, 1),
  3954. +};
  3955. +
  3956. +static const struct snd_kcontrol_new rt5671_mono_dac_r_mix[] = {
  3957. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_MONO_DAC_MIXER,
  3958. + RT5671_M_DAC_R1_MONO_R_SFT, 1, 1),
  3959. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_MONO_DAC_MIXER,
  3960. + RT5671_M_DAC_R2_MONO_R_SFT, 1, 1),
  3961. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_MONO_DAC_MIXER,
  3962. + RT5671_M_DAC_L2_MONO_R_SFT, 1, 1),
  3963. + SOC_DAPM_SINGLE("Sidetone Switch", RT5671_SIDETONE_CTRL,
  3964. + RT5671_M_ST_DACR2_SFT, 1, 1),
  3965. +};
  3966. +
  3967. +static const struct snd_kcontrol_new rt5671_dig_l_mix[] = {
  3968. + SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5671_DIG_MIXER,
  3969. + RT5671_M_STO_L_DAC_L_SFT, 1, 1),
  3970. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_DIG_MIXER,
  3971. + RT5671_M_DAC_L2_DAC_L_SFT, 1, 1),
  3972. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_DIG_MIXER,
  3973. + RT5671_M_DAC_R2_DAC_L_SFT, 1, 1),
  3974. +};
  3975. +
  3976. +static const struct snd_kcontrol_new rt5671_dig_r_mix[] = {
  3977. + SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5671_DIG_MIXER,
  3978. + RT5671_M_STO_R_DAC_R_SFT, 1, 1),
  3979. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_DIG_MIXER,
  3980. + RT5671_M_DAC_R2_DAC_R_SFT, 1, 1),
  3981. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_DIG_MIXER,
  3982. + RT5671_M_DAC_L2_DAC_R_SFT, 1, 1),
  3983. +};
  3984. +
  3985. +/* Analog Input Mixer */
  3986. +static const struct snd_kcontrol_new rt5671_rec_l_mix[] = {
  3987. + SOC_DAPM_SINGLE("INL Switch", RT5671_REC_L2_MIXER,
  3988. + RT5671_M_IN_L_RM_L_SFT, 1, 1),
  3989. + SOC_DAPM_SINGLE("BST4 Switch", RT5671_REC_L2_MIXER,
  3990. + RT5671_M_BST4_RM_L_SFT, 1, 1),
  3991. + SOC_DAPM_SINGLE("BST3 Switch", RT5671_REC_L2_MIXER,
  3992. + RT5671_M_BST3_RM_L_SFT, 1, 1),
  3993. + SOC_DAPM_SINGLE("BST2 Switch", RT5671_REC_L2_MIXER,
  3994. + RT5671_M_BST2_RM_L_SFT, 1, 1),
  3995. + SOC_DAPM_SINGLE("BST1 Switch", RT5671_REC_L2_MIXER,
  3996. + RT5671_M_BST1_RM_L_SFT, 1, 1),
  3997. +};
  3998. +
  3999. +static const struct snd_kcontrol_new rt5671_rec_r_mix[] = {
  4000. + SOC_DAPM_SINGLE("INR Switch", RT5671_REC_R2_MIXER,
  4001. + RT5671_M_IN_R_RM_R_SFT, 1, 1),
  4002. + SOC_DAPM_SINGLE("BST4 Switch", RT5671_REC_R2_MIXER,
  4003. + RT5671_M_BST4_RM_R_SFT, 1, 1),
  4004. + SOC_DAPM_SINGLE("BST3 Switch", RT5671_REC_R2_MIXER,
  4005. + RT5671_M_BST3_RM_R_SFT, 1, 1),
  4006. + SOC_DAPM_SINGLE("BST2 Switch", RT5671_REC_R2_MIXER,
  4007. + RT5671_M_BST2_RM_R_SFT, 1, 1),
  4008. + SOC_DAPM_SINGLE("BST1 Switch", RT5671_REC_R2_MIXER,
  4009. + RT5671_M_BST1_RM_R_SFT, 1, 1),
  4010. +};
  4011. +
  4012. +static const struct snd_kcontrol_new rt5671_rec_m_mix[] = {
  4013. + SOC_DAPM_SINGLE("BST4 Switch", RT5671_REC_MONO2_MIXER,
  4014. + RT5671_M_BST4_RM_M_SFT, 1, 1),
  4015. + SOC_DAPM_SINGLE("BST3 Switch", RT5671_REC_MONO2_MIXER,
  4016. + RT5671_M_BST3_RM_M_SFT, 1, 1),
  4017. + SOC_DAPM_SINGLE("BST2 Switch", RT5671_REC_MONO2_MIXER,
  4018. + RT5671_M_BST2_RM_M_SFT, 1, 1),
  4019. + SOC_DAPM_SINGLE("BST1 Switch", RT5671_REC_MONO2_MIXER,
  4020. + RT5671_M_BST1_RM_M_SFT, 1, 1),
  4021. +};
  4022. +
  4023. +static const struct snd_kcontrol_new rt5671_out_l_mix[] = {
  4024. + SOC_DAPM_SINGLE("BST2 Switch", RT5671_OUT_L1_MIXER,
  4025. + RT5671_M_BST2_OM_L_SFT, 1, 1),
  4026. + SOC_DAPM_SINGLE("BST1 Switch", RT5671_OUT_L1_MIXER,
  4027. + RT5671_M_BST1_OM_L_SFT, 1, 1),
  4028. + SOC_DAPM_SINGLE("INL Switch", RT5671_OUT_L1_MIXER,
  4029. + RT5671_M_IN_L_OM_L_SFT, 1, 1),
  4030. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_OUT_L1_MIXER,
  4031. + RT5671_M_DAC_L2_OM_L_SFT, 1, 1),
  4032. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_OUT_L1_MIXER,
  4033. + RT5671_M_DAC_L1_OM_L_SFT, 1, 1),
  4034. +};
  4035. +
  4036. +static const struct snd_kcontrol_new rt5671_out_r_mix[] = {
  4037. + SOC_DAPM_SINGLE("BST3 Switch", RT5671_OUT_R1_MIXER,
  4038. + RT5671_M_BST3_OM_R_SFT, 1, 1),
  4039. + SOC_DAPM_SINGLE("BST4 Switch", RT5671_OUT_R1_MIXER,
  4040. + RT5671_M_BST4_OM_R_SFT, 1, 1),
  4041. + SOC_DAPM_SINGLE("INR Switch", RT5671_OUT_R1_MIXER,
  4042. + RT5671_M_IN_R_OM_R_SFT, 1, 1),
  4043. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_OUT_R1_MIXER,
  4044. + RT5671_M_DAC_R2_OM_R_SFT, 1, 1),
  4045. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_OUT_R1_MIXER,
  4046. + RT5671_M_DAC_R1_OM_R_SFT, 1, 1),
  4047. +};
  4048. +
  4049. +static const struct snd_kcontrol_new rt5671_mono_mix[] = {
  4050. + SOC_DAPM_SINGLE("DAC R2 Switch", RT5671_MONO_MIXER,
  4051. + RT5671_M_DAC_R2_MM_SFT, 1, 1),
  4052. + SOC_DAPM_SINGLE("DAC L2 Switch", RT5671_MONO_MIXER,
  4053. + RT5671_M_DAC_L2_MM_SFT, 1, 1),
  4054. + SOC_DAPM_SINGLE("BST4 Switch", RT5671_MONO_MIXER,
  4055. + RT5671_M_BST4_MM_SFT, 1, 1),
  4056. +};
  4057. +
  4058. +static const struct snd_kcontrol_new rt5671_hpo_mix[] = {
  4059. + SOC_DAPM_SINGLE("DAC1 Switch", RT5671_HPO_MIXER,
  4060. + RT5671_M_DAC1_HM_SFT, 1, 1),
  4061. + SOC_DAPM_SINGLE("HPVOL Switch", RT5671_HPO_MIXER,
  4062. + RT5671_M_HPVOL_HM_SFT, 1, 1),
  4063. +};
  4064. +
  4065. +static const struct snd_kcontrol_new rt5671_hpvoll_mix[] = {
  4066. + SOC_DAPM_SINGLE("DAC1 Switch", RT5671_HPO_MIXER,
  4067. + RT5671_M_DACL1_HML_SFT, 1, 1),
  4068. + SOC_DAPM_SINGLE("INL Switch", RT5671_HPO_MIXER,
  4069. + RT5671_M_INL1_HML_SFT, 1, 1),
  4070. +};
  4071. +
  4072. +static const struct snd_kcontrol_new rt5671_hpvolr_mix[] = {
  4073. + SOC_DAPM_SINGLE("DAC1 Switch", RT5671_HPO_MIXER,
  4074. + RT5671_M_DACR1_HMR_SFT, 1, 1),
  4075. + SOC_DAPM_SINGLE("INR Switch", RT5671_HPO_MIXER,
  4076. + RT5671_M_INR1_HMR_SFT, 1, 1),
  4077. +};
  4078. +
  4079. +static const struct snd_kcontrol_new rt5671_lout_mix[] = {
  4080. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_LOUT_MIXER,
  4081. + RT5671_M_DAC_L1_LM_SFT, 1, 1),
  4082. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_LOUT_MIXER,
  4083. + RT5671_M_DAC_R1_LM_SFT, 1, 1),
  4084. + SOC_DAPM_SINGLE("OUTMIX L Switch", RT5671_LOUT_MIXER,
  4085. + RT5671_M_OV_L_LM_SFT, 1, 1),
  4086. + SOC_DAPM_SINGLE("OUTMIX R Switch", RT5671_LOUT_MIXER,
  4087. + RT5671_M_OV_R_LM_SFT, 1, 1),
  4088. +};
  4089. +
  4090. +static const struct snd_kcontrol_new rt5671_monoamp_mix[] = {
  4091. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_MONO_MIXER,
  4092. + RT5671_M_DAC_L1_MA_SFT, 1, 1),
  4093. + SOC_DAPM_SINGLE("MONOVOL Switch", RT5671_MONO_MIXER,
  4094. + RT5671_M_OV_L_MM_SFT, 1, 1),
  4095. +};
  4096. +
  4097. +static const struct snd_kcontrol_new rt5671_hpl_mix[] = {
  4098. + SOC_DAPM_SINGLE("DAC L1 Switch", RT5671_HPO_MIXER,
  4099. + RT5671_M_DACL1_HML_SFT, 1, 1),
  4100. + SOC_DAPM_SINGLE("INL1 Switch", RT5671_HPO_MIXER,
  4101. + RT5671_M_INL1_HML_SFT, 1, 1),
  4102. +};
  4103. +
  4104. +static const struct snd_kcontrol_new rt5671_hpr_mix[] = {
  4105. + SOC_DAPM_SINGLE("DAC R1 Switch", RT5671_HPO_MIXER,
  4106. + RT5671_M_DACR1_HMR_SFT, 1, 1),
  4107. + SOC_DAPM_SINGLE("INR1 Switch", RT5671_HPO_MIXER,
  4108. + RT5671_M_INR1_HMR_SFT, 1, 1),
  4109. +};
  4110. +
  4111. +/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
  4112. +static const char * const const rt5671_dac1_src[] = {
  4113. + "IF1 DAC", "IF2 DAC", "IF3 DAC", "IF4 DAC"
  4114. +};
  4115. +
  4116. +static const SOC_ENUM_SINGLE_DECL(
  4117. + rt5671_dac1l_enum, RT5671_AD_DA_MIXER,
  4118. + RT5671_DAC1_L_SEL_SFT, rt5671_dac1_src);
  4119. +
  4120. +static const struct snd_kcontrol_new rt5671_dac1l_mux =
  4121. + SOC_DAPM_ENUM("DAC1 L source", rt5671_dac1l_enum);
  4122. +
  4123. +static const SOC_ENUM_SINGLE_DECL(
  4124. + rt5671_dac1r_enum, RT5671_AD_DA_MIXER,
  4125. + RT5671_DAC1_R_SEL_SFT, rt5671_dac1_src);
  4126. +
  4127. +static const struct snd_kcontrol_new rt5671_dac1r_mux =
  4128. + SOC_DAPM_ENUM("DAC1 R source", rt5671_dac1r_enum);
  4129. +
  4130. +/* DAC2 L/R source */ /* MX-1B [6:4] [2:0] */
  4131. +static int rt5671_dac12_map_values[] = {
  4132. + 0, 1, 2, 3, 5, 6,
  4133. +};
  4134. +static const char * const const rt5671_dac12_src[] = {
  4135. + "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "VAD_ADC", "IF4 DAC"
  4136. +};
  4137. +
  4138. +static const SOC_VALUE_ENUM_SINGLE_DECL(
  4139. + rt5671_dac2l_enum, RT5671_DAC_CTRL,
  4140. + RT5671_DAC2_L_SEL_SFT, 0x7, rt5671_dac12_src, rt5671_dac12_map_values);
  4141. +
  4142. +static const struct snd_kcontrol_new rt5671_dac_l2_mux =
  4143. + SOC_DAPM_VALUE_ENUM("DAC2 L source", rt5671_dac2l_enum);
  4144. +
  4145. +static const char * const rt5671_dacr2_src[] = {
  4146. + "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
  4147. +};
  4148. +
  4149. +static const SOC_ENUM_SINGLE_DECL(
  4150. + rt5671_dac2r_enum, RT5671_DAC_CTRL,
  4151. + RT5671_DAC2_R_SEL_SFT, rt5671_dacr2_src);
  4152. +
  4153. +static const struct snd_kcontrol_new rt5671_dac_r2_mux =
  4154. + SOC_DAPM_ENUM("DAC2 R source", rt5671_dac2r_enum);
  4155. +
  4156. +/* RxDP source */ /* MX-2D [15:13] */
  4157. +static const char * const rt5671_rxdp_src[] = {
  4158. + "IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
  4159. + "Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
  4160. +};
  4161. +
  4162. +static const SOC_ENUM_SINGLE_DECL(
  4163. + rt5671_rxdp_enum, RT5671_DSP_PATH1,
  4164. + RT5671_RXDP_SEL_SFT, rt5671_rxdp_src);
  4165. +
  4166. +static const struct snd_kcontrol_new rt5671_rxdp_mux =
  4167. + SOC_DAPM_ENUM("RxDP source", rt5671_rxdp_enum);
  4168. +
  4169. +/* MX-2D [1] [0] */
  4170. +static const char * const rt5671_dsp_bypass_src[] = {
  4171. + "DSP", "Bypass"
  4172. +};
  4173. +
  4174. +static const SOC_ENUM_SINGLE_DECL(
  4175. + rt5671_dsp_ul_enum, RT5671_DSP_PATH1,
  4176. + RT5671_DSP_UL_SFT, rt5671_dsp_bypass_src);
  4177. +
  4178. +static const struct snd_kcontrol_new rt5671_dsp_ul_mux =
  4179. + SOC_DAPM_ENUM("DSP UL source", rt5671_dsp_ul_enum);
  4180. +
  4181. +static const SOC_ENUM_SINGLE_DECL(
  4182. + rt5671_dsp_dl_enum, RT5671_DSP_PATH1,
  4183. + RT5671_DSP_DL_SFT, rt5671_dsp_bypass_src);
  4184. +
  4185. +static const struct snd_kcontrol_new rt5671_dsp_dl_mux =
  4186. + SOC_DAPM_ENUM("DSP DL source", rt5671_dsp_dl_enum);
  4187. +
  4188. +
  4189. +/* INL/R source */
  4190. +static const char * const rt5671_inl_src[] = {
  4191. + "IN2P", "MonoP"
  4192. +};
  4193. +
  4194. +static const SOC_ENUM_SINGLE_DECL(
  4195. + rt5671_inl_enum, RT5671_INL1_INR1_VOL,
  4196. + RT5671_INL_SEL_SFT, rt5671_inl_src);
  4197. +
  4198. +static const struct snd_kcontrol_new rt5671_inl_mux =
  4199. + SOC_DAPM_ENUM("INL source", rt5671_inl_enum);
  4200. +
  4201. +static const char * const rt5671_inr_src[] = {
  4202. + "IN2N", "MonoN"
  4203. +};
  4204. +
  4205. +static const SOC_ENUM_SINGLE_DECL(
  4206. + rt5671_inr_enum, RT5671_INL1_INR1_VOL,
  4207. + RT5671_INR_SEL_SFT, rt5671_inr_src);
  4208. +
  4209. +static const struct snd_kcontrol_new rt5671_inr_mux =
  4210. + SOC_DAPM_ENUM("INR source", rt5671_inr_enum);
  4211. +
  4212. +/* Stereo2 ADC source */
  4213. +/* MX-26 [15] */
  4214. +static const char * const rt5671_stereo2_adc_lr_src[] = {
  4215. + "L", "LR"
  4216. +};
  4217. +
  4218. +static const SOC_ENUM_SINGLE_DECL(
  4219. + rt5671_stereo2_adc_lr_enum, RT5671_STO2_ADC_MIXER,
  4220. + RT5671_STO2_ADC_SRC_SFT, rt5671_stereo2_adc_lr_src);
  4221. +
  4222. +static const struct snd_kcontrol_new rt5671_sto2_adc_lr_mux =
  4223. + SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5671_stereo2_adc_lr_enum);
  4224. +
  4225. +/* Stereo1 ADC source */
  4226. +/* MX-27 MX-26 [12] */
  4227. +static const char * const rt5671_stereo_adc1_src[] = {
  4228. + "DAC MIX", "ADC"
  4229. +};
  4230. +
  4231. +static const SOC_ENUM_SINGLE_DECL(
  4232. + rt5671_stereo1_adc1_enum, RT5671_STO1_ADC_MIXER,
  4233. + RT5671_ADC_1_SRC_SFT, rt5671_stereo_adc1_src);
  4234. +
  4235. +static const struct snd_kcontrol_new rt5671_sto_adc1_mux =
  4236. + SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5671_stereo1_adc1_enum);
  4237. +
  4238. +static const SOC_ENUM_SINGLE_DECL(
  4239. + rt5671_stereo2_adc1_enum, RT5671_STO2_ADC_MIXER,
  4240. + RT5671_ADC_1_SRC_SFT, rt5671_stereo_adc1_src);
  4241. +
  4242. +static const struct snd_kcontrol_new rt5671_sto2_adc1_mux =
  4243. + SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5671_stereo2_adc1_enum);
  4244. +
  4245. +/* MX-27 MX-26 [11] */
  4246. +static const char * const rt5671_stereo_adc2_src[] = {
  4247. + "DAC MIX", "DMIC"
  4248. +};
  4249. +
  4250. +static const SOC_ENUM_SINGLE_DECL(
  4251. + rt5671_stereo1_adc2_enum, RT5671_STO1_ADC_MIXER,
  4252. + RT5671_ADC_2_SRC_SFT, rt5671_stereo_adc2_src);
  4253. +
  4254. +static const struct snd_kcontrol_new rt5671_sto_adc2_mux =
  4255. + SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5671_stereo1_adc2_enum);
  4256. +
  4257. +static const SOC_ENUM_SINGLE_DECL(
  4258. + rt5671_stereo2_adc2_enum, RT5671_STO2_ADC_MIXER,
  4259. + RT5671_ADC_2_SRC_SFT, rt5671_stereo_adc2_src);
  4260. +
  4261. +static const struct snd_kcontrol_new rt5671_sto2_adc2_mux =
  4262. + SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5671_stereo2_adc2_enum);
  4263. +
  4264. +/* MX-27 MX26 [10] */
  4265. +static const char * const rt5671_stereo_adc_src[] = {
  4266. + "ADC1L ADC2R", "ADC3"
  4267. +};
  4268. +
  4269. +static const SOC_ENUM_SINGLE_DECL(
  4270. + rt5671_stereo1_adc_enum, RT5671_STO1_ADC_MIXER,
  4271. + RT5671_ADC_SRC_SFT, rt5671_stereo_adc_src);
  4272. +
  4273. +static const struct snd_kcontrol_new rt5671_sto_adc_mux =
  4274. + SOC_DAPM_ENUM("Stereo1 ADC source", rt5671_stereo1_adc_enum);
  4275. +
  4276. +static const SOC_ENUM_SINGLE_DECL(
  4277. + rt5671_stereo2_adc_enum, RT5671_STO2_ADC_MIXER,
  4278. + RT5671_ADC_SRC_SFT, rt5671_stereo_adc_src);
  4279. +
  4280. +static const struct snd_kcontrol_new rt5671_sto2_adc_mux =
  4281. + SOC_DAPM_ENUM("Stereo2 ADC source", rt5671_stereo2_adc_enum);
  4282. +
  4283. +static const char * const rt5671_stereo_adc12_src[] = {
  4284. + "ADC", "Stereo DAC"
  4285. +};
  4286. +
  4287. +static const SOC_ENUM_SINGLE_DECL(
  4288. + rt5671_stereo_adc12_enum, RT5671_DUMMY_CTRL,
  4289. + 10, rt5671_stereo_adc12_src);
  4290. +
  4291. +static const struct snd_kcontrol_new rt5671_sto_adc12_mux =
  4292. + SOC_DAPM_ENUM("ADC 1_2 source", rt5671_stereo_adc12_enum);
  4293. +
  4294. +/* MX-27 MX-26 [9:8] */
  4295. +static const char * const rt5671_stereo_dmic_src[] = {
  4296. + "DMIC1", "DMIC2", "DMIC3"
  4297. +};
  4298. +
  4299. +static const SOC_ENUM_SINGLE_DECL(
  4300. + rt5671_stereo1_dmic_enum, RT5671_STO1_ADC_MIXER,
  4301. + RT5671_DMIC_SRC_SFT, rt5671_stereo_dmic_src);
  4302. +
  4303. +static const struct snd_kcontrol_new rt5671_sto1_dmic_mux =
  4304. + SOC_DAPM_ENUM("Stereo1 DMIC source", rt5671_stereo1_dmic_enum);
  4305. +
  4306. +static const SOC_ENUM_SINGLE_DECL(
  4307. + rt5671_stereo2_dmic_enum, RT5671_STO2_ADC_MIXER,
  4308. + RT5671_DMIC_SRC_SFT, rt5671_stereo_dmic_src);
  4309. +
  4310. +static const struct snd_kcontrol_new rt5671_sto2_dmic_mux =
  4311. + SOC_DAPM_ENUM("Stereo2 DMIC source", rt5671_stereo2_dmic_enum);
  4312. +
  4313. +/* MX-27 [0] */
  4314. +static const char * const rt5671_stereo_dmic3_src[] = {
  4315. + "DMIC3", "PDM ADC"
  4316. +};
  4317. +
  4318. +static const SOC_ENUM_SINGLE_DECL(
  4319. + rt5671_stereo_dmic3_enum, RT5671_STO1_ADC_MIXER,
  4320. + RT5671_DMIC3_SRC_SFT, rt5671_stereo_dmic3_src);
  4321. +
  4322. +static const struct snd_kcontrol_new rt5671_sto_dmic3_mux =
  4323. + SOC_DAPM_ENUM("Stereo DMIC3 source", rt5671_stereo_dmic3_enum);
  4324. +
  4325. +/* Mono ADC source */
  4326. +/* MX-28 [12] */
  4327. +static const char * const rt5671_mono_adc_l1_src[] = {
  4328. + "Mono DAC MIXL", "ADC1 ADC3"
  4329. +};
  4330. +
  4331. +static const SOC_ENUM_SINGLE_DECL(
  4332. + rt5671_mono_adc_l1_enum, RT5671_MONO_ADC_MIXER,
  4333. + RT5671_MONO_ADC_L1_SRC_SFT, rt5671_mono_adc_l1_src);
  4334. +
  4335. +static const struct snd_kcontrol_new rt5671_mono_adc_l1_mux =
  4336. + SOC_DAPM_ENUM("Mono ADC1 left source", rt5671_mono_adc_l1_enum);
  4337. +/* MX-28 [11] */
  4338. +static const char * const rt5671_mono_adc_l2_src[] = {
  4339. + "Mono DAC MIXL", "DMIC"
  4340. +};
  4341. +
  4342. +static const SOC_ENUM_SINGLE_DECL(
  4343. + rt5671_mono_adc_l2_enum, RT5671_MONO_ADC_MIXER,
  4344. + RT5671_MONO_ADC_L2_SRC_SFT, rt5671_mono_adc_l2_src);
  4345. +
  4346. +static const struct snd_kcontrol_new rt5671_mono_adc_l2_mux =
  4347. + SOC_DAPM_ENUM("Mono ADC2 left source", rt5671_mono_adc_l2_enum);
  4348. +
  4349. +/* MX-28 [10] */
  4350. +static const char * const rt5671_mono_adc_l_src[] = {
  4351. + "ADC1", "ADC3"
  4352. +};
  4353. +
  4354. +static const SOC_ENUM_SINGLE_DECL(
  4355. + rt5671_mono_adc_l_enum, RT5671_MONO_ADC_MIXER,
  4356. + RT5671_MONO_ADC_L_SRC_SFT, rt5671_mono_adc_l_src);
  4357. +
  4358. +static const struct snd_kcontrol_new rt5671_mono_adc_l_mux =
  4359. + SOC_DAPM_ENUM("Mono ADC left source", rt5671_mono_adc_l_enum);
  4360. +
  4361. +/* MX-28 [9:8] */
  4362. +static const char * const rt5671_mono_dmic_src[] = {
  4363. + "DMIC1", "DMIC2", "DMIC3"
  4364. +};
  4365. +
  4366. +static const SOC_ENUM_SINGLE_DECL(
  4367. + rt5671_mono_dmic_l_enum, RT5671_MONO_ADC_MIXER,
  4368. + RT5671_MONO_DMIC_L_SRC_SFT, rt5671_mono_dmic_src);
  4369. +
  4370. +static const struct snd_kcontrol_new rt5671_mono_dmic_l_mux =
  4371. + SOC_DAPM_ENUM("Mono DMIC left source", rt5671_mono_dmic_l_enum);
  4372. +/* MX-28 [1:0] */
  4373. +static const SOC_ENUM_SINGLE_DECL(
  4374. + rt5671_mono_dmic_r_enum, RT5671_MONO_ADC_MIXER,
  4375. + RT5671_MONO_DMIC_R_SRC_SFT, rt5671_mono_dmic_src);
  4376. +
  4377. +static const struct snd_kcontrol_new rt5671_mono_dmic_r_mux =
  4378. + SOC_DAPM_ENUM("Mono DMIC Right source", rt5671_mono_dmic_r_enum);
  4379. +/* MX-28 [4] */
  4380. +static const char * const rt5671_mono_adc_r1_src[] = {
  4381. + "Mono DAC MIXR", "ADC2 ADC3"
  4382. +};
  4383. +
  4384. +static const SOC_ENUM_SINGLE_DECL(
  4385. + rt5671_mono_adc_r1_enum, RT5671_MONO_ADC_MIXER,
  4386. + RT5671_MONO_ADC_R1_SRC_SFT, rt5671_mono_adc_r1_src);
  4387. +
  4388. +static const struct snd_kcontrol_new rt5671_mono_adc_r1_mux =
  4389. + SOC_DAPM_ENUM("Mono ADC1 right source", rt5671_mono_adc_r1_enum);
  4390. +/* MX-28 [3] */
  4391. +static const char * const rt5671_mono_adc_r2_src[] = {
  4392. + "Mono DAC MIXR", "DMIC"
  4393. +};
  4394. +
  4395. +static const SOC_ENUM_SINGLE_DECL(
  4396. + rt5671_mono_adc_r2_enum, RT5671_MONO_ADC_MIXER,
  4397. + RT5671_MONO_ADC_R2_SRC_SFT, rt5671_mono_adc_r2_src);
  4398. +
  4399. +static const struct snd_kcontrol_new rt5671_mono_adc_r2_mux =
  4400. + SOC_DAPM_ENUM("Mono ADC2 right source", rt5671_mono_adc_r2_enum);
  4401. +
  4402. +/* MX-28 [2] */
  4403. +static const char * const rt5671_mono_adc_r_src[] = {
  4404. + "ADC2", "ADC3"
  4405. +};
  4406. +
  4407. +static const SOC_ENUM_SINGLE_DECL(
  4408. + rt5671_mono_adc_r_enum, RT5671_MONO_ADC_MIXER,
  4409. + RT5671_MONO_ADC_R_SRC_SFT, rt5671_mono_adc_r_src);
  4410. +
  4411. +static const struct snd_kcontrol_new rt5671_mono_adc_r_mux =
  4412. + SOC_DAPM_ENUM("Mono ADC Right source", rt5671_mono_adc_r_enum);
  4413. +
  4414. +/* MX-2D [3:2] */
  4415. +static const char * const rt5671_txdp_slot_src[] = {
  4416. + "Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
  4417. +};
  4418. +
  4419. +static const SOC_ENUM_SINGLE_DECL(
  4420. + rt5671_txdp_slot_enum, RT5671_DSP_PATH1,
  4421. + RT5671_TXDP_SLOT_SEL_SFT, rt5671_txdp_slot_src);
  4422. +
  4423. +static const struct snd_kcontrol_new rt5671_txdp_slot_mux =
  4424. + SOC_DAPM_ENUM("TxDP Slot source", rt5671_txdp_slot_enum);
  4425. +
  4426. +/* MX-2F [15] */
  4427. +static const char * const rt5671_if1_adc2_in_src[] = {
  4428. + "IF_ADC2", "VAD_ADC"
  4429. +};
  4430. +
  4431. +static const SOC_ENUM_SINGLE_DECL(
  4432. + rt5671_if1_adc2_in_enum, RT5671_DIG_INF1_DATA,
  4433. + RT5671_IF1_ADC2_IN_SFT, rt5671_if1_adc2_in_src);
  4434. +
  4435. +static const struct snd_kcontrol_new rt5671_if1_adc2_in_mux =
  4436. + SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5671_if1_adc2_in_enum);
  4437. +
  4438. +/* MX-77 [9:8] */
  4439. +static const char * const rt5671_if1_adc_in_src[] = {
  4440. + "IF1_ADC1", "IF_ADC3", "IF1_ADC2", "TxDC_DAC"
  4441. +};
  4442. +
  4443. +static const SOC_ENUM_SINGLE_DECL(
  4444. + rt5671_if1_adc_in_enum, RT5671_TDM_CTRL_1, 8, rt5671_if1_adc_in_src);
  4445. +
  4446. +static const struct snd_kcontrol_new rt5671_if1_adc_in_mux =
  4447. + SOC_DAPM_ENUM("IF1 ADC IN source", rt5671_if1_adc_in_enum);
  4448. +
  4449. +/* MX-2F [14:12] */
  4450. +static const char * const rt5671_if2_adc_in_src[] = {
  4451. + "IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
  4452. +};
  4453. +
  4454. +static const SOC_ENUM_SINGLE_DECL(
  4455. + rt5671_if2_adc_in_enum, RT5671_DIG_INF1_DATA,
  4456. + RT5671_IF2_ADC_IN_SFT, rt5671_if2_adc_in_src);
  4457. +
  4458. +static const struct snd_kcontrol_new rt5671_if2_adc_in_mux =
  4459. + SOC_DAPM_ENUM("IF2 ADC IN source", rt5671_if2_adc_in_enum);
  4460. +
  4461. +/* MX-2F [2:0] */
  4462. +static const char * const rt5671_if3_adc_in_src[] = {
  4463. + "IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
  4464. +};
  4465. +
  4466. +static const SOC_ENUM_SINGLE_DECL(
  4467. + rt5671_if3_adc_in_enum, RT5671_DIG_INF1_DATA,
  4468. + RT5671_IF3_ADC_IN_SFT, rt5671_if3_adc_in_src);
  4469. +
  4470. +static const struct snd_kcontrol_new rt5671_if3_adc_in_mux =
  4471. + SOC_DAPM_ENUM("IF3 ADC IN source", rt5671_if3_adc_in_enum);
  4472. +
  4473. +/* MX-30 [5:4] */
  4474. +static const char * const rt5671_if4_adc_in_src[] = {
  4475. + "IF_ADC1", "IF_ADC2", "IF_ADC3"
  4476. +};
  4477. +
  4478. +static const SOC_ENUM_SINGLE_DECL(
  4479. + rt5671_if4_adc_in_enum, RT5671_DIG_INF2_DATA,
  4480. + RT5671_IF4_ADC_IN_SFT, rt5671_if4_adc_in_src);
  4481. +
  4482. +static const struct snd_kcontrol_new rt5671_if4_adc_in_mux =
  4483. + SOC_DAPM_ENUM("IF4 ADC IN source", rt5671_if4_adc_in_enum);
  4484. +
  4485. +/* MX-31 [15] [13] [11] [9] */
  4486. +static const char * const rt5671_pdm_src[] = {
  4487. + "Mono DAC", "Stereo DAC"
  4488. +};
  4489. +
  4490. +static const SOC_ENUM_SINGLE_DECL(
  4491. + rt5671_pdm1_l_enum, RT5671_PDM_OUT_CTRL,
  4492. + RT5671_PDM1_L_SFT, rt5671_pdm_src);
  4493. +
  4494. +static const struct snd_kcontrol_new rt5671_pdm1_l_mux =
  4495. + SOC_DAPM_ENUM("PDM1 L source", rt5671_pdm1_l_enum);
  4496. +
  4497. +static const SOC_ENUM_SINGLE_DECL(
  4498. + rt5671_pdm1_r_enum, RT5671_PDM_OUT_CTRL,
  4499. + RT5671_PDM1_R_SFT, rt5671_pdm_src);
  4500. +
  4501. +static const struct snd_kcontrol_new rt5671_pdm1_r_mux =
  4502. + SOC_DAPM_ENUM("PDM1 R source", rt5671_pdm1_r_enum);
  4503. +
  4504. +static const SOC_ENUM_SINGLE_DECL(
  4505. + rt5671_pdm2_l_enum, RT5671_PDM_OUT_CTRL,
  4506. + RT5671_PDM2_L_SFT, rt5671_pdm_src);
  4507. +
  4508. +static const struct snd_kcontrol_new rt5671_pdm2_l_mux =
  4509. + SOC_DAPM_ENUM("PDM2 L source", rt5671_pdm2_l_enum);
  4510. +
  4511. +static const SOC_ENUM_SINGLE_DECL(
  4512. + rt5671_pdm2_r_enum, RT5671_PDM_OUT_CTRL,
  4513. + RT5671_PDM2_R_SFT, rt5671_pdm_src);
  4514. +
  4515. +static const struct snd_kcontrol_new rt5671_pdm2_r_mux =
  4516. + SOC_DAPM_ENUM("PDM2 R source", rt5671_pdm2_r_enum);
  4517. +
  4518. +/* MX-FA [12] */
  4519. +static const char * const rt5671_if1_adc1_in1_src[] = {
  4520. + "IF_ADC1", "IF1_ADC3"
  4521. +};
  4522. +
  4523. +static const SOC_ENUM_SINGLE_DECL(
  4524. + rt5671_if1_adc1_in1_enum, RT5671_GEN_CTRL1,
  4525. + RT5671_IF1_ADC1_IN1_SFT, rt5671_if1_adc1_in1_src);
  4526. +
  4527. +static const struct snd_kcontrol_new rt5671_if1_adc1_in1_mux =
  4528. + SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5671_if1_adc1_in1_enum);
  4529. +
  4530. +/* MX-FA [11] */
  4531. +static const char * const rt5671_if1_adc1_in2_src[] = {
  4532. + "IF1_ADC1_IN1", "IF1_ADC4"
  4533. +};
  4534. +
  4535. +static const SOC_ENUM_SINGLE_DECL(
  4536. + rt5671_if1_adc1_in2_enum, RT5671_GEN_CTRL1,
  4537. + RT5671_IF1_ADC1_IN2_SFT, rt5671_if1_adc1_in2_src);
  4538. +
  4539. +static const struct snd_kcontrol_new rt5671_if1_adc1_in2_mux =
  4540. + SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5671_if1_adc1_in2_enum);
  4541. +
  4542. +/* MX-FA [10] */
  4543. +static const char * const rt5671_if1_adc2_in1_src[] = {
  4544. + "IF1_ADC2_IN", "IF1_ADC4"
  4545. +};
  4546. +
  4547. +static const SOC_ENUM_SINGLE_DECL(
  4548. + rt5671_if1_adc2_in1_enum, RT5671_GEN_CTRL1,
  4549. + RT5671_IF1_ADC2_IN1_SFT, rt5671_if1_adc2_in1_src);
  4550. +
  4551. +static const struct snd_kcontrol_new rt5671_if1_adc2_in1_mux =
  4552. + SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5671_if1_adc2_in1_enum);
  4553. +
  4554. +/* MX-18 [11:9] */
  4555. +static const char * const rt5671_sidetone_src[] = {
  4556. + "DMIC L1", "DMIC L2", "DMIC L3", "ADC 1", "ADC 2", "ADC 3"
  4557. +};
  4558. +
  4559. +static const SOC_ENUM_SINGLE_DECL(
  4560. + rt5671_sidetone_enum, RT5671_SIDETONE_CTRL,
  4561. + RT5671_ST_SEL_SFT, rt5671_sidetone_src);
  4562. +
  4563. +static const struct snd_kcontrol_new rt5671_sidetone_mux =
  4564. + SOC_DAPM_ENUM("Sidetone source", rt5671_sidetone_enum);
  4565. +
  4566. +/* MX-18 [6] */
  4567. +static const char * const rt5671_anc_src[] = {
  4568. + "SNC", "Sidetone"
  4569. +};
  4570. +
  4571. +static const SOC_ENUM_SINGLE_DECL(
  4572. + rt5671_anc_enum, RT5671_SIDETONE_CTRL,
  4573. + RT5671_ST_EN_SFT, rt5671_anc_src);
  4574. +
  4575. +static const struct snd_kcontrol_new rt5671_anc_mux =
  4576. + SOC_DAPM_ENUM("ANC source", rt5671_anc_enum);
  4577. +
  4578. +/* MX-9D [9:8] */
  4579. +static const char * const rt5671_vad_adc_src[] = {
  4580. + "Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
  4581. +};
  4582. +
  4583. +static const SOC_ENUM_SINGLE_DECL(
  4584. + rt5671_vad_adc_enum, RT5671_VAD_CTRL4,
  4585. + RT5671_VAD_SEL_SFT, rt5671_vad_adc_src);
  4586. +
  4587. +static const struct snd_kcontrol_new rt5671_vad_adc_mux =
  4588. + SOC_DAPM_ENUM("VAD ADC source", rt5671_vad_adc_enum);
  4589. +
  4590. +static int rt5671_adc_clk_event(struct snd_soc_dapm_widget *w,
  4591. + struct snd_kcontrol *kcontrol, int event)
  4592. +{
  4593. + struct snd_soc_codec *codec = w->codec;
  4594. +
  4595. + switch (event) {
  4596. + case SND_SOC_DAPM_POST_PMU:
  4597. + rt5671_index_update_bits(codec,
  4598. + RT5671_CHOP_DAC_ADC, 0x1000, 0x1000);
  4599. + break;
  4600. +
  4601. + case SND_SOC_DAPM_POST_PMD:
  4602. + rt5671_index_update_bits(codec,
  4603. + RT5671_CHOP_DAC_ADC, 0x1000, 0x0000);
  4604. + break;
  4605. +
  4606. + default:
  4607. + return 0;
  4608. + }
  4609. +
  4610. + return 0;
  4611. +}
  4612. +
  4613. +static int rt5671_sto1_adcl_event(struct snd_soc_dapm_widget *w,
  4614. + struct snd_kcontrol *kcontrol, int event)
  4615. +{
  4616. + struct snd_soc_codec *codec = w->codec;
  4617. +
  4618. + switch (event) {
  4619. + case SND_SOC_DAPM_POST_PMU:
  4620. + msleep(50);
  4621. + snd_soc_update_bits(codec, RT5671_STO1_ADC_DIG_VOL,
  4622. + RT5671_L_MUTE, 0);
  4623. + break;
  4624. + case SND_SOC_DAPM_PRE_PMD:
  4625. + snd_soc_update_bits(codec, RT5671_STO1_ADC_DIG_VOL,
  4626. + RT5671_L_MUTE,
  4627. + RT5671_L_MUTE);
  4628. + break;
  4629. +
  4630. + default:
  4631. + return 0;
  4632. + }
  4633. +
  4634. + return 0;
  4635. +}
  4636. +
  4637. +static int rt5671_sto1_adcr_event(struct snd_soc_dapm_widget *w,
  4638. + struct snd_kcontrol *kcontrol, int event)
  4639. +{
  4640. + struct snd_soc_codec *codec = w->codec;
  4641. +
  4642. + switch (event) {
  4643. + case SND_SOC_DAPM_POST_PMU:
  4644. + msleep(50);
  4645. + snd_soc_update_bits(codec, RT5671_STO1_ADC_DIG_VOL,
  4646. + RT5671_R_MUTE, 0);
  4647. + break;
  4648. + case SND_SOC_DAPM_PRE_PMD:
  4649. + snd_soc_update_bits(codec, RT5671_STO1_ADC_DIG_VOL,
  4650. + RT5671_R_MUTE,
  4651. + RT5671_R_MUTE);
  4652. + break;
  4653. +
  4654. + default:
  4655. + return 0;
  4656. + }
  4657. +
  4658. + return 0;
  4659. +}
  4660. +
  4661. +static int rt5671_mono_adcl_event(struct snd_soc_dapm_widget *w,
  4662. + struct snd_kcontrol *kcontrol, int event)
  4663. +{
  4664. + struct snd_soc_codec *codec = w->codec;
  4665. +
  4666. + switch (event) {
  4667. + case SND_SOC_DAPM_POST_PMU:
  4668. + snd_soc_update_bits(codec, RT5671_MONO_ADC_DIG_VOL,
  4669. + RT5671_L_MUTE, 0);
  4670. + break;
  4671. + case SND_SOC_DAPM_PRE_PMD:
  4672. + snd_soc_update_bits(codec, RT5671_MONO_ADC_DIG_VOL,
  4673. + RT5671_L_MUTE,
  4674. + RT5671_L_MUTE);
  4675. + break;
  4676. +
  4677. + default:
  4678. + return 0;
  4679. + }
  4680. +
  4681. + return 0;
  4682. +}
  4683. +
  4684. +static int rt5671_mono_adcr_event(struct snd_soc_dapm_widget *w,
  4685. + struct snd_kcontrol *kcontrol, int event)
  4686. +{
  4687. + struct snd_soc_codec *codec = w->codec;
  4688. +
  4689. + switch (event) {
  4690. + case SND_SOC_DAPM_POST_PMU:
  4691. + snd_soc_update_bits(codec, RT5671_MONO_ADC_DIG_VOL,
  4692. + RT5671_R_MUTE, 0);
  4693. + break;
  4694. + case SND_SOC_DAPM_PRE_PMD:
  4695. + snd_soc_update_bits(codec, RT5671_MONO_ADC_DIG_VOL,
  4696. + RT5671_R_MUTE,
  4697. + RT5671_R_MUTE);
  4698. + break;
  4699. +
  4700. + default:
  4701. + return 0;
  4702. + }
  4703. +
  4704. + return 0;
  4705. +}
  4706. +
  4707. +static void hp_amp_power(struct snd_soc_codec *codec, int on)
  4708. +{
  4709. + if (on) {
  4710. + snd_soc_update_bits(codec, RT5671_CHARGE_PUMP,
  4711. + RT5671_PM_HP_MASK, RT5671_PM_HP_HV);
  4712. + /* headphone amp power on */
  4713. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  4714. + RT5671_PWR_HA | RT5671_PWR_FV1 |
  4715. + RT5671_PWR_FV2, RT5671_PWR_HA |
  4716. + RT5671_PWR_FV1 | RT5671_PWR_FV2);
  4717. + /* depop parameters */
  4718. + snd_soc_write(codec, RT5671_DEPOP_M2, 0x3140); /*bit 6 = 1 for Auto Power Down*/
  4719. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x8009);
  4720. + rt5671_index_write(codec, RT5671_HP_DCC_INT1, 0x9f00);
  4721. + pr_debug("hp_amp_time=%d\n", hp_amp_time);
  4722. + mdelay(hp_amp_time);
  4723. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x8019);
  4724. + } else {
  4725. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x0004);
  4726. + msleep(30);
  4727. + }
  4728. +}
  4729. +
  4730. +static void rt5671_pmu_depop(struct snd_soc_codec *codec)
  4731. +{
  4732. + /* headphone unmute sequence */
  4733. + rt5671_index_write(codec, RT5671_MAMP_INT_REG2, 0xb400);
  4734. + snd_soc_write(codec, RT5671_DEPOP_M3, 0x0772);
  4735. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x805d);
  4736. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x831d);
  4737. + snd_soc_update_bits(codec, RT5671_GEN_CTRL2,
  4738. + 0x0300, 0x0300);
  4739. + snd_soc_update_bits(codec, RT5671_HP_VOL,
  4740. + RT5671_L_MUTE | RT5671_R_MUTE, 0);
  4741. + pr_debug("pmu_depop_time=%d\n", pmu_depop_time);
  4742. + msleep(pmu_depop_time);
  4743. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x8019);
  4744. +}
  4745. +
  4746. +static void rt5671_pmd_depop(struct snd_soc_codec *codec)
  4747. +{
  4748. + /* headphone mute sequence */
  4749. + rt5671_index_write(codec, RT5671_MAMP_INT_REG2, 0xb400);
  4750. + snd_soc_write(codec, RT5671_DEPOP_M3, 0x0772);
  4751. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x803d);
  4752. + mdelay(10);
  4753. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x831d);
  4754. + mdelay(10);
  4755. + snd_soc_update_bits(codec, RT5671_HP_VOL,
  4756. + RT5671_L_MUTE | RT5671_R_MUTE, RT5671_L_MUTE | RT5671_R_MUTE);
  4757. + msleep(20);
  4758. + snd_soc_update_bits(codec, RT5671_GEN_CTRL2, 0x0300, 0x0);
  4759. + snd_soc_write(codec, RT5671_DEPOP_M1, 0x8019);
  4760. + snd_soc_write(codec, RT5671_DEPOP_M3, 0x0707);
  4761. + rt5671_index_write(codec, RT5671_MAMP_INT_REG2, 0xfc00);
  4762. +}
  4763. +
  4764. +static int rt5671_hp_power_event(struct snd_soc_dapm_widget *w,
  4765. + struct snd_kcontrol *kcontrol, int event)
  4766. +{
  4767. + struct snd_soc_codec *codec = w->codec;
  4768. +
  4769. + switch (event) {
  4770. + case SND_SOC_DAPM_POST_PMU:
  4771. + hp_amp_power(codec, 1);
  4772. + break;
  4773. + case SND_SOC_DAPM_PRE_PMD:
  4774. + hp_amp_power(codec, 0);
  4775. + break;
  4776. + default:
  4777. + return 0;
  4778. + }
  4779. +
  4780. + return 0;
  4781. +}
  4782. +
  4783. +static int rt5671_hp_event(struct snd_soc_dapm_widget *w,
  4784. + struct snd_kcontrol *kcontrol, int event)
  4785. +{
  4786. + struct snd_soc_codec *codec = w->codec;
  4787. +
  4788. + switch (event) {
  4789. + case SND_SOC_DAPM_POST_PMU:
  4790. + rt5671_pmu_depop(codec);
  4791. + snd_soc_update_bits(codec, RT5671_ALC_CTRL_1,
  4792. + RT5671_DRC_AGC_MASK, RT5671_DRC_AGC_EN);
  4793. + break;
  4794. +
  4795. + case SND_SOC_DAPM_PRE_PMD:
  4796. + snd_soc_update_bits(codec, RT5671_ALC_CTRL_1,
  4797. + RT5671_DRC_AGC_MASK, RT5671_DRC_AGC_DIS);
  4798. + rt5671_pmd_depop(codec);
  4799. + break;
  4800. +
  4801. + default:
  4802. + return 0;
  4803. + }
  4804. +
  4805. + return 0;
  4806. +}
  4807. +
  4808. +static int rt5671_mono_event(struct snd_soc_dapm_widget *w,
  4809. + struct snd_kcontrol *kcontrol, int event)
  4810. +{
  4811. + struct snd_soc_codec *codec = w->codec;
  4812. +
  4813. + switch (event) {
  4814. + case SND_SOC_DAPM_POST_PMU:
  4815. + snd_soc_update_bits(codec, RT5671_MONO_OUT,
  4816. + RT5671_L_MUTE, 0);
  4817. + break;
  4818. +
  4819. + case SND_SOC_DAPM_PRE_PMD:
  4820. + snd_soc_update_bits(codec, RT5671_MONO_OUT,
  4821. + RT5671_L_MUTE, RT5671_L_MUTE);
  4822. + break;
  4823. +
  4824. + default:
  4825. + return 0;
  4826. + }
  4827. +
  4828. + return 0;
  4829. +}
  4830. +
  4831. +static int rt5671_lout_event(struct snd_soc_dapm_widget *w,
  4832. + struct snd_kcontrol *kcontrol, int event)
  4833. +{
  4834. + struct snd_soc_codec *codec = w->codec;
  4835. +
  4836. + switch (event) {
  4837. + case SND_SOC_DAPM_POST_PMU:
  4838. + snd_soc_update_bits(codec, RT5671_CHARGE_PUMP,
  4839. + RT5671_PM_HP_MASK, RT5671_PM_HP_HV);
  4840. + snd_soc_update_bits(codec, RT5671_LOUT1,
  4841. + RT5671_L_MUTE | RT5671_R_MUTE, 0);
  4842. + break;
  4843. +
  4844. + case SND_SOC_DAPM_PRE_PMD:
  4845. + snd_soc_update_bits(codec, RT5671_LOUT1,
  4846. + RT5671_L_MUTE | RT5671_R_MUTE,
  4847. + RT5671_L_MUTE | RT5671_R_MUTE);
  4848. + break;
  4849. +
  4850. + default:
  4851. + return 0;
  4852. + }
  4853. +
  4854. + return 0;
  4855. +}
  4856. +
  4857. +static int rt5671_set_dmic1_event(struct snd_soc_dapm_widget *w,
  4858. + struct snd_kcontrol *kcontrol, int event)
  4859. +{
  4860. + struct snd_soc_codec *codec = w->codec;
  4861. +
  4862. + switch (event) {
  4863. + case SND_SOC_DAPM_PRE_PMU:
  4864. +#ifdef NVIDIA_DALMORE
  4865. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4866. + RT5671_PWR_BST1 | RT5671_PWR_BST1_P,
  4867. + RT5671_PWR_BST1 | RT5671_PWR_BST1_P);
  4868. + snd_soc_update_bits(codec, RT5671_CJ_CTRL2,
  4869. + RT5671_CBJ_DET_MODE, RT5671_CBJ_DET_MODE);
  4870. +#endif
  4871. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1,
  4872. + RT5671_GP2_PIN_MASK | RT5671_GP6_PIN_MASK |
  4873. + RT5671_I2S2_PIN_MASK,
  4874. + RT5671_GP2_PIN_DMIC1_SCL | RT5671_GP6_PIN_DMIC1_SDA |
  4875. + RT5671_I2S2_PIN_GPIO);
  4876. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  4877. + RT5671_DMIC_1L_LH_MASK | RT5671_DMIC_1R_LH_MASK |
  4878. + RT5671_DMIC_1_DP_MASK,
  4879. + RT5671_DMIC_1L_LH_FALLING | RT5671_DMIC_1R_LH_RISING |
  4880. + RT5671_DMIC_1_DP_GPIO6);
  4881. + break;
  4882. + case SND_SOC_DAPM_POST_PMD:
  4883. +#ifdef NVIDIA_DALMORE
  4884. + snd_soc_update_bits(codec, RT5671_CJ_CTRL2, RT5671_CBJ_DET_MODE,
  4885. + 0);
  4886. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4887. + RT5671_PWR_BST1 | RT5671_PWR_BST1_P, 0);
  4888. +#endif
  4889. + break;
  4890. + default:
  4891. + return 0;
  4892. + }
  4893. +
  4894. + return 0;
  4895. +}
  4896. +
  4897. +static int rt5671_set_dmic2_event(struct snd_soc_dapm_widget *w,
  4898. + struct snd_kcontrol *kcontrol, int event)
  4899. +{
  4900. + struct snd_soc_codec *codec = w->codec;
  4901. +
  4902. + switch (event) {
  4903. + case SND_SOC_DAPM_PRE_PMU:
  4904. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1,
  4905. + RT5671_GP2_PIN_MASK | RT5671_GP4_PIN_MASK,
  4906. + RT5671_GP2_PIN_DMIC1_SCL | RT5671_GP4_PIN_DMIC2_SDA);
  4907. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  4908. + RT5671_DMIC_2L_LH_MASK | RT5671_DMIC_2R_LH_MASK |
  4909. + RT5671_DMIC_2_DP_MASK,
  4910. + RT5671_DMIC_2L_LH_FALLING | RT5671_DMIC_2R_LH_RISING |
  4911. + RT5671_DMIC_2_DP_IN1N);
  4912. + break;
  4913. +
  4914. + case SND_SOC_DAPM_POST_PMD:
  4915. + break;
  4916. +
  4917. + default:
  4918. + return 0;
  4919. + }
  4920. +
  4921. + return 0;
  4922. +}
  4923. +
  4924. +static int rt5671_set_dmic3_event(struct snd_soc_dapm_widget *w,
  4925. + struct snd_kcontrol *kcontrol, int event)
  4926. +{
  4927. + struct snd_soc_codec *codec = w->codec;
  4928. +
  4929. + switch (event) {
  4930. + case SND_SOC_DAPM_PRE_PMU:
  4931. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1,
  4932. + RT5671_GP2_PIN_MASK | RT5671_GP4_PIN_MASK,
  4933. + RT5671_GP2_PIN_DMIC1_SCL | RT5671_GP4_PIN_DMIC2_SDA);
  4934. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  4935. + RT5671_DMIC_2L_LH_MASK | RT5671_DMIC_2R_LH_MASK |
  4936. + RT5671_DMIC_2_DP_MASK,
  4937. + RT5671_DMIC_2L_LH_FALLING | RT5671_DMIC_2R_LH_RISING |
  4938. + RT5671_DMIC_2_DP_IN1N);
  4939. + break;
  4940. +
  4941. + case SND_SOC_DAPM_POST_PMD:
  4942. + break;
  4943. +
  4944. + default:
  4945. + return 0;
  4946. + }
  4947. +
  4948. + return 0;
  4949. +}
  4950. +
  4951. +static int rt5671_bst1_event(struct snd_soc_dapm_widget *w,
  4952. + struct snd_kcontrol *kcontrol, int event)
  4953. +{
  4954. + struct snd_soc_codec *codec = w->codec;
  4955. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  4956. +
  4957. + switch (event) {
  4958. + case SND_SOC_DAPM_POST_PMU:
  4959. + snd_soc_update_bits(codec, RT5671_CHARGE_PUMP,
  4960. + RT5671_OSW_L_MASK | RT5671_OSW_R_MASK,
  4961. + RT5671_OSW_L_DIS | RT5671_OSW_R_DIS);
  4962. +
  4963. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4964. + RT5671_PWR_BST1_P, RT5671_PWR_BST1_P);
  4965. + if (rt5671->combo_jack_en) {
  4966. + snd_soc_update_bits(codec, RT5671_PWR_VOL,
  4967. + RT5671_PWR_MIC_DET, RT5671_PWR_MIC_DET);
  4968. + snd_soc_update_bits(codec, RT5671_GEN_CTRL2, 0x2, 0x0);
  4969. + }
  4970. + break;
  4971. +
  4972. + case SND_SOC_DAPM_PRE_PMD:
  4973. + snd_soc_update_bits(codec, RT5671_GEN_CTRL2, 0x2, 0x2);
  4974. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4975. + RT5671_PWR_BST1_P, 0);
  4976. + break;
  4977. +
  4978. + default:
  4979. + return 0;
  4980. + }
  4981. +
  4982. + return 0;
  4983. +}
  4984. +
  4985. +static int rt5671_bst2_event(struct snd_soc_dapm_widget *w,
  4986. + struct snd_kcontrol *kcontrol, int event)
  4987. +{
  4988. + struct snd_soc_codec *codec = w->codec;
  4989. +
  4990. + switch (event) {
  4991. + case SND_SOC_DAPM_POST_PMU:
  4992. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4993. + RT5671_PWR_BST2_P, RT5671_PWR_BST2_P);
  4994. + break;
  4995. +
  4996. + case SND_SOC_DAPM_PRE_PMD:
  4997. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  4998. + RT5671_PWR_BST2_P, 0);
  4999. + break;
  5000. +
  5001. + default:
  5002. + return 0;
  5003. + }
  5004. +
  5005. + return 0;
  5006. +}
  5007. +
  5008. +static int rt5671_bst3_event(struct snd_soc_dapm_widget *w,
  5009. + struct snd_kcontrol *kcontrol, int event)
  5010. +{
  5011. + struct snd_soc_codec *codec = w->codec;
  5012. +
  5013. + switch (event) {
  5014. + case SND_SOC_DAPM_POST_PMU:
  5015. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  5016. + RT5671_PWR_BST3_P, RT5671_PWR_BST3_P);
  5017. + break;
  5018. +
  5019. + case SND_SOC_DAPM_PRE_PMD:
  5020. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  5021. + RT5671_PWR_BST3_P, 0);
  5022. + break;
  5023. +
  5024. + default:
  5025. + return 0;
  5026. + }
  5027. +
  5028. + return 0;
  5029. +}
  5030. +
  5031. +static int rt5671_bst4_event(struct snd_soc_dapm_widget *w,
  5032. + struct snd_kcontrol *kcontrol, int event)
  5033. +{
  5034. + struct snd_soc_codec *codec = w->codec;
  5035. +
  5036. + switch (event) {
  5037. + case SND_SOC_DAPM_POST_PMU:
  5038. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  5039. + RT5671_PWR_BST4_P, RT5671_PWR_BST4_P);
  5040. + break;
  5041. +
  5042. + case SND_SOC_DAPM_PRE_PMD:
  5043. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  5044. + RT5671_PWR_BST4_P, 0);
  5045. + break;
  5046. +
  5047. + default:
  5048. + return 0;
  5049. + }
  5050. +
  5051. + return 0;
  5052. +}
  5053. +
  5054. +static int rt5671_pdm1_l_event(struct snd_soc_dapm_widget *w,
  5055. + struct snd_kcontrol *kcontrol, int event)
  5056. +{
  5057. + struct snd_soc_codec *codec = w->codec;
  5058. +
  5059. + switch (event) {
  5060. + case SND_SOC_DAPM_POST_PMU:
  5061. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5062. + RT5671_M_PDM1_L, 0);
  5063. + break;
  5064. +
  5065. + case SND_SOC_DAPM_PRE_PMD:
  5066. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5067. + RT5671_M_PDM1_L, RT5671_M_PDM1_L);
  5068. + break;
  5069. +
  5070. + default:
  5071. + return 0;
  5072. + }
  5073. +
  5074. + return 0;
  5075. +}
  5076. +
  5077. +static int rt5671_pdm1_r_event(struct snd_soc_dapm_widget *w,
  5078. + struct snd_kcontrol *kcontrol, int event)
  5079. +{
  5080. + struct snd_soc_codec *codec = w->codec;
  5081. +
  5082. + switch (event) {
  5083. + case SND_SOC_DAPM_POST_PMU:
  5084. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5085. + RT5671_M_PDM1_R, 0);
  5086. + break;
  5087. +
  5088. + case SND_SOC_DAPM_PRE_PMD:
  5089. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5090. + RT5671_M_PDM1_R, RT5671_M_PDM1_R);
  5091. + break;
  5092. +
  5093. + default:
  5094. + return 0;
  5095. + }
  5096. +
  5097. + return 0;
  5098. +}
  5099. +
  5100. +static int rt5671_pdm2_l_event(struct snd_soc_dapm_widget *w,
  5101. + struct snd_kcontrol *kcontrol, int event)
  5102. +{
  5103. + struct snd_soc_codec *codec = w->codec;
  5104. +
  5105. + switch (event) {
  5106. + case SND_SOC_DAPM_POST_PMU:
  5107. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5108. + RT5671_M_PDM2_L, 0);
  5109. + break;
  5110. +
  5111. + case SND_SOC_DAPM_PRE_PMD:
  5112. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5113. + RT5671_M_PDM2_L, RT5671_M_PDM2_L);
  5114. + break;
  5115. +
  5116. + default:
  5117. + return 0;
  5118. + }
  5119. +
  5120. + return 0;
  5121. +}
  5122. +
  5123. +static int rt5671_pdm2_r_event(struct snd_soc_dapm_widget *w,
  5124. + struct snd_kcontrol *kcontrol, int event)
  5125. +{
  5126. + struct snd_soc_codec *codec = w->codec;
  5127. +
  5128. + switch (event) {
  5129. + case SND_SOC_DAPM_POST_PMU:
  5130. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5131. + RT5671_M_PDM2_R, 0);
  5132. + break;
  5133. +
  5134. + case SND_SOC_DAPM_PRE_PMD:
  5135. + snd_soc_update_bits(codec, RT5671_PDM_OUT_CTRL,
  5136. + RT5671_M_PDM2_R, RT5671_M_PDM2_R);
  5137. + break;
  5138. +
  5139. + default:
  5140. + return 0;
  5141. + }
  5142. +
  5143. + return 0;
  5144. +}
  5145. +
  5146. +static int rt5671_sto_adc12_event(struct snd_soc_dapm_widget *w,
  5147. + struct snd_kcontrol *kcontrol, int event)
  5148. +{
  5149. + struct snd_soc_codec *codec = w->codec;
  5150. + unsigned int val;
  5151. +
  5152. + switch (event) {
  5153. + case SND_SOC_DAPM_POST_REG:
  5154. + val = snd_soc_read(codec, RT5671_DUMMY_CTRL) & 0x0400;
  5155. + rt5671_index_update_bits(codec, 0x3a, 0x0400, val);
  5156. + break;
  5157. +
  5158. + default:
  5159. + return 0;
  5160. + }
  5161. +
  5162. + return 0;
  5163. +}
  5164. +
  5165. +static int rt5671_drc_event(struct snd_soc_dapm_widget *w,
  5166. + struct snd_kcontrol *kcontrol, int event)
  5167. +{
  5168. + struct snd_soc_codec *codec = w->codec;
  5169. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  5170. +
  5171. + switch (event) {
  5172. + case SND_SOC_DAPM_POST_PMU:
  5173. + if (rt5671->drc_mode)
  5174. + snd_soc_write(codec, RT5671_ALC_CTRL_1, 0xe206);
  5175. + break;
  5176. +
  5177. + case SND_SOC_DAPM_PRE_PMD:
  5178. + snd_soc_write(codec, RT5671_ALC_CTRL_1, 0x2206); /*MX-B4*/
  5179. + break;
  5180. +
  5181. + default:
  5182. + return 0;
  5183. + }
  5184. +
  5185. + return 0;
  5186. +}
  5187. +
  5188. +static const struct snd_soc_dapm_widget rt5671_dapm_widgets[] = {
  5189. + SND_SOC_DAPM_SUPPLY("PLL1", RT5671_PWR_ANLG2,
  5190. + RT5671_PWR_PLL_BIT, 0, NULL, 0),
  5191. + SND_SOC_DAPM_SUPPLY("I2S DSP", RT5671_PWR_DIG2,
  5192. + RT5671_PWR_I2S_DSP_BIT, 0, NULL, 0),
  5193. + SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5671_PWR_VOL,
  5194. + RT5671_PWR_MIC_DET_BIT, 0, NULL, 0),
  5195. +
  5196. + /* ASRC */
  5197. + SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5671_ASRC_1,
  5198. + 11, 0, NULL, 0),
  5199. + SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5671_ASRC_1,
  5200. + 12, 0, NULL, 0),
  5201. + SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5671_ASRC_1,
  5202. + 13, 0, NULL, 0),
  5203. + SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5671_ASRC_1,
  5204. + 14, 0, NULL, 0),
  5205. + SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5671_ASRC_1,
  5206. + 10, 0, NULL, 0),
  5207. + SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5671_ASRC_1,
  5208. + 9, 0, NULL, 0),
  5209. + SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5671_ASRC_1,
  5210. + 8, 0, NULL, 0),
  5211. + SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5671_ASRC_1,
  5212. + 3, 0, NULL, 0),
  5213. + SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5671_ASRC_1,
  5214. + 2, 0, NULL, 0),
  5215. + SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5671_ASRC_1,
  5216. + 1, 0, NULL, 0),
  5217. + SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5671_ASRC_1,
  5218. + 0, 0, NULL, 0),
  5219. +
  5220. + /* Input Side */
  5221. + /* micbias */
  5222. + SND_SOC_DAPM_MICBIAS("micbias1", RT5671_PWR_ANLG2,
  5223. + RT5671_PWR_MB1_BIT, 0),
  5224. + SND_SOC_DAPM_MICBIAS("micbias2", RT5671_PWR_ANLG2,
  5225. + RT5671_PWR_MB2_BIT, 0),
  5226. + /* Input Lines */
  5227. + SND_SOC_DAPM_INPUT("DMIC L1"),
  5228. + SND_SOC_DAPM_INPUT("DMIC R1"),
  5229. + SND_SOC_DAPM_INPUT("DMIC L2"),
  5230. + SND_SOC_DAPM_INPUT("DMIC R2"),
  5231. + SND_SOC_DAPM_INPUT("DMIC L3"),
  5232. + SND_SOC_DAPM_INPUT("DMIC R3"),
  5233. +
  5234. + SND_SOC_DAPM_INPUT("IN1P"),
  5235. + SND_SOC_DAPM_INPUT("IN1N"),
  5236. + SND_SOC_DAPM_INPUT("IN2P"),
  5237. + SND_SOC_DAPM_INPUT("IN2N"),
  5238. + SND_SOC_DAPM_INPUT("IN3P"),
  5239. + SND_SOC_DAPM_INPUT("IN3N"),
  5240. + SND_SOC_DAPM_INPUT("IN4P"),
  5241. + SND_SOC_DAPM_INPUT("IN4N"),
  5242. +
  5243. + SND_SOC_DAPM_PGA_E("DMIC1", SND_SOC_NOPM,
  5244. + 0, 0, NULL, 0, NULL,
  5245. + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  5246. + SND_SOC_DAPM_PGA_E("DMIC2", SND_SOC_NOPM,
  5247. + 0, 0, NULL, 0, NULL,
  5248. + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  5249. + SND_SOC_DAPM_PGA_E("DMIC3", SND_SOC_NOPM,
  5250. + 0, 0, NULL, 0, NULL,
  5251. + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  5252. + SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
  5253. + set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  5254. + SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5671_DMIC_CTRL1,
  5255. + RT5671_DMIC_1_EN_SFT, 0, rt5671_set_dmic1_event,
  5256. + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  5257. + SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5671_DMIC_CTRL1,
  5258. + RT5671_DMIC_2_EN_SFT, 0, rt5671_set_dmic2_event,
  5259. + SND_SOC_DAPM_PRE_PMU),
  5260. + SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5671_DMIC_CTRL1,
  5261. + RT5671_DMIC_3_EN_SFT, 0, rt5671_set_dmic3_event,
  5262. + SND_SOC_DAPM_PRE_PMU),
  5263. +
  5264. + /* Boost */
  5265. + SND_SOC_DAPM_PGA_E("BST1", RT5671_PWR_ANLG2,
  5266. + RT5671_PWR_BST1_BIT, 0, NULL, 0, rt5671_bst1_event,
  5267. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5268. + SND_SOC_DAPM_PGA_E("BST2", RT5671_PWR_ANLG2,
  5269. + RT5671_PWR_BST2_BIT, 0, NULL, 0, rt5671_bst2_event,
  5270. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5271. + SND_SOC_DAPM_PGA_E("BST3", RT5671_PWR_ANLG2,
  5272. + RT5671_PWR_BST3_BIT, 0, NULL, 0, rt5671_bst3_event,
  5273. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5274. + SND_SOC_DAPM_PGA_E("BST4", RT5671_PWR_ANLG2,
  5275. + RT5671_PWR_BST4_BIT, 0, NULL, 0, rt5671_bst4_event,
  5276. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5277. + /* Input Volume */
  5278. + SND_SOC_DAPM_PGA("INL VOL", RT5671_PWR_VOL,
  5279. + RT5671_PWR_IN_L_BIT, 0, NULL, 0),
  5280. + SND_SOC_DAPM_PGA("INR VOL", RT5671_PWR_VOL,
  5281. + RT5671_PWR_IN_R_BIT, 0, NULL, 0),
  5282. +
  5283. + /* REC Mixer */
  5284. + SND_SOC_DAPM_MIXER("RECMIXL", RT5671_PWR_MIXER, RT5671_PWR_RM_L_BIT, 0,
  5285. + rt5671_rec_l_mix, ARRAY_SIZE(rt5671_rec_l_mix)),
  5286. + SND_SOC_DAPM_MIXER("RECMIXR", RT5671_PWR_MIXER, RT5671_PWR_RM_R_BIT, 0,
  5287. + rt5671_rec_r_mix, ARRAY_SIZE(rt5671_rec_r_mix)),
  5288. + SND_SOC_DAPM_MIXER("RECMIXM", RT5671_PWR_MIXER, RT5671_PWR_RM_M_BIT, 0,
  5289. + rt5671_rec_m_mix, ARRAY_SIZE(rt5671_rec_m_mix)),
  5290. + /* ADCs */
  5291. + SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  5292. + SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
  5293. + SND_SOC_DAPM_ADC("ADC 3", NULL, SND_SOC_NOPM, 0, 0),
  5294. +
  5295. + SND_SOC_DAPM_MUX_E("ADC 1_2", SND_SOC_NOPM, 0, 0,
  5296. + &rt5671_sto_adc12_mux, rt5671_sto_adc12_event,
  5297. + SND_SOC_DAPM_POST_REG),
  5298. +
  5299. + SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5671_PWR_DIG1,
  5300. + RT5671_PWR_ADC_L_BIT, 0, NULL, 0),
  5301. + SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5671_PWR_DIG1,
  5302. + RT5671_PWR_ADC_R_BIT, 0, NULL, 0),
  5303. + SND_SOC_DAPM_SUPPLY("ADC 3 power", RT5671_PWR_DIG1,
  5304. + RT5671_PWR_ADC_3_BIT, 0, NULL, 0),
  5305. + SND_SOC_DAPM_SUPPLY("ADC clock", SND_SOC_NOPM, 0, 0,
  5306. + rt5671_adc_clk_event, SND_SOC_DAPM_POST_PMD |
  5307. + SND_SOC_DAPM_POST_PMU),
  5308. + /* ADC Mux */
  5309. + SND_SOC_DAPM_MUX("Stereo1 ADC Mux", SND_SOC_NOPM, 0, 0,
  5310. + &rt5671_sto_adc_mux),
  5311. + SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
  5312. + &rt5671_sto1_dmic_mux),
  5313. + SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  5314. + &rt5671_sto_adc2_mux),
  5315. + SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  5316. + &rt5671_sto_adc1_mux),
  5317. + SND_SOC_DAPM_MUX("Stereo2 ADC Mux", SND_SOC_NOPM, 0, 0,
  5318. + &rt5671_sto2_adc_mux),
  5319. + SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
  5320. + &rt5671_sto2_dmic_mux),
  5321. + SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
  5322. + &rt5671_sto2_adc2_mux),
  5323. + SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
  5324. + &rt5671_sto2_adc1_mux),
  5325. + SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
  5326. + &rt5671_sto2_adc_lr_mux),
  5327. + SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
  5328. + &rt5671_mono_adc_l_mux),
  5329. + SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
  5330. + &rt5671_mono_adc_r_mux),
  5331. + SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
  5332. + &rt5671_mono_dmic_l_mux),
  5333. + SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
  5334. + &rt5671_mono_dmic_r_mux),
  5335. + SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  5336. + &rt5671_mono_adc_l2_mux),
  5337. + SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  5338. + &rt5671_mono_adc_l1_mux),
  5339. + SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  5340. + &rt5671_mono_adc_r1_mux),
  5341. + SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  5342. + &rt5671_mono_adc_r2_mux),
  5343. + /* ADC Mixer */
  5344. + SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5671_PWR_DIG2,
  5345. + RT5671_PWR_ADC_S1F_BIT, 0, rt5671_drc_event,
  5346. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5347. + SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5671_PWR_DIG2,
  5348. + RT5671_PWR_ADC_S2F_BIT, 0, NULL, 0),
  5349. + SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  5350. + rt5671_sto1_adc_l_mix, ARRAY_SIZE(rt5671_sto1_adc_l_mix)),
  5351. + SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  5352. + rt5671_sto1_adc_r_mix, ARRAY_SIZE(rt5671_sto1_adc_r_mix)),
  5353. + SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
  5354. + rt5671_sto2_adc_l_mix, ARRAY_SIZE(rt5671_sto2_adc_l_mix)),
  5355. + SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
  5356. + rt5671_sto2_adc_r_mix, ARRAY_SIZE(rt5671_sto2_adc_r_mix)),
  5357. + SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5671_PWR_DIG2,
  5358. + RT5671_PWR_ADC_MF_L_BIT, 0, NULL, 0),
  5359. + SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
  5360. + rt5671_mono_adc_l_mix, ARRAY_SIZE(rt5671_mono_adc_l_mix),
  5361. + rt5671_mono_adcl_event, SND_SOC_DAPM_PRE_PMD |
  5362. + SND_SOC_DAPM_POST_PMU),
  5363. + SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5671_PWR_DIG2,
  5364. + RT5671_PWR_ADC_MF_R_BIT, 0, NULL, 0),
  5365. + SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
  5366. + rt5671_mono_adc_r_mix, ARRAY_SIZE(rt5671_mono_adc_r_mix),
  5367. + rt5671_mono_adcr_event, SND_SOC_DAPM_PRE_PMD |
  5368. + SND_SOC_DAPM_POST_PMU),
  5369. +
  5370. + /* ADC PGA */
  5371. + SND_SOC_DAPM_PGA_S("Stereo1 ADC MIXL", 1, SND_SOC_NOPM, 0, 0,
  5372. + rt5671_sto1_adcl_event, SND_SOC_DAPM_PRE_PMD |
  5373. + SND_SOC_DAPM_POST_PMU),
  5374. + SND_SOC_DAPM_PGA_S("Stereo1 ADC MIXR", 1, SND_SOC_NOPM, 0, 0,
  5375. + rt5671_sto1_adcr_event, SND_SOC_DAPM_PRE_PMD |
  5376. + SND_SOC_DAPM_POST_PMU),
  5377. + SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
  5378. + SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
  5379. + SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5380. + SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5381. + SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5382. + SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5383. + SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5384. + SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  5385. + SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  5386. + SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  5387. + SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  5388. + SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  5389. +
  5390. + /* DSP */
  5391. + SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5392. + SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5393. + SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5394. + SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5395. +
  5396. + SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
  5397. + &rt5671_txdp_slot_mux),
  5398. +
  5399. + SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
  5400. + &rt5671_dsp_ul_mux),
  5401. + SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
  5402. + &rt5671_dsp_dl_mux),
  5403. +
  5404. + SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
  5405. + &rt5671_rxdp_mux),
  5406. +
  5407. + /* IF1 2 3 4 Mux */
  5408. + SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM, 0, 0,
  5409. + &rt5671_if1_adc_in_mux),
  5410. + SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
  5411. + &rt5671_if2_adc_in_mux),
  5412. + SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
  5413. + &rt5671_if3_adc_in_mux),
  5414. + SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
  5415. + &rt5671_if4_adc_in_mux),
  5416. +
  5417. + /* Digital Interface */
  5418. + SND_SOC_DAPM_SUPPLY("I2S1", RT5671_PWR_DIG1,
  5419. + RT5671_PWR_I2S1_BIT, 0, NULL, 0),
  5420. + SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  5421. + SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  5422. + SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5423. + SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5424. + SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5425. + SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5426. + SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5427. + SND_SOC_DAPM_SUPPLY("I2S2", RT5671_PWR_DIG1,
  5428. + RT5671_PWR_I2S2_BIT, 0, NULL, 0),
  5429. + SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5430. + SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5431. + SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5432. + SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5433. + SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5434. + SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5435. + SND_SOC_DAPM_SUPPLY("I2S3", RT5671_PWR_DIG1,
  5436. + RT5671_PWR_I2S3_BIT, 0, NULL, 0),
  5437. + SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5438. + SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5439. + SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5440. + SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5441. + SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5442. + SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5443. + SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5444. + SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5445. + SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5446. + SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
  5447. + SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  5448. + SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  5449. + SND_SOC_DAPM_SUPPLY("I2S4", RT5671_PWR_DIG1,
  5450. + RT5671_PWR_I2S4_BIT, 0, NULL, 0),
  5451. +
  5452. + /* Digital Interface Select */
  5453. + SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
  5454. + &rt5671_if1_adc1_in1_mux),
  5455. + SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
  5456. + &rt5671_if1_adc1_in2_mux),
  5457. + SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
  5458. + &rt5671_if1_adc2_in_mux),
  5459. + SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
  5460. + &rt5671_if1_adc2_in1_mux),
  5461. + SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
  5462. + &rt5671_vad_adc_mux),
  5463. +
  5464. + /* Audio Interface */
  5465. + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  5466. + SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  5467. + SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  5468. + SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  5469. + SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
  5470. + SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
  5471. + SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
  5472. + SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
  5473. +
  5474. + /* Audio DSP */
  5475. + SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
  5476. +
  5477. + /* Output Side */
  5478. + /* DAC mixer before sound effect */
  5479. + SND_SOC_DAPM_MIXER("DAC1 MIXL", RT5671_GEN_CTRL2, 12, 0,
  5480. + rt5671_dac_l_mix, ARRAY_SIZE(rt5671_dac_l_mix)),
  5481. + SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
  5482. + rt5671_dac_r_mix, ARRAY_SIZE(rt5671_dac_r_mix)),
  5483. + SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5484. +
  5485. + /* DAC2 channel Mux */
  5486. + SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
  5487. + &rt5671_dac_l2_mux),
  5488. + SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
  5489. + &rt5671_dac_r2_mux),
  5490. + SND_SOC_DAPM_PGA("DAC L2 Volume", RT5671_PWR_DIG1,
  5491. + RT5671_PWR_DAC_L2_BIT, 0, NULL, 0),
  5492. + SND_SOC_DAPM_PGA("DAC R2 Volume", RT5671_PWR_DIG1,
  5493. + RT5671_PWR_DAC_R2_BIT, 0, NULL, 0),
  5494. +
  5495. + SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0,
  5496. + &rt5671_dac1l_mux),
  5497. + SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0,
  5498. + &rt5671_dac1r_mux),
  5499. +
  5500. + /* Sidetone */
  5501. + SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
  5502. + &rt5671_sidetone_mux),
  5503. + SND_SOC_DAPM_MUX("ANC Mux", SND_SOC_NOPM, 0, 0,
  5504. + &rt5671_anc_mux),
  5505. + SND_SOC_DAPM_PGA("SNC", SND_SOC_NOPM,
  5506. + 0, 0, NULL, 0),
  5507. + /* DAC Mixer */
  5508. + SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5671_PWR_DIG2,
  5509. + RT5671_PWR_DAC_S1F_BIT, 0, NULL, 0),
  5510. + SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5671_PWR_DIG2,
  5511. + RT5671_PWR_DAC_MF_L_BIT, 0, NULL, 0),
  5512. + SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5671_PWR_DIG2,
  5513. + RT5671_PWR_DAC_MF_R_BIT, 0, NULL, 0),
  5514. + SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
  5515. + rt5671_sto_dac_l_mix, ARRAY_SIZE(rt5671_sto_dac_l_mix)),
  5516. + SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
  5517. + rt5671_sto_dac_r_mix, ARRAY_SIZE(rt5671_sto_dac_r_mix)),
  5518. + SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
  5519. + rt5671_mono_dac_l_mix, ARRAY_SIZE(rt5671_mono_dac_l_mix)),
  5520. + SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
  5521. + rt5671_mono_dac_r_mix, ARRAY_SIZE(rt5671_mono_dac_r_mix)),
  5522. + SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
  5523. + rt5671_dig_l_mix, ARRAY_SIZE(rt5671_dig_l_mix)),
  5524. + SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
  5525. + rt5671_dig_r_mix, ARRAY_SIZE(rt5671_dig_r_mix)),
  5526. + SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  5527. +
  5528. + /* DACs */
  5529. + SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5671_PWR_DIG1,
  5530. + RT5671_PWR_DAC_L1_BIT, 0, NULL, 0),
  5531. + SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5671_PWR_DIG1,
  5532. + RT5671_PWR_DAC_R1_BIT, 0, NULL, 0),
  5533. + SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
  5534. + SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
  5535. + SND_SOC_DAPM_DAC("DAC L2", NULL, RT5671_PWR_DIG1,
  5536. + RT5671_PWR_DAC_L2_BIT, 0),
  5537. +
  5538. + SND_SOC_DAPM_DAC("DAC R2", NULL, RT5671_PWR_DIG1,
  5539. + RT5671_PWR_DAC_R2_BIT, 0),
  5540. + /* OUT Mixer */
  5541. +
  5542. + SND_SOC_DAPM_MIXER("OUT MIXL", RT5671_PWR_MIXER, RT5671_PWR_OM_L_BIT,
  5543. + 0, rt5671_out_l_mix, ARRAY_SIZE(rt5671_out_l_mix)),
  5544. + SND_SOC_DAPM_MIXER("OUT MIXR", RT5671_PWR_MIXER, RT5671_PWR_OM_R_BIT,
  5545. + 0, rt5671_out_r_mix, ARRAY_SIZE(rt5671_out_r_mix)),
  5546. + /* Ouput Volume */
  5547. + SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5671_PWR_VOL, RT5671_PWR_HV_L_BIT,
  5548. + 0, rt5671_hpvoll_mix, ARRAY_SIZE(rt5671_hpvoll_mix)),
  5549. + SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5671_PWR_VOL, RT5671_PWR_HV_R_BIT,
  5550. + 0, rt5671_hpvolr_mix, ARRAY_SIZE(rt5671_hpvolr_mix)),
  5551. + SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
  5552. + 0, 0, NULL, 0),
  5553. + SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
  5554. + 0, 0, NULL, 0),
  5555. + SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
  5556. + 0, 0, NULL, 0),
  5557. +
  5558. + /* HPO/LOUT/Mono Mixer */
  5559. + SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
  5560. + rt5671_hpo_mix, ARRAY_SIZE(rt5671_hpo_mix)),
  5561. + SND_SOC_DAPM_MIXER("LOUT MIX", RT5671_PWR_ANLG1, RT5671_PWR_LM_BIT,
  5562. + 0, rt5671_lout_mix, ARRAY_SIZE(rt5671_lout_mix)),
  5563. + SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5671_PWR_ANLG1, RT5671_PWR_MM_BIT,
  5564. + 0, rt5671_mono_mix, ARRAY_SIZE(rt5671_mono_mix)),
  5565. + SND_SOC_DAPM_MIXER("MONOAmp MIX", SND_SOC_NOPM, 0,
  5566. + 0, rt5671_monoamp_mix, ARRAY_SIZE(rt5671_monoamp_mix)),
  5567. +
  5568. + SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM,
  5569. + 0, 0, rt5671_hp_power_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  5570. + SND_SOC_DAPM_SUPPLY("HP L Amp", RT5671_PWR_ANLG1,
  5571. + RT5671_PWR_HP_L_BIT, 0, NULL, 0),
  5572. + SND_SOC_DAPM_SUPPLY("HP R Amp", RT5671_PWR_ANLG1,
  5573. + RT5671_PWR_HP_R_BIT, 0, NULL, 0),
  5574. + SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
  5575. + rt5671_hp_event, SND_SOC_DAPM_PRE_PMD |
  5576. + SND_SOC_DAPM_POST_PMU),
  5577. + SND_SOC_DAPM_PGA_S("LOUT Amp", 1, SND_SOC_NOPM, 0, 0,
  5578. + rt5671_lout_event, SND_SOC_DAPM_PRE_PMD |
  5579. + SND_SOC_DAPM_POST_PMU),
  5580. + SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5671_PWR_ANLG1,
  5581. + RT5671_PWR_MA_BIT, 0, rt5671_mono_event,
  5582. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5583. +
  5584. + /* PDM */
  5585. + SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5671_PWR_DIG2,
  5586. + RT5671_PWR_PDM1_BIT, 0, NULL, 0),
  5587. + SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5671_PWR_DIG2,
  5588. + RT5671_PWR_PDM2_BIT, 0, NULL, 0),
  5589. +
  5590. + SND_SOC_DAPM_MUX_E("PDM1 L Mux", SND_SOC_NOPM, 0, 0,
  5591. + &rt5671_pdm1_l_mux, rt5671_pdm1_l_event,
  5592. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5593. + SND_SOC_DAPM_MUX_E("PDM1 R Mux", SND_SOC_NOPM, 0, 0,
  5594. + &rt5671_pdm1_r_mux, rt5671_pdm1_r_event,
  5595. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5596. + SND_SOC_DAPM_MUX_E("PDM2 L Mux", SND_SOC_NOPM, 0, 0,
  5597. + &rt5671_pdm2_l_mux, rt5671_pdm2_l_event,
  5598. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5599. + SND_SOC_DAPM_MUX_E("PDM2 R Mux", SND_SOC_NOPM, 0, 0,
  5600. + &rt5671_pdm2_r_mux, rt5671_pdm2_r_event,
  5601. + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  5602. +
  5603. + /* Output Lines */
  5604. + SND_SOC_DAPM_OUTPUT("HPOL"),
  5605. + SND_SOC_DAPM_OUTPUT("HPOR"),
  5606. + SND_SOC_DAPM_OUTPUT("LOUTL"),
  5607. + SND_SOC_DAPM_OUTPUT("LOUTR"),
  5608. + SND_SOC_DAPM_OUTPUT("MonoP"),
  5609. + SND_SOC_DAPM_OUTPUT("MonoN"),
  5610. + SND_SOC_DAPM_OUTPUT("PDM1L"),
  5611. + SND_SOC_DAPM_OUTPUT("PDM1R"),
  5612. + SND_SOC_DAPM_OUTPUT("PDM2L"),
  5613. + SND_SOC_DAPM_OUTPUT("PDM2R"),
  5614. +};
  5615. +
  5616. +static const struct snd_soc_dapm_route rt5671_dapm_routes[] = {
  5617. + { "adc stereo1 filter", NULL, "ADC STO1 ASRC", check_adc_sto1_asrc_source },
  5618. + { "adc stereo2 filter", NULL, "ADC STO2 ASRC", check_adc_sto2_asrc_source },
  5619. + { "adc mono left filter", NULL, "ADC MONO L ASRC", check_adc_monol_asrc_source },
  5620. + { "adc mono right filter", NULL, "ADC MONO R ASRC", check_adc_monor_asrc_source },
  5621. + { "dac mono left filter", NULL, "DAC MONO L ASRC", check_dac_monol_asrc_source },
  5622. + { "dac mono right filter", NULL, "DAC MONO R ASRC", check_dac_monor_asrc_source },
  5623. + { "dac stereo1 filter", NULL, "DAC STO ASRC", check_dac_sto_asrc_source },
  5624. +
  5625. + {"I2S1", NULL, "I2S1 ASRC"},
  5626. + {"I2S2", NULL, "I2S2 ASRC"},
  5627. + {"I2S3", NULL, "I2S3 ASRC"},
  5628. + {"I2S4", NULL, "I2S4 ASRC"},
  5629. +
  5630. + { "micbias1", NULL, "DAC L1 Power" },
  5631. + { "micbias1", NULL, "DAC R1 Power" },
  5632. + { "micbias2", NULL, "DAC L1 Power" },
  5633. + { "micbias2", NULL, "DAC R1 Power" },
  5634. +
  5635. + { "DMIC1", NULL, "DMIC L1" },
  5636. + { "DMIC1", NULL, "DMIC R1" },
  5637. + { "DMIC2", NULL, "DMIC L2" },
  5638. + { "DMIC2", NULL, "DMIC R2" },
  5639. + { "DMIC3", NULL, "DMIC L3" },
  5640. + { "DMIC3", NULL, "DMIC R3" },
  5641. +
  5642. + { "BST1", NULL, "IN1P" },
  5643. + { "BST1", NULL, "IN1N" },
  5644. + { "BST1", NULL, "Mic Det Power" },
  5645. + { "BST2", NULL, "IN2P" },
  5646. + { "BST2", NULL, "IN2N" },
  5647. + { "BST3", NULL, "IN3P" },
  5648. + { "BST3", NULL, "IN3N" },
  5649. + { "BST4", NULL, "IN4P" },
  5650. + { "BST4", NULL, "IN4N" },
  5651. +
  5652. + { "INL VOL", NULL, "IN3P" },
  5653. + { "INR VOL", NULL, "IN3N" },
  5654. +
  5655. + { "RECMIXL", "INL Switch", "INL VOL" },
  5656. + { "RECMIXL", "BST4 Switch", "BST4" },
  5657. + { "RECMIXL", "BST3 Switch", "BST3" },
  5658. + { "RECMIXL", "BST2 Switch", "BST2" },
  5659. + { "RECMIXL", "BST1 Switch", "BST1" },
  5660. +
  5661. + { "RECMIXR", "INR Switch", "INR VOL" },
  5662. + { "RECMIXR", "BST4 Switch", "BST4" },
  5663. + { "RECMIXR", "BST3 Switch", "BST3" },
  5664. + { "RECMIXR", "BST2 Switch", "BST2" },
  5665. + { "RECMIXR", "BST1 Switch", "BST1" },
  5666. +
  5667. + { "RECMIXM", "BST4 Switch", "BST4" },
  5668. + { "RECMIXM", "BST3 Switch", "BST3" },
  5669. + { "RECMIXM", "BST2 Switch", "BST2" },
  5670. + { "RECMIXM", "BST1 Switch", "BST1" },
  5671. +
  5672. + { "ADC 1", NULL, "RECMIXL" },
  5673. + { "ADC 1", NULL, "ADC 1 power" },
  5674. + { "ADC 1", NULL, "ADC clock" },
  5675. + { "ADC 2", NULL, "RECMIXR" },
  5676. + { "ADC 2", NULL, "ADC 2 power" },
  5677. + { "ADC 2", NULL, "ADC clock" },
  5678. + { "ADC 3", NULL, "RECMIXM" },
  5679. + { "ADC 3", NULL, "ADC 3 power" },
  5680. + { "ADC 3", NULL, "ADC clock" },
  5681. +
  5682. + { "DMIC L1", NULL, "DMIC CLK" },
  5683. + { "DMIC R1", NULL, "DMIC CLK" },
  5684. + { "DMIC L2", NULL, "DMIC CLK" },
  5685. + { "DMIC R2", NULL, "DMIC CLK" },
  5686. + { "DMIC L3", NULL, "DMIC CLK" },
  5687. + { "DMIC R3", NULL, "DMIC CLK" },
  5688. +
  5689. + { "DMIC L1", NULL, "DMIC1 Power" },
  5690. + { "DMIC R1", NULL, "DMIC1 Power" },
  5691. + { "DMIC L2", NULL, "DMIC2 Power" },
  5692. + { "DMIC R2", NULL, "DMIC2 Power" },
  5693. + { "DMIC L3", NULL, "DMIC3 Power" },
  5694. + { "DMIC R3", NULL, "DMIC3 Power" },
  5695. +
  5696. + { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
  5697. + { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
  5698. + { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
  5699. +
  5700. + { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
  5701. + { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
  5702. + { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
  5703. +
  5704. + { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
  5705. + { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
  5706. + { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
  5707. +
  5708. + { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
  5709. + { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
  5710. + { "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
  5711. +
  5712. + { "ADC 1_2", "ADC", "ADC 1" },
  5713. + { "ADC 1_2", "ADC", "ADC 2" },
  5714. +
  5715. + { "ADC 1_2", "Stereo DAC", "Stereo DAC MIXL" },
  5716. + { "ADC 1_2", "Stereo DAC", "Stereo DAC MIXR" },
  5717. +
  5718. + { "Stereo1 ADC Mux", "ADC1L ADC2R", "ADC 1_2" },
  5719. + { "Stereo1 ADC Mux", "ADC3", "ADC 3" },
  5720. +
  5721. + { "DAC MIX", NULL, "DAC MIXL" },
  5722. + { "DAC MIX", NULL, "DAC MIXR" },
  5723. +
  5724. + { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
  5725. + { "Stereo1 ADC2 Mux", "DAC MIX", "DAC MIX" },
  5726. + { "Stereo1 ADC1 Mux", "ADC", "Stereo1 ADC Mux" },
  5727. + { "Stereo1 ADC1 Mux", "DAC MIX", "DAC MIX" },
  5728. +
  5729. + { "Mono ADC L Mux", "ADC1", "ADC 1" },
  5730. + { "Mono ADC L Mux", "ADC3", "ADC 3" },
  5731. +
  5732. + { "Mono ADC R Mux", "ADC2", "ADC 2" },
  5733. + { "Mono ADC R Mux", "ADC3", "ADC 3" },
  5734. +
  5735. + { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
  5736. + { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
  5737. + { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
  5738. + { "Mono ADC L1 Mux", "ADC1 ADC3", "Mono ADC L Mux" },
  5739. +
  5740. + { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
  5741. + { "Mono ADC R1 Mux", "ADC2 ADC3", "Mono ADC R Mux" },
  5742. + { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
  5743. + { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
  5744. +
  5745. + { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
  5746. + { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
  5747. + { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
  5748. + { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
  5749. +
  5750. + { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
  5751. + { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
  5752. +
  5753. + { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
  5754. + { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
  5755. + { "adc stereo1 filter", NULL, "PLL1", check_sysclk1_source },
  5756. +
  5757. + { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
  5758. + { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
  5759. + { "Mono ADC MIXL", NULL, "adc mono left filter" },
  5760. + { "adc mono left filter", NULL, "PLL1", check_sysclk1_source },
  5761. +
  5762. + { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
  5763. + { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
  5764. + { "Mono ADC MIXR", NULL, "adc mono right filter" },
  5765. + { "adc mono right filter", NULL, "PLL1", check_sysclk1_source },
  5766. +
  5767. + { "Stereo2 ADC Mux", "ADC1L ADC2R", "ADC 1_2" },
  5768. + { "Stereo2 ADC Mux", "ADC3", "ADC 3" },
  5769. +
  5770. + { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
  5771. + { "Stereo2 ADC2 Mux", "DAC MIX", "DAC MIX" },
  5772. + { "Stereo2 ADC1 Mux", "ADC", "Stereo2 ADC Mux" },
  5773. + { "Stereo2 ADC1 Mux", "DAC MIX", "DAC MIX" },
  5774. +
  5775. + { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
  5776. + { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
  5777. + { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
  5778. + { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
  5779. +
  5780. + { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
  5781. + { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
  5782. +
  5783. + { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
  5784. + { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
  5785. +
  5786. + { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
  5787. + { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
  5788. +
  5789. + { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
  5790. + { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
  5791. + { "adc stereo2 filter", NULL, "PLL1", check_sysclk1_source },
  5792. +
  5793. + { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
  5794. + { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
  5795. + { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
  5796. + { "VAD ADC Mux", "Sto2 ADC L", "Stereo2 ADC MIXL" },
  5797. +
  5798. + { "VAD_ADC", NULL, "VAD ADC Mux" },
  5799. +
  5800. + { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
  5801. + { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
  5802. + { "IF_ADC2", NULL, "Mono ADC MIXL" },
  5803. + { "IF_ADC2", NULL, "Mono ADC MIXR" },
  5804. + { "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
  5805. + { "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
  5806. +
  5807. + { "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
  5808. + { "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF_ADC3" },
  5809. +
  5810. + { "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
  5811. + { "IF1 ADC1 IN2 Mux", "IF1_ADC4", "TxDP_ADC" },
  5812. +
  5813. + { "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
  5814. + { "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
  5815. +
  5816. + { "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
  5817. + { "IF1 ADC2 IN1 Mux", "IF1_ADC4", "TxDP_ADC" },
  5818. +
  5819. + { "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
  5820. + { "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
  5821. +
  5822. + { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
  5823. + { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
  5824. + { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
  5825. + { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
  5826. + { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
  5827. + { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
  5828. +
  5829. + { "RxDP Mux", "IF2 DAC", "IF2 DAC" },
  5830. + { "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
  5831. + { "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
  5832. + { "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
  5833. + { "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
  5834. + { "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
  5835. + { "RxDP Mux", "DAC1", "DAC1 MIX" },
  5836. +
  5837. + { "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
  5838. + { "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
  5839. + { "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
  5840. + { "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
  5841. +
  5842. + { "DSP UL Mux", "Bypass", "TDM Data Mux" },
  5843. + { "DSP UL Mux", NULL, "I2S DSP" },
  5844. + { "DSP DL Mux", "Bypass", "RxDP Mux" },
  5845. + { "DSP DL Mux", NULL, "I2S DSP" },
  5846. +
  5847. + { "TxDP_ADC_L", NULL, "DSP UL Mux" },
  5848. + { "TxDP_ADC_R", NULL, "DSP UL Mux" },
  5849. + { "TxDC_DAC", NULL, "DSP DL Mux" },
  5850. +
  5851. + { "TxDP_ADC", NULL, "TxDP_ADC_L" },
  5852. + { "TxDP_ADC", NULL, "TxDP_ADC_R" },
  5853. +
  5854. + { "IF1 ADC", NULL, "I2S1" },
  5855. +#ifdef USE_TDM
  5856. + { "IF1 ADC", NULL, "IF1_ADC1" },
  5857. + { "IF1 ADC", NULL, "IF1_ADC2" },
  5858. + { "IF1 ADC", NULL, "IF_ADC3" },
  5859. + { "IF1 ADC", NULL, "TxDP_ADC" },
  5860. +#else
  5861. + { "IF1 ADC Mux", "IF1_ADC1", "IF1_ADC1" },
  5862. + { "IF1 ADC Mux", "IF1_ADC2", "IF1_ADC2" },
  5863. + { "IF1 ADC Mux", "IF_ADC3", "IF_ADC3" },
  5864. + { "IF1 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
  5865. + { "IF1 ADC", NULL, "IF1 ADC Mux" },
  5866. +#endif
  5867. + { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
  5868. + { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
  5869. + { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
  5870. + { "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
  5871. + { "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
  5872. + { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
  5873. +
  5874. + { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
  5875. + { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
  5876. + { "IF3 ADC Mux", "IF_ADC3", "IF_ADC3" },
  5877. + { "IF3 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
  5878. + { "IF3 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
  5879. + { "IF3 ADC Mux", "VAD_ADC", "VAD_ADC" },
  5880. +
  5881. + { "IF4 ADC Mux", "IF_ADC1", "IF_ADC1" },
  5882. + { "IF4 ADC Mux", "IF_ADC2", "IF_ADC2" },
  5883. + { "IF4 ADC Mux", "IF_ADC3", "IF_ADC3" },
  5884. +
  5885. + { "IF2 ADC L", NULL, "IF2 ADC Mux" },
  5886. + { "IF2 ADC R", NULL, "IF2 ADC Mux" },
  5887. + { "IF3 ADC L", NULL, "IF3 ADC Mux" },
  5888. + { "IF3 ADC R", NULL, "IF3 ADC Mux" },
  5889. + { "IF4 ADC L", NULL, "IF4 ADC Mux" },
  5890. + { "IF4 ADC R", NULL, "IF4 ADC Mux" },
  5891. +
  5892. + { "IF2 ADC", NULL, "I2S2" },
  5893. + { "IF2 ADC", NULL, "IF2 ADC L" },
  5894. + { "IF2 ADC", NULL, "IF2 ADC R" },
  5895. + { "IF3 ADC", NULL, "I2S3" },
  5896. + { "IF3 ADC", NULL, "IF3 ADC L" },
  5897. + { "IF3 ADC", NULL, "IF3 ADC R" },
  5898. + { "IF4 ADC", NULL, "I2S4" },
  5899. + { "IF4 ADC", NULL, "IF4 ADC L" },
  5900. + { "IF4 ADC", NULL, "IF4 ADC R" },
  5901. +
  5902. + { "AIF1TX", NULL, "IF1 ADC" },
  5903. + { "AIF2TX", NULL, "IF2 ADC" },
  5904. + { "AIF3TX", NULL, "IF3 ADC" },
  5905. + { "AIF4TX", NULL, "IF4 ADC" },
  5906. +
  5907. + { "IF1 DAC1", NULL, "AIF1RX" },
  5908. + { "IF1 DAC2", NULL, "AIF1RX" },
  5909. + { "IF2 DAC", NULL, "AIF2RX" },
  5910. + { "IF3 DAC", NULL, "AIF3RX" },
  5911. + { "IF4 DAC", NULL, "AIF4RX" },
  5912. +
  5913. + { "IF1 DAC1", NULL, "I2S1" },
  5914. + { "IF1 DAC2", NULL, "I2S1" },
  5915. + { "IF2 DAC", NULL, "I2S2" },
  5916. + { "IF3 DAC", NULL, "I2S3" },
  5917. + { "IF4 DAC", NULL, "I2S4" },
  5918. +
  5919. + { "IF1 DAC2 L", NULL, "IF1 DAC2" },
  5920. + { "IF1 DAC2 R", NULL, "IF1 DAC2" },
  5921. + { "IF1 DAC1 L", NULL, "IF1 DAC1" },
  5922. + { "IF1 DAC1 R", NULL, "IF1 DAC1" },
  5923. + { "IF2 DAC L", NULL, "IF2 DAC" },
  5924. + { "IF2 DAC R", NULL, "IF2 DAC" },
  5925. + { "IF3 DAC L", NULL, "IF3 DAC" },
  5926. + { "IF3 DAC R", NULL, "IF3 DAC" },
  5927. + { "IF4 DAC L", NULL, "IF4 DAC" },
  5928. + { "IF4 DAC R", NULL, "IF4 DAC" },
  5929. +
  5930. + { "Sidetone Mux", "DMIC L1", "DMIC L1" },
  5931. + { "Sidetone Mux", "DMIC L2", "DMIC L2" },
  5932. + { "Sidetone Mux", "DMIC L3", "DMIC L3" },
  5933. + { "Sidetone Mux", "ADC 1", "ADC 1" },
  5934. + { "Sidetone Mux", "ADC 2", "ADC 2" },
  5935. + { "Sidetone Mux", "ADC 3", "ADC 3" },
  5936. +
  5937. + { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
  5938. + { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
  5939. + { "DAC1 L Mux", "IF3 DAC", "IF3 DAC L" },
  5940. + { "DAC1 L Mux", "IF4 DAC", "IF4 DAC L" },
  5941. +
  5942. + { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
  5943. + { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
  5944. + { "DAC1 R Mux", "IF3 DAC", "IF3 DAC R" },
  5945. + { "DAC1 R Mux", "IF4 DAC", "IF4 DAC R" },
  5946. +
  5947. + { "DAC1 MIXL", NULL, "DAC L1 Power" },
  5948. + { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
  5949. + { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
  5950. + { "DAC1 MIXL", NULL, "dac stereo1 filter" },
  5951. + { "DAC1 MIXR", NULL, "DAC R1 Power" },
  5952. + { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
  5953. + { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
  5954. + { "DAC1 MIXR", NULL, "dac stereo1 filter" },
  5955. +
  5956. + { "DAC1 MIX", NULL, "DAC1 MIXL" },
  5957. + { "DAC1 MIX", NULL, "DAC1 MIXR" },
  5958. +
  5959. + { "Audio DSP", NULL, "DAC1 MIXL" },
  5960. + { "Audio DSP", NULL, "DAC1 MIXR" },
  5961. +
  5962. + { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
  5963. + { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
  5964. + { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
  5965. + { "DAC L2 Mux", "IF4 DAC", "IF4 DAC L" },
  5966. + { "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
  5967. + { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
  5968. + { "DAC L2 Volume", NULL, "DAC L2 Mux" },
  5969. + { "DAC L2 Volume", NULL, "dac mono left filter" },
  5970. +
  5971. + { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
  5972. + { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
  5973. + { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
  5974. + { "DAC R2 Mux", "IF4 DAC", "IF4 DAC R" },
  5975. + { "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
  5976. + { "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
  5977. + { "DAC R2 Volume", NULL, "DAC R2 Mux" },
  5978. + { "DAC R2 Volume", NULL, "dac mono right filter" },
  5979. +
  5980. + { "SNC", NULL, "ADC 1" },
  5981. + { "SNC", NULL, "ADC 2" },
  5982. +
  5983. + { "ANC Mux", "SNC", "SNC" },
  5984. + { "ANC Mux", "Sidetone", "Sidetone Mux" },
  5985. +
  5986. + { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
  5987. + { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
  5988. + { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  5989. + { "Stereo DAC MIXL", "ANC Switch", "ANC Mux" },
  5990. + { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
  5991. + { "Stereo DAC MIXL", NULL, "DAC L1 Power" },
  5992. + { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
  5993. + { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
  5994. + { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  5995. + { "Stereo DAC MIXR", "ANC Switch", "ANC Mux" },
  5996. + { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
  5997. + { "Stereo DAC MIXR", NULL, "DAC R1 Power" },
  5998. +
  5999. + { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
  6000. + { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  6001. + { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
  6002. + { "Mono DAC MIXL", "Sidetone Switch", "Sidetone Mux" },
  6003. + { "Mono DAC MIXL", NULL, "dac mono left filter" },
  6004. + { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
  6005. + { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  6006. + { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
  6007. + { "Mono DAC MIXR", "Sidetone Switch", "Sidetone Mux" },
  6008. + { "Mono DAC MIXR", NULL, "dac mono right filter" },
  6009. +
  6010. + { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
  6011. + { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
  6012. + { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
  6013. + { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
  6014. + { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
  6015. + { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
  6016. +
  6017. + { "DAC L1", NULL, "Stereo DAC MIXL" },
  6018. + { "DAC L1", NULL, "PLL1", check_sysclk1_source },
  6019. + { "DAC R1", NULL, "Stereo DAC MIXR" },
  6020. + { "DAC R1", NULL, "PLL1", check_sysclk1_source },
  6021. + { "DAC L2", NULL, "Mono DAC MIXL" },
  6022. + { "DAC L2", NULL, "PLL1", check_sysclk1_source },
  6023. + { "DAC R2", NULL, "Mono DAC MIXR" },
  6024. + { "DAC R2", NULL, "PLL1", check_sysclk1_source },
  6025. +
  6026. + { "OUT MIXL", "BST2 Switch", "BST2" },
  6027. + { "OUT MIXL", "BST1 Switch", "BST1" },
  6028. + { "OUT MIXL", "INL Switch", "INL VOL" },
  6029. + { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
  6030. + { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
  6031. +
  6032. + { "OUT MIXR", "BST4 Switch", "BST4" },
  6033. + { "OUT MIXR", "BST3 Switch", "BST3" },
  6034. + { "OUT MIXR", "INR Switch", "INR VOL" },
  6035. + { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
  6036. + { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
  6037. +
  6038. + { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
  6039. + { "HPOVOL MIXL", "INL Switch", "INL VOL" },
  6040. + { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
  6041. + { "HPOVOL MIXR", "INR Switch", "INR VOL" },
  6042. +
  6043. + { "DAC 2", NULL, "DAC L2" },
  6044. + { "DAC 2", NULL, "DAC R2" },
  6045. + { "DAC 1", NULL, "DAC L1" },
  6046. + { "DAC 1", NULL, "DAC R1" },
  6047. + { "HPOVOL", NULL, "HPOVOL MIXL" },
  6048. + { "HPOVOL", NULL, "HPOVOL MIXR" },
  6049. + { "HPO MIX", "DAC1 Switch", "DAC 1" },
  6050. + { "HPO MIX", "HPVOL Switch", "HPOVOL" },
  6051. +
  6052. + { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
  6053. + { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
  6054. + { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
  6055. + { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
  6056. +
  6057. + { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
  6058. + { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
  6059. + { "MONOVOL MIX", "BST4 Switch", "BST4" },
  6060. +
  6061. + { "MONOAmp MIX", "DAC L1 Switch", "DAC L1" },
  6062. + { "MONOAmp MIX", "MONOVOL Switch", "MONOVOL MIX" },
  6063. +
  6064. + { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
  6065. + { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
  6066. + { "PDM1 L Mux", NULL, "PDM1 Power" },
  6067. + { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
  6068. + { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
  6069. + { "PDM1 R Mux", NULL, "PDM1 Power" },
  6070. + { "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
  6071. + { "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
  6072. + { "PDM2 L Mux", NULL, "PDM2 Power" },
  6073. + { "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
  6074. + { "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
  6075. + { "PDM2 R Mux", NULL, "PDM2 Power" },
  6076. +
  6077. + { "HP Amp", NULL, "HPO MIX" },
  6078. + { "HP Amp", NULL, "Mic Det Power" },
  6079. + { "HPOL", NULL, "HP Amp" },
  6080. + { "HPOL", NULL, "HP L Amp" },
  6081. + { "HPOL", NULL, "Improve HP Amp Drv" },
  6082. + { "HPOR", NULL, "HP Amp" },
  6083. + { "HPOR", NULL, "HP R Amp" },
  6084. + { "HPOR", NULL, "Improve HP Amp Drv" },
  6085. +
  6086. + { "LOUT Amp", NULL, "LOUT MIX" },
  6087. + { "LOUTL", NULL, "LOUT Amp" },
  6088. + { "LOUTR", NULL, "LOUT Amp" },
  6089. + { "LOUTL", NULL, "Improve HP Amp Drv" },
  6090. + { "LOUTR", NULL, "Improve HP Amp Drv" },
  6091. +
  6092. + { "Mono Amp", NULL, "MONOAmp MIX" },
  6093. + { "MonoP", NULL, "Mono Amp" },
  6094. + { "MonoN", NULL, "Mono Amp" },
  6095. +
  6096. + { "PDM1L", NULL, "PDM1 L Mux" },
  6097. + { "PDM1R", NULL, "PDM1 R Mux" },
  6098. + { "PDM2L", NULL, "PDM2 L Mux" },
  6099. + { "PDM2R", NULL, "PDM2 R Mux" },
  6100. +};
  6101. +
  6102. +static int get_clk_info(int sclk, int rate)
  6103. +{
  6104. + int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
  6105. +
  6106. + if (sclk <= 0 || rate <= 0)
  6107. + return -EINVAL;
  6108. +
  6109. + rate = rate << 8;
  6110. + for (i = 0; i < ARRAY_SIZE(pd); i++)
  6111. + if (sclk == rate * pd[i])
  6112. + return i;
  6113. +
  6114. + return -EINVAL;
  6115. +}
  6116. +
  6117. +static int rt5671_hw_params(struct snd_pcm_substream *substream,
  6118. + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  6119. +{
  6120. + struct snd_soc_codec *codec = dai->codec;
  6121. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6122. + unsigned int val = 0, val_clk, mask_clk;
  6123. + int pre_div, bclk_ms;
  6124. +
  6125. + rt5671->lrck[dai->id] = params_rate(params);
  6126. + pre_div = get_clk_info(rt5671->sysclk, rt5671->lrck[dai->id]);
  6127. + if (pre_div < 0) {
  6128. + dev_err(codec->dev, "Unsupported clock setting\n");
  6129. + return -EINVAL;
  6130. + }
  6131. +
  6132. + if (rt5671->pdata.bclk_32fs[dai->id])
  6133. + bclk_ms = 0;
  6134. + else
  6135. + bclk_ms = 1;
  6136. + rt5671->bclk[dai->id] = rt5671->lrck[dai->id] * (32 << bclk_ms);
  6137. +
  6138. + dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  6139. + rt5671->bclk[dai->id], rt5671->lrck[dai->id]);
  6140. + dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  6141. + bclk_ms, pre_div, dai->id);
  6142. +
  6143. + switch (params_format(params)) {
  6144. + case SNDRV_PCM_FORMAT_S16_LE:
  6145. + break;
  6146. + case SNDRV_PCM_FORMAT_S20_3LE:
  6147. + val |= RT5671_I2S_DL_20;
  6148. + break;
  6149. + case SNDRV_PCM_FORMAT_S24_LE:
  6150. + val |= RT5671_I2S_DL_24;
  6151. + break;
  6152. + case SNDRV_PCM_FORMAT_S8:
  6153. + val |= RT5671_I2S_DL_8;
  6154. + break;
  6155. + default:
  6156. + return -EINVAL;
  6157. + }
  6158. +
  6159. + if (rt5671->master[dai->id] == 0)
  6160. + val |= RT5671_I2S_MS_S;
  6161. +
  6162. + switch (dai->id) {
  6163. + case RT5671_AIF1:
  6164. + mask_clk = RT5671_I2S_PD1_MASK;
  6165. + val_clk = pre_div << RT5671_I2S_PD1_SFT;
  6166. + snd_soc_update_bits(codec, RT5671_ADDA_CLK1, mask_clk, val_clk);
  6167. + snd_soc_update_bits(codec, RT5671_I2S1_SDP,
  6168. + RT5671_I2S_DL_MASK | RT5671_I2S_MS_MASK, val);
  6169. + break;
  6170. + case RT5671_AIF2:
  6171. + mask_clk = RT5671_I2S_BCLK_MS2_MASK | RT5671_I2S_PD2_MASK;
  6172. + val_clk = bclk_ms << RT5671_I2S_BCLK_MS2_SFT |
  6173. + pre_div << RT5671_I2S_PD2_SFT;
  6174. + snd_soc_update_bits(codec, RT5671_ADDA_CLK1, mask_clk, val_clk);
  6175. + snd_soc_update_bits(codec, RT5671_I2S2_SDP,
  6176. + RT5671_I2S_DL_MASK | RT5671_I2S_MS_MASK, val);
  6177. + break;
  6178. + case RT5671_AIF3:
  6179. + mask_clk = RT5671_I2S_BCLK_MS3_MASK | RT5671_I2S_PD3_MASK;
  6180. + val_clk = bclk_ms << RT5671_I2S_BCLK_MS3_SFT |
  6181. + pre_div << RT5671_I2S_PD3_SFT;
  6182. + snd_soc_update_bits(codec, RT5671_ADDA_CLK1, mask_clk, val_clk);
  6183. + snd_soc_update_bits(codec, RT5671_I2S3_SDP,
  6184. + RT5671_I2S_DL_MASK | RT5671_I2S_MS_MASK, val);
  6185. + break;
  6186. + case RT5671_AIF4:
  6187. + mask_clk = RT5671_I2S_BCLK_MS4_MASK | RT5671_I2S_PD4_MASK;
  6188. + val_clk = bclk_ms << RT5671_I2S_BCLK_MS4_SFT |
  6189. + pre_div << RT5671_I2S_PD4_SFT;
  6190. + snd_soc_update_bits(codec, RT5671_DSP_CLK, mask_clk, val_clk);
  6191. + snd_soc_update_bits(codec, RT5671_I2S4_SDP,
  6192. + RT5671_I2S_DL_MASK | RT5671_I2S_MS_MASK, val);
  6193. + break;
  6194. + }
  6195. +
  6196. + return 0;
  6197. +}
  6198. +
  6199. +static void rt5671_shutdown(struct snd_pcm_substream *substream,
  6200. + struct snd_soc_dai *dai)
  6201. +{
  6202. + struct snd_soc_codec *codec = dai->codec;
  6203. +
  6204. + if (!dai->active) {
  6205. + switch (dai->id) {
  6206. + case RT5671_AIF1:
  6207. + snd_soc_update_bits(codec, RT5671_I2S1_SDP,
  6208. + RT5671_I2S_MS_MASK, RT5671_I2S_MS_S);
  6209. + break;
  6210. + case RT5671_AIF2:
  6211. + snd_soc_update_bits(codec, RT5671_I2S2_SDP,
  6212. + RT5671_I2S_MS_MASK, RT5671_I2S_MS_S);
  6213. + break;
  6214. + case RT5671_AIF3:
  6215. + snd_soc_update_bits(codec, RT5671_I2S3_SDP,
  6216. + RT5671_I2S_MS_MASK, RT5671_I2S_MS_S);
  6217. + break;
  6218. + case RT5671_AIF4:
  6219. + snd_soc_update_bits(codec, RT5671_I2S4_SDP,
  6220. + RT5671_I2S_MS_MASK, RT5671_I2S_MS_S);
  6221. + break;
  6222. + }
  6223. + }
  6224. +}
  6225. +
  6226. +static int rt5671_prepare(struct snd_pcm_substream *substream,
  6227. + struct snd_soc_dai *dai)
  6228. +{
  6229. + struct snd_soc_codec *codec = dai->codec;
  6230. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6231. +
  6232. + rt5671->aif_pu = dai->id;
  6233. + return 0;
  6234. +}
  6235. +
  6236. +static int rt5671_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  6237. +{
  6238. + struct snd_soc_codec *codec = dai->codec;
  6239. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6240. + unsigned int reg_val = 0;
  6241. +
  6242. + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  6243. + case SND_SOC_DAIFMT_CBM_CFM:
  6244. + rt5671->master[dai->id] = 1;
  6245. + break;
  6246. + case SND_SOC_DAIFMT_CBS_CFS:
  6247. + rt5671->master[dai->id] = 0;
  6248. + break;
  6249. + default:
  6250. + return -EINVAL;
  6251. + }
  6252. +
  6253. + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  6254. + case SND_SOC_DAIFMT_NB_NF:
  6255. + break;
  6256. + case SND_SOC_DAIFMT_IB_NF:
  6257. + reg_val |= RT5671_I2S_BP_INV;
  6258. + break;
  6259. + default:
  6260. + return -EINVAL;
  6261. + }
  6262. +
  6263. + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  6264. + case SND_SOC_DAIFMT_I2S:
  6265. + break;
  6266. + case SND_SOC_DAIFMT_LEFT_J:
  6267. + reg_val |= RT5671_I2S_DF_LEFT;
  6268. + break;
  6269. + case SND_SOC_DAIFMT_DSP_A:
  6270. + reg_val |= RT5671_I2S_DF_PCM_A;
  6271. + break;
  6272. + case SND_SOC_DAIFMT_DSP_B:
  6273. + reg_val |= RT5671_I2S_DF_PCM_B;
  6274. + break;
  6275. + default:
  6276. + return -EINVAL;
  6277. + }
  6278. +
  6279. + switch (dai->id) {
  6280. + case RT5671_AIF1:
  6281. + snd_soc_update_bits(codec, RT5671_I2S1_SDP,
  6282. + RT5671_I2S_BP_MASK |
  6283. + RT5671_I2S_DF_MASK, reg_val);
  6284. + break;
  6285. + case RT5671_AIF2:
  6286. + snd_soc_update_bits(codec, RT5671_I2S2_SDP,
  6287. + RT5671_I2S_BP_MASK |
  6288. + RT5671_I2S_DF_MASK, reg_val);
  6289. + break;
  6290. + case RT5671_AIF3:
  6291. + snd_soc_update_bits(codec, RT5671_I2S3_SDP,
  6292. + RT5671_I2S_BP_MASK |
  6293. + RT5671_I2S_DF_MASK, reg_val);
  6294. + break;
  6295. + case RT5671_AIF4:
  6296. + snd_soc_update_bits(codec, RT5671_I2S4_SDP,
  6297. + RT5671_I2S_BP_MASK |
  6298. + RT5671_I2S_DF_MASK, reg_val);
  6299. + break;
  6300. + }
  6301. +
  6302. + return 0;
  6303. +}
  6304. +
  6305. +static int rt5671_set_dai_sysclk(struct snd_soc_dai *dai,
  6306. + int clk_id, unsigned int freq, int dir)
  6307. +{
  6308. + struct snd_soc_codec *codec = dai->codec;
  6309. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6310. + unsigned int reg_val = 0;
  6311. +
  6312. + if (freq == rt5671->sysclk && clk_id == rt5671->sysclk_src)
  6313. + return 0;
  6314. +
  6315. + if (SND_SOC_BIAS_OFF != codec->dapm.bias_level) {
  6316. + switch (clk_id) {
  6317. + case RT5671_SCLK_S_MCLK:
  6318. + reg_val |= RT5671_SCLK_SRC_MCLK;
  6319. + break;
  6320. + case RT5671_SCLK_S_PLL1:
  6321. + reg_val |= RT5671_SCLK_SRC_PLL1;
  6322. + break;
  6323. + case RT5671_SCLK_S_RCCLK:
  6324. + reg_val |= RT5671_SCLK_SRC_RCCLK;
  6325. + break;
  6326. + default:
  6327. + dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
  6328. + return -EINVAL;
  6329. + }
  6330. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6331. + RT5671_SCLK_SRC_MASK, reg_val);
  6332. + }
  6333. +
  6334. + rt5671->sysclk = freq;
  6335. + rt5671->sysclk_src = clk_id;
  6336. +
  6337. + dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  6338. +
  6339. + return 0;
  6340. +}
  6341. +
  6342. +/**
  6343. + * rt5671_pll_calc - Calcualte PLL M/N/K code.
  6344. + * @freq_in: external clock provided to codec.
  6345. + * @freq_out: target clock which codec works on.
  6346. + * @pll_code: Pointer to structure with M, N, K and bypass flag.
  6347. + *
  6348. + * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
  6349. + * which make calculation more efficiently.
  6350. + *
  6351. + * Returns 0 for success or negative error code.
  6352. + */
  6353. +static int rt5671_pll_calc(const unsigned int freq_in,
  6354. + const unsigned int freq_out, struct rt5671_pll_code *pll_code)
  6355. +{
  6356. + int max_n = RT5671_PLL_N_MAX, max_m = RT5671_PLL_M_MAX;
  6357. + int k, n = 0, m = 0, red, n_t, m_t, pll_out, in_t;
  6358. + int out_t, red_t = abs(freq_out - freq_in);
  6359. + bool bypass = false;
  6360. +
  6361. + if (RT5671_PLL_INP_MAX < freq_in || RT5671_PLL_INP_MIN > freq_in)
  6362. + return -EINVAL;
  6363. +
  6364. + k = 100000000 / freq_out - 2;
  6365. + if (k > RT5671_PLL_K_MAX)
  6366. + k = RT5671_PLL_K_MAX;
  6367. + for (n_t = 0; n_t <= max_n; n_t++) {
  6368. + in_t = freq_in / (k + 2);
  6369. + pll_out = freq_out / (n_t + 2);
  6370. + if (in_t < 0)
  6371. + continue;
  6372. + if (in_t == pll_out) {
  6373. + bypass = true;
  6374. + n = n_t;
  6375. + goto code_find;
  6376. + }
  6377. + red = abs(in_t - pll_out);
  6378. + if (red < red_t) {
  6379. + bypass = true;
  6380. + n = n_t;
  6381. + m = m_t;
  6382. + if (red == 0)
  6383. + goto code_find;
  6384. + red_t = red;
  6385. + }
  6386. + for (m_t = 0; m_t <= max_m; m_t++) {
  6387. + out_t = in_t / (m_t + 2);
  6388. + red = abs(out_t - pll_out);
  6389. + if (red < red_t) {
  6390. + bypass = false;
  6391. + n = n_t;
  6392. + m = m_t;
  6393. + if (red == 0)
  6394. + goto code_find;
  6395. + red_t = red;
  6396. + }
  6397. + }
  6398. + }
  6399. + pr_info("Only get approximation about PLL\n");
  6400. +
  6401. +code_find:
  6402. +
  6403. + pll_code->m_bp = bypass;
  6404. + pll_code->m_code = m;
  6405. + pll_code->n_code = n;
  6406. + pll_code->k_code = k;
  6407. + return 0;
  6408. +}
  6409. +
  6410. +static int rt5671_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  6411. + unsigned int freq_in, unsigned int freq_out)
  6412. +{
  6413. + struct snd_soc_codec *codec = dai->codec;
  6414. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6415. + struct rt5671_pll_code pll_code;
  6416. + int ret;
  6417. +
  6418. + if (source == rt5671->pll_src && freq_in == rt5671->pll_in &&
  6419. + freq_out == rt5671->pll_out)
  6420. + return 0;
  6421. +
  6422. + if (!freq_in || !freq_out) {
  6423. + dev_dbg(codec->dev, "PLL disabled\n");
  6424. +
  6425. + rt5671->pll_in = 0;
  6426. + rt5671->pll_out = 0;
  6427. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6428. + RT5671_SCLK_SRC_MASK, RT5671_SCLK_SRC_MCLK);
  6429. + return 0;
  6430. + }
  6431. +
  6432. + switch (source) {
  6433. + case RT5671_PLL1_S_MCLK:
  6434. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6435. + RT5671_PLL1_SRC_MASK, RT5671_PLL1_SRC_MCLK);
  6436. + break;
  6437. + case RT5671_PLL1_S_BCLK1:
  6438. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6439. + RT5671_PLL1_SRC_MASK, RT5671_PLL1_SRC_BCLK1);
  6440. + break;
  6441. + case RT5671_PLL1_S_BCLK2:
  6442. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6443. + RT5671_PLL1_SRC_MASK, RT5671_PLL1_SRC_BCLK2);
  6444. + break;
  6445. + case RT5671_PLL1_S_BCLK3:
  6446. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6447. + RT5671_PLL1_SRC_MASK, RT5671_PLL1_SRC_BCLK3);
  6448. + break;
  6449. + case RT5671_PLL1_S_BCLK4:
  6450. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6451. + RT5671_PLL1_SRC_MASK, RT5671_PLL1_SRC_BCLK4);
  6452. + break;
  6453. + default:
  6454. + dev_err(codec->dev, "Unknown PLL source %d\n", source);
  6455. + return -EINVAL;
  6456. + }
  6457. +
  6458. + ret = rt5671_pll_calc(freq_in, freq_out, &pll_code);
  6459. + if (ret < 0) {
  6460. + dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
  6461. + return ret;
  6462. + }
  6463. +
  6464. + dev_info(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
  6465. + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  6466. + pll_code.n_code, pll_code.k_code);
  6467. +
  6468. + snd_soc_write(codec, RT5671_PLL_CTRL1,
  6469. + pll_code.n_code << RT5671_PLL_N_SFT | pll_code.k_code);
  6470. + snd_soc_write(codec, RT5671_PLL_CTRL2,
  6471. + (pll_code.m_bp ? 0 : pll_code.m_code) << RT5671_PLL_M_SFT |
  6472. + pll_code.m_bp << RT5671_PLL_M_BP_SFT);
  6473. +
  6474. + rt5671->pll_in = freq_in;
  6475. + rt5671->pll_out = freq_out;
  6476. + rt5671->pll_src = source;
  6477. +
  6478. + dev_info(codec->dev, "pll_in=%d pll_out=%d pll_src=%d\n",
  6479. + rt5671->pll_in, rt5671->pll_out, rt5671->pll_src);
  6480. +
  6481. + return 0;
  6482. +}
  6483. +
  6484. +/**
  6485. + * rt5671_index_show - Dump private registers.
  6486. + * @dev: codec device.
  6487. + * @attr: device attribute.
  6488. + * @buf: buffer for display.
  6489. + *
  6490. + * To show non-zero values of all private registers.
  6491. + *
  6492. + * Returns buffer length.
  6493. + */
  6494. +static ssize_t rt5671_index_show(struct device *dev,
  6495. + struct device_attribute *attr, char *buf)
  6496. +{
  6497. + struct i2c_client *client = to_i2c_client(dev);
  6498. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6499. + struct snd_soc_codec *codec = rt5671->codec;
  6500. + unsigned int val;
  6501. + int cnt = 0, i;
  6502. +
  6503. + cnt += sprintf(buf, "RT5671 index register\n");
  6504. + for (i = 0; i < 0xff; i++) {
  6505. + if (cnt + RT5671_REG_DISP_LEN >= PAGE_SIZE)
  6506. + break;
  6507. + val = rt5671_index_read(codec, i);
  6508. + if (!val)
  6509. + continue;
  6510. + cnt += snprintf(buf + cnt, RT5671_REG_DISP_LEN,
  6511. + "%02x: %04x\n", i, val);
  6512. + }
  6513. +
  6514. + if (cnt >= PAGE_SIZE)
  6515. + cnt = PAGE_SIZE - 1;
  6516. +
  6517. + return cnt;
  6518. +}
  6519. +
  6520. +static ssize_t rt5671_index_store(struct device *dev,
  6521. + struct device_attribute *attr, const char *buf, size_t count)
  6522. +{
  6523. + struct i2c_client *client = to_i2c_client(dev);
  6524. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6525. + struct snd_soc_codec *codec = rt5671->codec;
  6526. + unsigned int val = 0, addr = 0;
  6527. + int i;
  6528. +
  6529. + for (i = 0; i < count; i++) {
  6530. + if (*(buf+i) <= '9' && *(buf + i) >= '0')
  6531. + addr = (addr << 4) | (*(buf + i) - '0');
  6532. + else if (*(buf+i) <= 'f' && *(buf + i) >= 'a')
  6533. + addr = (addr << 4) | ((*(buf + i) - 'a')+0xa);
  6534. + else if (*(buf+i) <= 'F' && *(buf+i) >= 'A')
  6535. + addr = (addr << 4) | ((*(buf + i) - 'A')+0xa);
  6536. + else
  6537. + break;
  6538. + }
  6539. +
  6540. + for (i = i + 1; i < count; i++) {
  6541. + if (*(buf+i) <= '9' && *(buf+i) >= '0')
  6542. + val = (val << 4) | (*(buf + i) - '0');
  6543. + else if (*(buf+i) <= 'f' && *(buf + i) >= 'a')
  6544. + val = (val << 4) | ((*(buf + i)-'a')+0xa);
  6545. + else if (*(buf+i) <= 'F' && *(buf + i) >= 'A')
  6546. + val = (val << 4) | ((*(buf + i) - 'A')+0xa);
  6547. + else
  6548. + break;
  6549. + }
  6550. + pr_debug("addr=0x%x val=0x%x\n", addr, val);
  6551. + if (addr > RT5671_VENDOR_ID2 || val > 0xffff || val < 0)
  6552. + return count;
  6553. +
  6554. + if (i == count)
  6555. + pr_debug("0x%02x = 0x%04x\n", addr,
  6556. + rt5671_index_read(codec, addr));
  6557. + else
  6558. + rt5671_index_write(codec, addr, val);
  6559. +
  6560. +
  6561. + return count;
  6562. +}
  6563. +static DEVICE_ATTR(index_reg, 0664, rt5671_index_show, rt5671_index_store);
  6564. +
  6565. +static ssize_t rt5671_codec_show(struct device *dev,
  6566. + struct device_attribute *attr, char *buf)
  6567. +{
  6568. + struct i2c_client *client = to_i2c_client(dev);
  6569. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6570. + struct snd_soc_codec *codec = rt5671->codec;
  6571. + unsigned int val;
  6572. + int cnt = 0, i;
  6573. +
  6574. + for (i = 0; i <= RT5671_VENDOR_ID2; i++) {
  6575. + if (cnt + RT5671_REG_DISP_LEN >= PAGE_SIZE)
  6576. + break;
  6577. +
  6578. + if (rt5671_readable_register(codec, i)) {
  6579. + val = snd_soc_read(codec, i);
  6580. +
  6581. + cnt += snprintf(buf + cnt, RT5671_REG_DISP_LEN,
  6582. + "%04x: %04x\n", i, val);
  6583. + }
  6584. + }
  6585. +
  6586. + if (cnt >= PAGE_SIZE)
  6587. + cnt = PAGE_SIZE - 1;
  6588. +
  6589. + return cnt;
  6590. +}
  6591. +
  6592. +static ssize_t rt5671_codec_store(struct device *dev,
  6593. + struct device_attribute *attr, const char *buf, size_t count)
  6594. +{
  6595. + struct i2c_client *client = to_i2c_client(dev);
  6596. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6597. + struct snd_soc_codec *codec = rt5671->codec;
  6598. + unsigned int val = 0, addr = 0;
  6599. + int i;
  6600. +
  6601. + pr_debug("register \"%s\" count=%d\n", buf, count);
  6602. + for (i = 0; i < count; i++) {
  6603. + if (*(buf+i) <= '9' && *(buf + i) >= '0')
  6604. + addr = (addr << 4) | (*(buf + i) - '0');
  6605. + else if (*(buf+i) <= 'f' && *(buf + i) >= 'a')
  6606. + addr = (addr << 4) | ((*(buf + i) - 'a')+0xa);
  6607. + else if (*(buf+i) <= 'F' && *(buf + i) >= 'A')
  6608. + addr = (addr << 4) | ((*(buf + i) - 'A')+0xa);
  6609. + else
  6610. + break;
  6611. + }
  6612. +
  6613. + for (i = i+1; i < count; i++) {
  6614. + if (*(buf+i) <= '9' && *(buf + i) >= '0')
  6615. + val = (val << 4) | (*(buf + i) - '0');
  6616. + else if (*(buf+i) <= 'f' && *(buf + i) >= 'a')
  6617. + val = (val << 4) | ((*(buf + i) - 'a')+0xa);
  6618. + else if (*(buf+i) <= 'F' && *(buf + i) >= 'A')
  6619. + val = (val << 4) | ((*(buf + i) - 'A')+0xa);
  6620. + else
  6621. + break;
  6622. + }
  6623. + pr_debug("addr=0x%x val=0x%x\n", addr, val);
  6624. + if (addr > RT5671_VENDOR_ID2 || val > 0xffff || val < 0)
  6625. + return count;
  6626. +
  6627. + if (i == count)
  6628. + pr_debug("0x%02x = 0x%04x\n", addr,
  6629. + snd_soc_read(codec, addr));
  6630. + else
  6631. + snd_soc_write(codec, addr, val);
  6632. +
  6633. + return count;
  6634. +}
  6635. +
  6636. +static DEVICE_ATTR(codec_reg, 0664, rt5671_codec_show, rt5671_codec_store);
  6637. +
  6638. +static ssize_t rt5671_codec_adb_show(struct device *dev,
  6639. + struct device_attribute *attr, char *buf)
  6640. +{
  6641. + struct i2c_client *client = to_i2c_client(dev);
  6642. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6643. + struct snd_soc_codec *codec = rt5671->codec;
  6644. + unsigned int val;
  6645. + int cnt = 0, i;
  6646. +
  6647. + for (i = 0; i < rt5671->adb_reg_num; i++) {
  6648. + if (cnt + RT5671_REG_DISP_LEN >= PAGE_SIZE)
  6649. + break;
  6650. +
  6651. + switch (rt5671->adb_reg_addr[i] & 0x30000) {
  6652. + case 0x10000:
  6653. + val = rt5671_index_read(codec, rt5671->adb_reg_addr[i] & 0xffff);
  6654. + break;
  6655. + case 0x20000:
  6656. + val = rt5671_dsp_read(codec, rt5671->adb_reg_addr[i] & 0xffff);
  6657. + break;
  6658. + default:
  6659. + val = snd_soc_read(codec, rt5671->adb_reg_addr[i] & 0xffff);
  6660. + }
  6661. +
  6662. + cnt += snprintf(buf + cnt, RT5671_REG_DISP_LEN, "%05x: %04x\n",
  6663. + rt5671->adb_reg_addr[i], val);
  6664. + }
  6665. +
  6666. + return cnt;
  6667. +}
  6668. +
  6669. +static ssize_t rt5671_codec_adb_store(struct device *dev,
  6670. + struct device_attribute *attr, const char *buf, size_t count)
  6671. +{
  6672. + struct i2c_client *client = to_i2c_client(dev);
  6673. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  6674. + struct snd_soc_codec *codec = rt5671->codec;
  6675. + unsigned int value = 0;
  6676. + int i = 2, j = 0;
  6677. +
  6678. + if (buf[0] == 'R' || buf[0] == 'r') {
  6679. + while (j < 0x100 && i < count) {
  6680. + rt5671->adb_reg_addr[j] = 0;
  6681. + value = 0;
  6682. + for (; i < count; i++) {
  6683. + if (*(buf + i) <= '9' && *(buf + i) >= '0')
  6684. + value = (value << 4) | (*(buf + i) - '0');
  6685. + else if (*(buf + i) <= 'f' && *(buf + i) >= 'a')
  6686. + value = (value << 4) | ((*(buf + i) - 'a')+0xa);
  6687. + else if (*(buf + i) <= 'F' && *(buf + i) >= 'A')
  6688. + value = (value << 4) | ((*(buf + i) - 'A')+0xa);
  6689. + else
  6690. + break;
  6691. + }
  6692. + i++;
  6693. +
  6694. + rt5671->adb_reg_addr[j] = value;
  6695. + j++;
  6696. + }
  6697. + rt5671->adb_reg_num = j;
  6698. + } else if (buf[0] == 'W' || buf[0] == 'w') {
  6699. + while (j < 0x100 && i < count) {
  6700. + /* Get address */
  6701. + rt5671->adb_reg_addr[j] = 0;
  6702. + value = 0;
  6703. + for (; i < count; i++) {
  6704. + if (*(buf + i) <= '9' && *(buf + i) >= '0')
  6705. + value = (value << 4) | (*(buf + i) - '0');
  6706. + else if (*(buf + i) <= 'f' && *(buf + i) >= 'a')
  6707. + value = (value << 4) | ((*(buf + i) - 'a')+0xa);
  6708. + else if (*(buf + i) <= 'F' && *(buf + i) >= 'A')
  6709. + value = (value << 4) | ((*(buf + i) - 'A')+0xa);
  6710. + else
  6711. + break;
  6712. + }
  6713. + i++;
  6714. + rt5671->adb_reg_addr[j] = value;
  6715. +
  6716. + /* Get value */
  6717. + rt5671->adb_reg_value[j] = 0;
  6718. + value = 0;
  6719. + for (; i < count; i++) {
  6720. + if (*(buf + i) <= '9' && *(buf + i) >= '0')
  6721. + value = (value << 4) | (*(buf + i) - '0');
  6722. + else if (*(buf + i) <= 'f' && *(buf + i) >= 'a')
  6723. + value = (value << 4) | ((*(buf + i) - 'a')+0xa);
  6724. + else if (*(buf + i) <= 'F' && *(buf + i) >= 'A')
  6725. + value = (value << 4) | ((*(buf + i) - 'A')+0xa);
  6726. + else
  6727. + break;
  6728. + }
  6729. + i++;
  6730. + rt5671->adb_reg_value[j] = value;
  6731. +
  6732. + j++;
  6733. + }
  6734. +
  6735. + rt5671->adb_reg_num = j;
  6736. +
  6737. + for (i = 0; i < rt5671->adb_reg_num; i++) {
  6738. + switch (rt5671->adb_reg_addr[i] & 0x30000) {
  6739. + case 0x10000:
  6740. + rt5671_index_write(codec,
  6741. + rt5671->adb_reg_addr[i] & 0xffff,
  6742. + rt5671->adb_reg_value[i]);
  6743. + break;
  6744. + case 0x20000:
  6745. + rt5671_dsp_write(codec,
  6746. + rt5671->adb_reg_addr[i] & 0xffff,
  6747. + rt5671->adb_reg_value[i]);
  6748. + break;
  6749. + default:
  6750. + snd_soc_write(codec,
  6751. + rt5671->adb_reg_addr[i] & 0xffff,
  6752. + rt5671->adb_reg_value[i]);
  6753. + }
  6754. + }
  6755. +
  6756. + }
  6757. +
  6758. + return count;
  6759. +}
  6760. +static DEVICE_ATTR(codec_reg_adb, 0664, rt5671_codec_adb_show, rt5671_codec_adb_store);
  6761. +
  6762. +static int rt5671_set_bias_level(struct snd_soc_codec *codec,
  6763. + enum snd_soc_bias_level level)
  6764. +{
  6765. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6766. + switch (level) {
  6767. + case SND_SOC_BIAS_ON:
  6768. + break;
  6769. +
  6770. + case SND_SOC_BIAS_PREPARE:
  6771. + snd_soc_update_bits(codec, RT5671_ADDA_CLK1,
  6772. + RT5671_I2S_PD1_MASK, RT5671_I2S_PD1_2);
  6773. + snd_soc_update_bits(codec, RT5671_CHARGE_PUMP,
  6774. + RT5671_OSW_L_MASK | RT5671_OSW_R_MASK,
  6775. + RT5671_OSW_L_DIS | RT5671_OSW_R_DIS);
  6776. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6777. + RT5671_LDO_SEL_MASK, 0x5);
  6778. + if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
  6779. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6780. + RT5671_PWR_VREF1 | RT5671_PWR_MB |
  6781. + RT5671_PWR_BG | RT5671_PWR_VREF2,
  6782. + RT5671_PWR_VREF1 | RT5671_PWR_MB |
  6783. + RT5671_PWR_BG | RT5671_PWR_VREF2);
  6784. + mdelay(10);
  6785. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6786. + RT5671_PWR_FV1 | RT5671_PWR_FV2,
  6787. + RT5671_PWR_FV1 | RT5671_PWR_FV2);
  6788. + snd_soc_update_bits(codec, RT5671_GEN_CTRL1, 0x1, 0x1);
  6789. + switch (rt5671->sysclk_src) {
  6790. + case RT5671_SCLK_S_MCLK:
  6791. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6792. + RT5671_SCLK_SRC_MASK,
  6793. + RT5671_SCLK_SRC_MCLK);
  6794. + break;
  6795. + case RT5671_SCLK_S_PLL1:
  6796. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6797. + RT5671_SCLK_SRC_MASK,
  6798. + RT5671_SCLK_SRC_PLL1);
  6799. + break;
  6800. + default:
  6801. + pr_err("Invalid sysclk_src %d, use MCLK\n",
  6802. + rt5671->sysclk_src);
  6803. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6804. + RT5671_SCLK_SRC_MASK,
  6805. + RT5671_SCLK_SRC_MCLK);
  6806. + break;
  6807. + }
  6808. +
  6809. + snd_soc_update_bits(codec, RT5671_MICBIAS,
  6810. + RT5671_PWR_CLK25M_MASK |
  6811. + RT5671_PWR_MB_MASK, 0);
  6812. + }
  6813. + break;
  6814. +
  6815. + case SND_SOC_BIAS_STANDBY:
  6816. +
  6817. + break;
  6818. +
  6819. + case SND_SOC_BIAS_OFF:
  6820. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  6821. + RT5671_SCLK_SRC_MASK, RT5671_SCLK_SRC_RCCLK);
  6822. + snd_soc_write(codec, RT5671_ADDA_CLK1, 0x7770);
  6823. + snd_soc_update_bits(codec, RT5671_MICBIAS,
  6824. + RT5671_PWR_CLK25M_MASK | RT5671_PWR_MB_MASK,
  6825. + RT5671_PWR_CLK25M_PU | RT5671_PWR_MB_PU);
  6826. + snd_soc_update_bits(codec, RT5671_GEN_CTRL1, 0x1, 0);
  6827. + snd_soc_write(codec, RT5671_PWR_DIG1, 0x0000);
  6828. + snd_soc_write(codec, RT5671_PWR_DIG2, 0x0001);
  6829. + snd_soc_write(codec, RT5671_PWR_VOL, 0x0000);
  6830. + snd_soc_write(codec, RT5671_PWR_MIXER, 0x0001);
  6831. + snd_soc_write(codec, RT5671_PWR_ANLG1, 0x2001);
  6832. + snd_soc_write(codec, RT5671_PWR_ANLG2, 0x0004);
  6833. + break;
  6834. +
  6835. + default:
  6836. + break;
  6837. + }
  6838. + codec->dapm.bias_level = level;
  6839. +
  6840. + return 0;
  6841. +}
  6842. +
  6843. +static int rt5671_probe(struct snd_soc_codec *codec)
  6844. +{
  6845. + struct rt5670_platform_data *pdata = dev_get_platdata(codec->dev);
  6846. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  6847. +#ifdef RTK_IOCTL
  6848. +#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
  6849. + struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
  6850. +#endif
  6851. +#endif
  6852. + int ret;
  6853. +
  6854. + pr_info("Codec driver version %s\n", VERSION);
  6855. +
  6856. + ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
  6857. + if (ret != 0) {
  6858. + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  6859. + return ret;
  6860. + }
  6861. + rt5671_reset(codec);
  6862. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6863. + RT5671_PWR_HP_L | RT5671_PWR_HP_R |
  6864. + RT5671_PWR_VREF2, RT5671_PWR_VREF2);
  6865. + msleep(100);
  6866. +
  6867. + rt5671_reset(codec);
  6868. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6869. + RT5671_PWR_VREF1 | RT5671_PWR_MB |
  6870. + RT5671_PWR_BG | RT5671_PWR_VREF2,
  6871. + RT5671_PWR_VREF1 | RT5671_PWR_MB |
  6872. + RT5671_PWR_BG | RT5671_PWR_VREF2);
  6873. + mdelay(10);
  6874. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6875. + RT5671_PWR_FV1 | RT5671_PWR_FV2,
  6876. + RT5671_PWR_FV1 | RT5671_PWR_FV2);
  6877. + /* DMIC */
  6878. + if (rt5671->dmic_en == RT5671_DMIC1) {
  6879. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1,
  6880. + RT5671_GP2_PIN_MASK, RT5671_GP2_PIN_DMIC1_SCL);
  6881. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  6882. + RT5671_DMIC_1L_LH_MASK | RT5671_DMIC_1R_LH_MASK,
  6883. + RT5671_DMIC_1L_LH_FALLING | RT5671_DMIC_1R_LH_RISING);
  6884. + } else if (rt5671->dmic_en == RT5671_DMIC2) {
  6885. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1,
  6886. + RT5671_GP2_PIN_MASK, RT5671_GP2_PIN_DMIC1_SCL);
  6887. + snd_soc_update_bits(codec, RT5671_DMIC_CTRL1,
  6888. + RT5671_DMIC_2L_LH_MASK | RT5671_DMIC_2R_LH_MASK,
  6889. + RT5671_DMIC_2L_LH_FALLING | RT5671_DMIC_2R_LH_RISING);
  6890. + }
  6891. +
  6892. + rt5671_reg_init(codec);
  6893. + /*for IRQ*/
  6894. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL1, 0x8000, 0x8000);
  6895. + snd_soc_update_bits(codec, RT5671_GPIO_CTRL2, 0x0004, 0x0004);
  6896. +
  6897. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1, RT5671_LDO_SEL_MASK, 0x1);
  6898. +
  6899. + rt5671->codec = codec;
  6900. + rt5671->combo_jack_en = true; /* enable combo jack */
  6901. +
  6902. + if (pdata)
  6903. + rt5671->pdata = *pdata;
  6904. + else
  6905. + pr_info("pdata = NULL\n");
  6906. +
  6907. + if (rt5671->pdata.in2_diff)
  6908. + snd_soc_update_bits(codec, RT5671_IN2,
  6909. + RT5671_IN_DF2, RT5671_IN_DF2);
  6910. + if (rt5671->pdata.in3_diff)
  6911. + snd_soc_update_bits(codec, RT5671_IN3_IN4,
  6912. + RT5671_IN_DF1, RT5671_IN_DF1);
  6913. +
  6914. + if (rt5671->pdata.in4_diff)
  6915. + snd_soc_update_bits(codec, RT5671_IN3_IN4,
  6916. + RT5671_IN_DF2, RT5671_IN_DF2);
  6917. +
  6918. + if (rt5671->pdata.jd_mode) {
  6919. + snd_soc_update_bits(codec, RT5671_PWR_ANLG1,
  6920. + RT5671_PWR_MB,
  6921. + RT5671_PWR_MB);
  6922. + snd_soc_update_bits(codec, RT5671_PWR_ANLG2,
  6923. + RT5671_PWR_JD1,
  6924. + RT5671_PWR_JD1);
  6925. + snd_soc_update_bits(codec, RT5671_IRQ_CTRL1,
  6926. + 0x0200, 0x0200);
  6927. + switch (rt5671->pdata.jd_mode) {
  6928. + case 1:
  6929. + snd_soc_update_bits(codec, RT5671_A_JD_CTRL1,
  6930. + 0x3, 0x0);
  6931. + break;
  6932. + case 2:
  6933. + snd_soc_update_bits(codec, RT5671_A_JD_CTRL1,
  6934. + 0x3, 0x1);
  6935. + break;
  6936. + case 3:
  6937. + snd_soc_update_bits(codec, RT5671_A_JD_CTRL1,
  6938. + 0x3, 0x2);
  6939. + break;
  6940. + default:
  6941. + break;
  6942. + }
  6943. + }
  6944. +
  6945. + snd_soc_add_codec_controls(codec, rt5671_snd_controls,
  6946. + ARRAY_SIZE(rt5671_snd_controls));
  6947. + snd_soc_dapm_new_controls(&codec->dapm, rt5671_dapm_widgets,
  6948. + ARRAY_SIZE(rt5671_dapm_widgets));
  6949. + snd_soc_dapm_add_routes(&codec->dapm, rt5671_dapm_routes,
  6950. + ARRAY_SIZE(rt5671_dapm_routes));
  6951. + rt5671_dsp_probe(codec);
  6952. +
  6953. +#ifdef RTK_IOCTL
  6954. +#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
  6955. + ioctl_ops->index_write = rt5671_index_write;
  6956. + ioctl_ops->index_read = rt5671_index_read;
  6957. + ioctl_ops->index_update_bits = rt5671_index_update_bits;
  6958. + ioctl_ops->ioctl_common = rt5671_ioctl_common;
  6959. + realtek_ce_init_hwdep(codec);
  6960. +#endif
  6961. +#endif
  6962. +
  6963. + ret = device_create_file(codec->dev, &dev_attr_index_reg);
  6964. + if (ret != 0) {
  6965. + dev_err(codec->dev,
  6966. + "Failed to create index_reg sysfs files: %d\n", ret);
  6967. + return ret;
  6968. + }
  6969. +
  6970. + ret = device_create_file(codec->dev, &dev_attr_codec_reg);
  6971. + if (ret != 0) {
  6972. + dev_err(codec->dev,
  6973. + "Failed to create codex_reg sysfs files: %d\n", ret);
  6974. + return ret;
  6975. + }
  6976. +
  6977. + ret = device_create_file(codec->dev, &dev_attr_codec_reg_adb);
  6978. + if (ret != 0) {
  6979. + dev_err(codec->dev,
  6980. + "Failed to create codec_reg_adb sysfs files: %d\n", ret);
  6981. + return ret;
  6982. + }
  6983. +
  6984. + rt5671->jack_type = 0;
  6985. + if (rt5671->pdata.codec_gpio != -1) {
  6986. + rt5671->hp_gpio.gpio = rt5671->pdata.codec_gpio;
  6987. + rt5671->hp_gpio.name = "headphone detect";
  6988. + rt5671->hp_gpio.report = SND_JACK_HEADSET |
  6989. + SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2;
  6990. + rt5671->hp_gpio.debounce_time = 150,
  6991. + rt5671->hp_gpio.wake = true,
  6992. + rt5671->hp_gpio.jack_status_check = rt5671_irq_detection,
  6993. + snd_soc_jack_new(codec, rt5671->hp_gpio.name,
  6994. + rt5671->hp_gpio.report,
  6995. + &rt5671->hp_jack);
  6996. + snd_soc_jack_add_gpios(&rt5671->hp_jack, 1,
  6997. + &rt5671->hp_gpio);
  6998. + }
  6999. +
  7000. + rt5671_set_bias_level(codec, SND_SOC_BIAS_OFF);
  7001. +
  7002. + return 0;
  7003. +}
  7004. +
  7005. +static int rt5671_remove(struct snd_soc_codec *codec)
  7006. +{
  7007. + struct rt5671_priv *rt5671 = snd_soc_codec_get_drvdata(codec);
  7008. +
  7009. + rt5671_set_bias_level(codec, SND_SOC_BIAS_OFF);
  7010. + snd_soc_jack_free_gpios(&rt5671->hp_jack, 1, &rt5671->hp_gpio);
  7011. + return 0;
  7012. +}
  7013. +
  7014. +#ifdef CONFIG_PM
  7015. +static int rt5671_suspend(struct snd_soc_codec *codec)
  7016. +{
  7017. + rt5671_dsp_suspend(codec);
  7018. + snd_soc_update_bits(codec, RT5671_GLB_CLK,
  7019. + RT5671_SCLK_SRC_MASK, RT5671_SCLK_SRC_MCLK);
  7020. + snd_soc_write(codec, RT5671_MICBIAS, 0x0000);
  7021. + snd_soc_write(codec, RT5671_PWR_DIG1, 0x0000);
  7022. + snd_soc_write(codec, RT5671_PWR_DIG2, 0x0000);
  7023. + snd_soc_write(codec, RT5671_PWR_VOL, 0x0000);
  7024. + snd_soc_write(codec, RT5671_PWR_MIXER, 0x0000);
  7025. + snd_soc_write(codec, RT5671_PWR_ANLG1, 0x0001);
  7026. + snd_soc_write(codec, RT5671_PWR_ANLG2, 0x0000);
  7027. + return 0;
  7028. +}
  7029. +
  7030. +static int rt5671_resume(struct snd_soc_codec *codec)
  7031. +{
  7032. + codec->cache_only = false;
  7033. + codec->cache_sync = 1;
  7034. + snd_soc_cache_sync(codec);
  7035. + rt5671_index_sync(codec);
  7036. + rt5671_dsp_resume(codec);
  7037. + rt5671_set_bias_level(codec, SND_SOC_BIAS_OFF);
  7038. + return 0;
  7039. +}
  7040. +#else
  7041. +#define rt5671_suspend NULL
  7042. +#define rt5671_resume NULL
  7043. +#endif
  7044. +
  7045. +#define RT5671_STEREO_RATES SNDRV_PCM_RATE_8000_96000
  7046. +#define RT5671_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  7047. + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  7048. +
  7049. +struct snd_soc_dai_ops rt5671_aif_dai_ops = {
  7050. + .hw_params = rt5671_hw_params,
  7051. + .prepare = rt5671_prepare,
  7052. + .set_fmt = rt5671_set_dai_fmt,
  7053. + .set_sysclk = rt5671_set_dai_sysclk,
  7054. + .set_pll = rt5671_set_dai_pll,
  7055. + .shutdown = rt5671_shutdown,
  7056. +};
  7057. +
  7058. +struct snd_soc_dai_driver rt5671_dai[] = {
  7059. + {
  7060. + .name = "rt5671-aif1",
  7061. + .id = RT5671_AIF1,
  7062. + .playback = {
  7063. + .stream_name = "AIF1 Playback",
  7064. + .channels_min = 1,
  7065. + .channels_max = 2,
  7066. + .rates = RT5671_STEREO_RATES,
  7067. + .formats = RT5671_FORMATS,
  7068. + },
  7069. + .capture = {
  7070. + .stream_name = "AIF1 Capture",
  7071. + .channels_min = 1,
  7072. + .channels_max = 2,
  7073. + .rates = RT5671_STEREO_RATES,
  7074. + .formats = RT5671_FORMATS,
  7075. + },
  7076. + .ops = &rt5671_aif_dai_ops,
  7077. + .symmetric_rates = 1,
  7078. + },
  7079. + {
  7080. + .name = "rt5671-aif2",
  7081. + .id = RT5671_AIF2,
  7082. + .playback = {
  7083. + .stream_name = "AIF2 Playback",
  7084. + .channels_min = 1,
  7085. + .channels_max = 2,
  7086. + .rates = RT5671_STEREO_RATES,
  7087. + .formats = RT5671_FORMATS,
  7088. + },
  7089. + .capture = {
  7090. + .stream_name = "AIF2 Capture",
  7091. + .channels_min = 1,
  7092. + .channels_max = 2,
  7093. + .rates = RT5671_STEREO_RATES,
  7094. + .formats = RT5671_FORMATS,
  7095. + },
  7096. + .ops = &rt5671_aif_dai_ops,
  7097. + .symmetric_rates = 1,
  7098. + },
  7099. + {
  7100. + .name = "rt5671-aif3",
  7101. + .id = RT5671_AIF3,
  7102. + .playback = {
  7103. + .stream_name = "AIF3 Playback",
  7104. + .channels_min = 1,
  7105. + .channels_max = 2,
  7106. + .rates = RT5671_STEREO_RATES,
  7107. + .formats = RT5671_FORMATS,
  7108. + },
  7109. + .capture = {
  7110. + .stream_name = "AIF3 Capture",
  7111. + .channels_min = 1,
  7112. + .channels_max = 2,
  7113. + .rates = RT5671_STEREO_RATES,
  7114. + .formats = RT5671_FORMATS,
  7115. + },
  7116. + .ops = &rt5671_aif_dai_ops,
  7117. + .symmetric_rates = 1,
  7118. + },
  7119. + {
  7120. + .name = "rt5671-aif4",
  7121. + .id = RT5671_AIF4,
  7122. + .playback = {
  7123. + .stream_name = "AIF4 Playback",
  7124. + .channels_min = 1,
  7125. + .channels_max = 2,
  7126. + .rates = RT5671_STEREO_RATES,
  7127. + .formats = RT5671_FORMATS,
  7128. + },
  7129. + .capture = {
  7130. + .stream_name = "AIF4 Capture",
  7131. + .channels_min = 1,
  7132. + .channels_max = 2,
  7133. + .rates = RT5671_STEREO_RATES,
  7134. + .formats = RT5671_FORMATS,
  7135. + },
  7136. + .ops = &rt5671_aif_dai_ops,
  7137. + .symmetric_rates = 1,
  7138. + },
  7139. +
  7140. +};
  7141. +
  7142. +static struct snd_soc_codec_driver soc_codec_dev_rt5671 = {
  7143. + .probe = rt5671_probe,
  7144. + .remove = rt5671_remove,
  7145. + .suspend = rt5671_suspend,
  7146. + .resume = rt5671_resume,
  7147. + .set_bias_level = rt5671_set_bias_level,
  7148. + .idle_bias_off = true,
  7149. + .reg_cache_size = RT5671_VENDOR_ID2 + 1,
  7150. + .reg_word_size = sizeof(u16),
  7151. + .reg_cache_default = rt5671_reg,
  7152. + .volatile_register = rt5671_volatile_register,
  7153. + .readable_register = rt5671_readable_register,
  7154. + .reg_cache_step = 1,
  7155. +};
  7156. +
  7157. +static const struct i2c_device_id rt5671_i2c_id[] = {
  7158. + { "rt5671", 0 },
  7159. + { }
  7160. +};
  7161. +MODULE_DEVICE_TABLE(i2c, rt5671_i2c_id);
  7162. +
  7163. +static int rt5671_i2c_probe(struct i2c_client *i2c,
  7164. + const struct i2c_device_id *id)
  7165. +{
  7166. + struct rt5671_priv *rt5671;
  7167. + int ret;
  7168. +
  7169. + pr_debug("enter %s\n", __func__);
  7170. + rt5671 = kzalloc(sizeof(struct rt5671_priv), GFP_KERNEL);
  7171. + if (NULL == rt5671)
  7172. + return -ENOMEM;
  7173. +
  7174. + i2c_set_clientdata(i2c, rt5671);
  7175. +
  7176. + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5671,
  7177. + rt5671_dai, ARRAY_SIZE(rt5671_dai));
  7178. + if (ret < 0)
  7179. + kfree(rt5671);
  7180. +
  7181. + return ret;
  7182. +}
  7183. +
  7184. +static int rt5671_i2c_remove(struct i2c_client *i2c)
  7185. +{
  7186. + snd_soc_unregister_codec(&i2c->dev);
  7187. + kfree(i2c_get_clientdata(i2c));
  7188. + return 0;
  7189. +}
  7190. +
  7191. +void rt5671_i2c_shutdown(struct i2c_client *client)
  7192. +{
  7193. + struct rt5671_priv *rt5671 = i2c_get_clientdata(client);
  7194. + struct snd_soc_codec *codec = rt5671->codec;
  7195. +
  7196. + pr_debug("enter %s\n", __func__);
  7197. + if (codec != NULL)
  7198. + rt5671_set_bias_level(codec, SND_SOC_BIAS_OFF);
  7199. +}
  7200. +
  7201. +struct i2c_driver rt5671_i2c_driver = {
  7202. + .driver = {
  7203. + .name = "rt5671",
  7204. + .owner = THIS_MODULE,
  7205. + },
  7206. + .probe = rt5671_i2c_probe,
  7207. + .remove = rt5671_i2c_remove,
  7208. + .shutdown = rt5671_i2c_shutdown,
  7209. + .id_table = rt5671_i2c_id,
  7210. +};
  7211. +
  7212. +static int __init rt5671_modinit(void)
  7213. +{
  7214. + return i2c_add_driver(&rt5671_i2c_driver);
  7215. +}
  7216. +module_init(rt5671_modinit);
  7217. +
  7218. +static void __exit rt5671_modexit(void)
  7219. +{
  7220. + i2c_del_driver(&rt5671_i2c_driver);
  7221. +}
  7222. +module_exit(rt5671_modexit);
  7223. +
  7224. +MODULE_DESCRIPTION("ASoC RT5671 driver");
  7225. +MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  7226. +MODULE_LICENSE("GPL");
  7227. diff --git a/sound/soc/codecs/rt5671.h b/sound/soc/codecs/rt5671.h
  7228. new file mode 100644
  7229. index 0000000..36e76cd
  7230. --- /dev/null
  7231. +++ b/sound/soc/codecs/rt5671.h
  7232. @@ -0,0 +1,2091 @@
  7233. +/*
  7234. + * rt5671.h -- RT5671 ALSA SoC audio driver
  7235. + *
  7236. + * Copyright 2011 Realtek Microelectronics
  7237. + * Copyright (C) 2016 XiaoMi, Inc.
  7238. + * Author: Johnny Hsu <johnnyhsu@realtek.com>
  7239. + *
  7240. + * This program is free software; you can redistribute it and/or modify
  7241. + * it under the terms of the GNU General Public License version 2 as
  7242. + * published by the Free Software Foundation.
  7243. + */
  7244. +
  7245. +#ifndef __RT5671_H__
  7246. +#define __RT5671_H__
  7247. +
  7248. +#include <sound/rt5670.h>
  7249. +
  7250. +/* Info */
  7251. +#define RT5671_RESET 0x00
  7252. +#define RT5671_VENDOR_ID 0xfd
  7253. +#define RT5671_VENDOR_ID1 0xfe
  7254. +#define RT5671_VENDOR_ID2 0xff
  7255. +/* dummy register */
  7256. +#define RT5671_DUMMY_CTRL 0x01
  7257. +/* I/O - Output */
  7258. +#define RT5671_HP_VOL 0x02
  7259. +#define RT5671_LOUT1 0x03
  7260. +#define RT5671_MONO_OUT 0x04
  7261. +/* I/O - Input */
  7262. +#define RT5671_CJ_CTRL1 0x0a
  7263. +#define RT5671_CJ_CTRL2 0x0b
  7264. +#define RT5671_CJ_CTRL3 0x0c
  7265. +#define RT5671_IN2 0x0d
  7266. +#define RT5671_IN3_IN4 0x0e
  7267. +#define RT5671_INL1_INR1_VOL 0x0f
  7268. +/* I/O - ADC/DAC/DMIC */
  7269. +#define RT5671_SIDETONE_CTRL 0x18
  7270. +#define RT5671_DAC1_DIG_VOL 0x19
  7271. +#define RT5671_DAC2_DIG_VOL 0x1a
  7272. +#define RT5671_DAC_CTRL 0x1b
  7273. +#define RT5671_STO1_ADC_DIG_VOL 0x1c
  7274. +#define RT5671_MONO_ADC_DIG_VOL 0x1d
  7275. +#define RT5671_ADC_BST_VOL1 0x1e
  7276. +#define RT5671_STO2_ADC_DIG_VOL 0x1f
  7277. +/* Mixer - D-D */
  7278. +#define RT5671_ADC_BST_VOL2 0x20
  7279. +#define RT5671_STO2_ADC_MIXER 0x26
  7280. +#define RT5671_STO1_ADC_MIXER 0x27
  7281. +#define RT5671_MONO_ADC_MIXER 0x28
  7282. +#define RT5671_AD_DA_MIXER 0x29
  7283. +#define RT5671_STO_DAC_MIXER 0x2a
  7284. +#define RT5671_MONO_DAC_MIXER 0x2b
  7285. +#define RT5671_DIG_MIXER 0x2c
  7286. +#define RT5671_DSP_PATH1 0x2d
  7287. +#define RT5671_DSP_PATH2 0x2e
  7288. +#define RT5671_DIG_INF1_DATA 0x2f
  7289. +#define RT5671_DIG_INF2_DATA 0x30
  7290. +/* Mixer - PDM */
  7291. +#define RT5671_PDM_OUT_CTRL 0x31
  7292. +#define RT5671_PDM_DATA_CTRL1 0x32
  7293. +#define RT5671_PDM1_DATA_CTRL2 0x33
  7294. +#define RT5671_PDM1_DATA_CTRL3 0x34
  7295. +#define RT5671_PDM1_DATA_CTRL4 0x35
  7296. +#define RT5671_PDM2_DATA_CTRL2 0x36
  7297. +#define RT5671_PDM2_DATA_CTRL3 0x37
  7298. +#define RT5671_PDM2_DATA_CTRL4 0x38
  7299. +/* Mixer - ADC */
  7300. +#define RT5671_REC_L1_MIXER 0x3b
  7301. +#define RT5671_REC_L2_MIXER 0x3c
  7302. +#define RT5671_REC_R1_MIXER 0x3d
  7303. +#define RT5671_REC_R2_MIXER 0x3e
  7304. +#define RT5671_REC_MONO1_MIXER 0x3f
  7305. +#define RT5671_REC_MONO2_MIXER 0x40
  7306. +/* Mixer - DAC */
  7307. +#define RT5671_HPO_MIXER 0x45
  7308. +#define RT5671_MONO_MIXER 0x4c
  7309. +#define RT5671_OUT_L1_MIXER 0x4f
  7310. +#define RT5671_OUT_R1_MIXER 0x52
  7311. +#define RT5671_LOUT_MIXER 0x53
  7312. +/* Power */
  7313. +#define RT5671_PWR_DIG1 0x61
  7314. +#define RT5671_PWR_DIG2 0x62
  7315. +#define RT5671_PWR_ANLG1 0x63
  7316. +#define RT5671_PWR_ANLG2 0x64
  7317. +#define RT5671_PWR_MIXER 0x65
  7318. +#define RT5671_PWR_VOL 0x66
  7319. +/* Private Register Control */
  7320. +#define RT5671_PRIV_INDEX 0x6a
  7321. +#define RT5671_PRIV_DATA 0x6c
  7322. +/* Format - ADC/DAC */
  7323. +#define RT5671_I2S4_SDP 0x6f
  7324. +#define RT5671_I2S1_SDP 0x70
  7325. +#define RT5671_I2S2_SDP 0x71
  7326. +#define RT5671_I2S3_SDP 0x72
  7327. +#define RT5671_ADDA_CLK1 0x73
  7328. +#define RT5671_ADDA_HPF 0x74
  7329. +#define RT5671_DMIC_CTRL1 0x75
  7330. +#define RT5671_DMIC_CTRL2 0x76
  7331. +/* Format - TDM Control */
  7332. +#define RT5671_TDM_CTRL_1 0x77
  7333. +#define RT5671_TDM_CTRL_2 0x78
  7334. +#define RT5671_TDM_CTRL_3 0x79
  7335. +
  7336. +/* Function - Analog */
  7337. +#define RT5671_DSP_CLK 0x7f
  7338. +#define RT5671_GLB_CLK 0x80
  7339. +#define RT5671_PLL_CTRL1 0x81
  7340. +#define RT5671_PLL_CTRL2 0x82
  7341. +#define RT5671_ASRC_1 0x83
  7342. +#define RT5671_ASRC_2 0x84
  7343. +#define RT5671_ASRC_3 0x85
  7344. +#define RT5671_ASRC_I2S1 0x87
  7345. +#define RT5671_ASRC_I2S2 0x88
  7346. +#define RT5671_ASRC_I2S3 0x89
  7347. +#define RT5671_ASRC_4 0x8a
  7348. +#define RT5671_ASRC_5 0x8c
  7349. +#define RT5671_DEPOP_M1 0x8e
  7350. +#define RT5671_DEPOP_M2 0x8f
  7351. +#define RT5671_DEPOP_M3 0x90
  7352. +#define RT5671_CHARGE_PUMP 0x91
  7353. +#define RT5671_MICBIAS 0x93
  7354. +#define RT5671_A_JD_CTRL1 0x94
  7355. +#define RT5671_A_JD_CTRL2 0x95
  7356. +#define RT5671_VAD_CTRL1 0x9a
  7357. +#define RT5671_VAD_CTRL2 0x9b
  7358. +#define RT5671_VAD_CTRL3 0x9c
  7359. +#define RT5671_VAD_CTRL4 0x9d
  7360. +#define RT5671_VAD_CTRL5 0x9e
  7361. +/* Function - Digital */
  7362. +#define RT5671_ADC_EQ_CTRL1 0xae
  7363. +#define RT5671_ADC_EQ_CTRL2 0xaf
  7364. +#define RT5671_EQ_CTRL1 0xb0
  7365. +#define RT5671_EQ_CTRL2 0xb1
  7366. +#define RT5671_ALC_DRC_CTRL1 0xb2
  7367. +#define RT5671_ALC_DRC_CTRL2 0xb3
  7368. +#define RT5671_ALC_CTRL_1 0xb4
  7369. +#define RT5671_ALC_CTRL_2 0xb5
  7370. +#define RT5671_ALC_CTRL_3 0xb6
  7371. +#define RT5671_ALC_CTRL_4 0xb7
  7372. +#define RT5671_JD_CTRL1 0xbb
  7373. +#define RT5671_JD_CTRL2 0xbc
  7374. +#define RT5671_IRQ_CTRL1 0xbd
  7375. +#define RT5671_IRQ_CTRL2 0xbe
  7376. +#define RT5671_IRQ_CTRL3 0xbf
  7377. +#define RT5671_GPIO_CTRL1 0xc0
  7378. +#define RT5671_GPIO_CTRL2 0xc1
  7379. +#define RT5671_GPIO_CTRL3 0xc2
  7380. +#define RT5671_SCRABBLE_FUN 0xcd
  7381. +#define RT5671_SCRABBLE_CTRL 0xce
  7382. +#define RT5671_BASE_BACK 0xcf
  7383. +#define RT5671_MP3_PLUS1 0xd0
  7384. +#define RT5671_MP3_PLUS2 0xd1
  7385. +#define RT5671_ADJ_HPF1 0xd3
  7386. +#define RT5671_ADJ_HPF2 0xd4
  7387. +#define RT5671_HP_CALIB_AMP_DET 0xd6
  7388. +#define RT5671_SV_ZCD1 0xd9
  7389. +#define RT5671_SV_ZCD2 0xda
  7390. +#define RT5671_IL_CMD1 0xdb
  7391. +#define RT5671_IL_CMD2 0xdc
  7392. +#define RT5671_IL_CMD3 0xdd
  7393. +#define RT5671_DRC_HL_CTRL1 0xe6
  7394. +#define RT5671_DRC_HL_CTRL2 0xe7
  7395. +#define RT5671_ADC_MONO_HP_CTRL1 0xec
  7396. +#define RT5671_ADC_MONO_HP_CTRL2 0xed
  7397. +#define RT5671_ADC_STO2_HP_CTRL1 0xee
  7398. +#define RT5671_ADC_STO2_HP_CTRL2 0xef
  7399. +#define RT5671_JD_CTRL3 0xf8
  7400. +#define RT5671_JD_CTRL4 0xf9
  7401. +/* General Control */
  7402. +#define RT5671_GEN_CTRL1 0xfa
  7403. +#define RT5671_GEN_CTRL2 0xfb
  7404. +#define RT5671_GEN_CTRL3 0xfc
  7405. +
  7406. +
  7407. +/* Index of Codec Private Register definition */
  7408. +#define RT5671_DIG_VOL 0x00
  7409. +#define RT5671_PR_ALC_CTRL_1 0x01
  7410. +#define RT5671_PR_ALC_CTRL_2 0x02
  7411. +#define RT5671_PR_ALC_CTRL_3 0x03
  7412. +#define RT5671_PR_ALC_CTRL_4 0x04
  7413. +#define RT5671_PR_ALC_CTRL_5 0x05
  7414. +#define RT5671_PR_ALC_CTRL_6 0x06
  7415. +#define RT5671_BIAS_CUR1 0x12
  7416. +#define RT5671_BIAS_CUR3 0x14
  7417. +#define RT5671_CLSD_INT_REG1 0x1c
  7418. +#define RT5671_MAMP_INT_REG2 0x37
  7419. +#define RT5671_CHOP_DAC_ADC 0x3d
  7420. +#define RT5671_MIXER_INT_REG 0x3f
  7421. +#define RT5671_3D_SPK 0x63
  7422. +#define RT5671_WND_1 0x6c
  7423. +#define RT5671_WND_2 0x6d
  7424. +#define RT5671_WND_3 0x6e
  7425. +#define RT5671_WND_4 0x6f
  7426. +#define RT5671_WND_5 0x70
  7427. +#define RT5671_WND_8 0x73
  7428. +#define RT5671_DIP_SPK_INF 0x75
  7429. +#define RT5671_HP_DCC_INT1 0x77
  7430. +#define RT5671_EQ_BW_LOP 0xa0
  7431. +#define RT5671_EQ_GN_LOP 0xa1
  7432. +#define RT5671_EQ_FC_BP1 0xa2
  7433. +#define RT5671_EQ_BW_BP1 0xa3
  7434. +#define RT5671_EQ_GN_BP1 0xa4
  7435. +#define RT5671_EQ_FC_BP2 0xa5
  7436. +#define RT5671_EQ_BW_BP2 0xa6
  7437. +#define RT5671_EQ_GN_BP2 0xa7
  7438. +#define RT5671_EQ_FC_BP3 0xa8
  7439. +#define RT5671_EQ_BW_BP3 0xa9
  7440. +#define RT5671_EQ_GN_BP3 0xaa
  7441. +#define RT5671_EQ_FC_BP4 0xab
  7442. +#define RT5671_EQ_BW_BP4 0xac
  7443. +#define RT5671_EQ_GN_BP4 0xad
  7444. +#define RT5671_EQ_FC_HIP1 0xae
  7445. +#define RT5671_EQ_GN_HIP1 0xaf
  7446. +#define RT5671_EQ_FC_HIP2 0xb0
  7447. +#define RT5671_EQ_BW_HIP2 0xb1
  7448. +#define RT5671_EQ_GN_HIP2 0xb2
  7449. +#define RT5671_EQ_PRE_VOL 0xb3
  7450. +#define RT5671_EQ_PST_VOL 0xb4
  7451. +
  7452. +
  7453. +/* global definition */
  7454. +#define RT5671_L_MUTE (0x1 << 15)
  7455. +#define RT5671_L_MUTE_SFT 15
  7456. +#define RT5671_VOL_L_MUTE (0x1 << 14)
  7457. +#define RT5671_VOL_L_SFT 14
  7458. +#define RT5671_R_MUTE (0x1 << 7)
  7459. +#define RT5671_R_MUTE_SFT 7
  7460. +#define RT5671_VOL_R_MUTE (0x1 << 6)
  7461. +#define RT5671_VOL_R_SFT 6
  7462. +#define RT5671_L_VOL_MASK (0x3f << 8)
  7463. +#define RT5671_L_VOL_SFT 8
  7464. +#define RT5671_R_VOL_MASK (0x3f)
  7465. +#define RT5671_R_VOL_SFT 0
  7466. +
  7467. +/* Combo Jack Control 1 (0x0a) */
  7468. +#define RT5671_CBJ_BST1_MASK (0xf << 12)
  7469. +#define RT5671_CBJ_BST1_SFT (12)
  7470. +#define RT5671_CBJ_JD_HP_EN (0x1 << 9)
  7471. +#define RT5671_CBJ_JD_MIC_EN (0x1 << 8)
  7472. +#define RT5671_CBJ_BST1_EN (0x1 << 2)
  7473. +
  7474. +/* Combo Jack Control 1 (0x0b) */
  7475. +#define RT5671_CBJ_MN_JD (0x1 << 12)
  7476. +#define RT5671_CAPLESS_EN (0x1 << 11)
  7477. +#define RT5671_CBJ_DET_MODE (0x1 << 7)
  7478. +
  7479. +/* IN1 and IN2 Control (0x0d) */
  7480. +/* IN3 and IN4 Control (0x0e) */
  7481. +#define RT5671_BST_MASK1 (0xf<<12)
  7482. +#define RT5671_BST_SFT1 12
  7483. +#define RT5671_BST_MASK2 (0xf<<8)
  7484. +#define RT5671_BST_SFT2 8
  7485. +#define RT5671_IN_DF1 (0x1 << 7)
  7486. +#define RT5671_IN_SFT1 7
  7487. +#define RT5671_IN_DF2 (0x1 << 6)
  7488. +#define RT5671_IN_SFT2 6
  7489. +
  7490. +/* INL and INR Volume Control (0x0f) */
  7491. +#define RT5671_INL_SEL_MASK (0x1 << 15)
  7492. +#define RT5671_INL_SEL_SFT 15
  7493. +#define RT5671_INL_SEL_IN4P (0x0 << 15)
  7494. +#define RT5671_INL_SEL_MONOP (0x1 << 15)
  7495. +#define RT5671_INL_VOL_MASK (0x1f << 8)
  7496. +#define RT5671_INL_VOL_SFT 8
  7497. +#define RT5671_INR_SEL_MASK (0x1 << 7)
  7498. +#define RT5671_INR_SEL_SFT 7
  7499. +#define RT5671_INR_SEL_IN4N (0x0 << 7)
  7500. +#define RT5671_INR_SEL_MONON (0x1 << 7)
  7501. +#define RT5671_INR_VOL_MASK (0x1f)
  7502. +#define RT5671_INR_VOL_SFT 0
  7503. +
  7504. +/* Sidetone Control (0x18) */
  7505. +#define RT5671_ST_SEL_MASK (0x7 << 9)
  7506. +#define RT5671_ST_SEL_SFT 9
  7507. +#define RT5671_M_ST_DACR2 (0x1 << 8)
  7508. +#define RT5671_M_ST_DACR2_SFT 8
  7509. +#define RT5671_M_ST_DACL2 (0x1 << 7)
  7510. +#define RT5671_M_ST_DACL2_SFT 7
  7511. +#define RT5671_ST_EN (0x1 << 6)
  7512. +#define RT5671_ST_EN_SFT 6
  7513. +
  7514. +/* DAC1 Digital Volume (0x19) */
  7515. +#define RT5671_DAC_L1_VOL_MASK (0xff << 8)
  7516. +#define RT5671_DAC_L1_VOL_SFT 8
  7517. +#define RT5671_DAC_R1_VOL_MASK (0xff)
  7518. +#define RT5671_DAC_R1_VOL_SFT 0
  7519. +
  7520. +/* DAC2 Digital Volume (0x1a) */
  7521. +#define RT5671_DAC_L2_VOL_MASK (0xff << 8)
  7522. +#define RT5671_DAC_L2_VOL_SFT 8
  7523. +#define RT5671_DAC_R2_VOL_MASK (0xff)
  7524. +#define RT5671_DAC_R2_VOL_SFT 0
  7525. +
  7526. +/* DAC2 Control (0x1b) */
  7527. +#define RT5671_M_DAC_L2_VOL (0x1 << 13)
  7528. +#define RT5671_M_DAC_L2_VOL_SFT 13
  7529. +#define RT5671_M_DAC_R2_VOL (0x1 << 12)
  7530. +#define RT5671_M_DAC_R2_VOL_SFT 12
  7531. +#define RT5671_DAC2_L_SEL_MASK (0x7 << 4)
  7532. +#define RT5671_DAC2_L_SEL_SFT 4
  7533. +#define RT5671_DAC2_R_SEL_MASK (0x7 << 0)
  7534. +#define RT5671_DAC2_R_SEL_SFT 0
  7535. +
  7536. +/* ADC Digital Volume Control (0x1c) */
  7537. +#define RT5671_ADC_L_VOL_MASK (0x7f << 8)
  7538. +#define RT5671_ADC_L_VOL_SFT 8
  7539. +#define RT5671_ADC_R_VOL_MASK (0x7f)
  7540. +#define RT5671_ADC_R_VOL_SFT 0
  7541. +
  7542. +/* Mono ADC Digital Volume Control (0x1d) */
  7543. +#define RT5671_MONO_ADC_L_VOL_MASK (0x7f << 8)
  7544. +#define RT5671_MONO_ADC_L_VOL_SFT 8
  7545. +#define RT5671_MONO_ADC_R_VOL_MASK (0x7f)
  7546. +#define RT5671_MONO_ADC_R_VOL_SFT 0
  7547. +
  7548. +/* ADC Boost Volume Control (0x1e) */
  7549. +#define RT5671_STO1_ADC_L_BST_MASK (0x3 << 14)
  7550. +#define RT5671_STO1_ADC_L_BST_SFT 14
  7551. +#define RT5671_STO1_ADC_R_BST_MASK (0x3 << 12)
  7552. +#define RT5671_STO1_ADC_R_BST_SFT 12
  7553. +#define RT5671_STO1_ADC_COMP_MASK (0x3 << 10)
  7554. +#define RT5671_STO1_ADC_COMP_SFT 10
  7555. +#define RT5671_STO2_ADC_L_BST_MASK (0x3 << 8)
  7556. +#define RT5671_STO2_ADC_L_BST_SFT 8
  7557. +#define RT5671_STO2_ADC_R_BST_MASK (0x3 << 6)
  7558. +#define RT5671_STO2_ADC_R_BST_SFT 6
  7559. +#define RT5671_STO2_ADC_COMP_MASK (0x3 << 4)
  7560. +#define RT5671_STO2_ADC_COMP_SFT 4
  7561. +
  7562. +/* Stereo2 ADC Mixer Control (0x26) */
  7563. +#define RT5671_STO2_ADC_SRC_MASK (0x1 << 15)
  7564. +#define RT5671_STO2_ADC_SRC_SFT 15
  7565. +
  7566. +/* Stereo ADC Mixer Control (0x26 0x27) */
  7567. +#define RT5671_M_ADC_L1 (0x1 << 14)
  7568. +#define RT5671_M_ADC_L1_SFT 14
  7569. +#define RT5671_M_ADC_L2 (0x1 << 13)
  7570. +#define RT5671_M_ADC_L2_SFT 13
  7571. +#define RT5671_ADC_1_SRC_MASK (0x1 << 12)
  7572. +#define RT5671_ADC_1_SRC_SFT 12
  7573. +#define RT5671_ADC_1_SRC_ADC (0x1 << 12)
  7574. +#define RT5671_ADC_1_SRC_DACMIX (0x0 << 12)
  7575. +#define RT5671_ADC_2_SRC_MASK (0x1 << 11)
  7576. +#define RT5671_ADC_2_SRC_SFT 11
  7577. +#define RT5671_ADC_SRC_MASK (0x1 << 10)
  7578. +#define RT5671_ADC_SRC_SFT 10
  7579. +#define RT5671_DMIC_SRC_MASK (0x3 << 8)
  7580. +#define RT5671_DMIC_SRC_SFT 8
  7581. +#define RT5671_M_ADC_R1 (0x1 << 6)
  7582. +#define RT5671_M_ADC_R1_SFT 6
  7583. +#define RT5671_M_ADC_R2 (0x1 << 5)
  7584. +#define RT5671_M_ADC_R2_SFT 5
  7585. +#define RT5671_DMIC3_SRC_MASK (0x1 << 1)
  7586. +#define RT5671_DMIC3_SRC_SFT 0
  7587. +
  7588. +/* Mono ADC Mixer Control (0x28) */
  7589. +#define RT5671_M_MONO_ADC_L1 (0x1 << 14)
  7590. +#define RT5671_M_MONO_ADC_L1_SFT 14
  7591. +#define RT5671_M_MONO_ADC_L2 (0x1 << 13)
  7592. +#define RT5671_M_MONO_ADC_L2_SFT 13
  7593. +#define RT5671_MONO_ADC_L1_SRC_MASK (0x1 << 12)
  7594. +#define RT5671_MONO_ADC_L1_SRC_SFT 12
  7595. +#define RT5671_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
  7596. +#define RT5671_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
  7597. +#define RT5671_MONO_ADC_L2_SRC_MASK (0x1 << 11)
  7598. +#define RT5671_MONO_ADC_L2_SRC_SFT 11
  7599. +#define RT5671_MONO_ADC_L_SRC_MASK (0x1 << 10)
  7600. +#define RT5671_MONO_ADC_L_SRC_SFT 10
  7601. +#define RT5671_MONO_DMIC_L_SRC_MASK (0x3 << 8)
  7602. +#define RT5671_MONO_DMIC_L_SRC_SFT 8
  7603. +#define RT5671_M_MONO_ADC_R1 (0x1 << 6)
  7604. +#define RT5671_M_MONO_ADC_R1_SFT 6
  7605. +#define RT5671_M_MONO_ADC_R2 (0x1 << 5)
  7606. +#define RT5671_M_MONO_ADC_R2_SFT 5
  7607. +#define RT5671_MONO_ADC_R1_SRC_MASK (0x1 << 4)
  7608. +#define RT5671_MONO_ADC_R1_SRC_SFT 4
  7609. +#define RT5671_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
  7610. +#define RT5671_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
  7611. +#define RT5671_MONO_ADC_R2_SRC_MASK (0x1 << 3)
  7612. +#define RT5671_MONO_ADC_R2_SRC_SFT 3
  7613. +#define RT5671_MONO_ADC_R_SRC_MASK (0x1 << 2)
  7614. +#define RT5671_MONO_ADC_R_SRC_SFT 2
  7615. +#define RT5671_MONO_DMIC_R_SRC_MASK (0x3)
  7616. +#define RT5671_MONO_DMIC_R_SRC_SFT 0
  7617. +
  7618. +/* ADC Mixer to DAC Mixer Control (0x29) */
  7619. +#define RT5671_M_ADCMIX_L (0x1 << 15)
  7620. +#define RT5671_M_ADCMIX_L_SFT 15
  7621. +#define RT5671_M_DAC1_L (0x1 << 14)
  7622. +#define RT5671_M_DAC1_L_SFT 14
  7623. +#define RT5671_DAC1_R_SEL_MASK (0x3 << 10)
  7624. +#define RT5671_DAC1_R_SEL_SFT 10
  7625. +#define RT5671_DAC1_R_SEL_IF1 (0x0 << 10)
  7626. +#define RT5671_DAC1_R_SEL_IF2 (0x1 << 10)
  7627. +#define RT5671_DAC1_R_SEL_IF3 (0x2 << 10)
  7628. +#define RT5671_DAC1_R_SEL_IF4 (0x3 << 10)
  7629. +#define RT5671_DAC1_L_SEL_MASK (0x3 << 8)
  7630. +#define RT5671_DAC1_L_SEL_SFT 8
  7631. +#define RT5671_DAC1_L_SEL_IF1 (0x0 << 8)
  7632. +#define RT5671_DAC1_L_SEL_IF2 (0x1 << 8)
  7633. +#define RT5671_DAC1_L_SEL_IF3 (0x2 << 8)
  7634. +#define RT5671_DAC1_L_SEL_IF4 (0x3 << 8)
  7635. +#define RT5671_M_ADCMIX_R (0x1 << 7)
  7636. +#define RT5671_M_ADCMIX_R_SFT 7
  7637. +#define RT5671_M_DAC1_R (0x1 << 6)
  7638. +#define RT5671_M_DAC1_R_SFT 6
  7639. +
  7640. +/* Stereo DAC Mixer Control (0x2a) */
  7641. +#define RT5671_M_DAC_L1 (0x1 << 14)
  7642. +#define RT5671_M_DAC_L1_SFT 14
  7643. +#define RT5671_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
  7644. +#define RT5671_DAC_L1_STO_L_VOL_SFT 13
  7645. +#define RT5671_M_DAC_L2 (0x1 << 12)
  7646. +#define RT5671_M_DAC_L2_SFT 12
  7647. +#define RT5671_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
  7648. +#define RT5671_DAC_L2_STO_L_VOL_SFT 11
  7649. +#define RT5671_M_ANC_DAC_L (0x1 << 10)
  7650. +#define RT5671_M_ANC_DAC_L_SFT 10
  7651. +#define RT5671_M_DAC_R1_STO_L (0x1 << 9)
  7652. +#define RT5671_M_DAC_R1_STO_L_SFT 9
  7653. +#define RT5671_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
  7654. +#define RT5671_DAC_R1_STO_L_VOL_SFT 8
  7655. +#define RT5671_M_DAC_R1 (0x1 << 6)
  7656. +#define RT5671_M_DAC_R1_SFT 6
  7657. +#define RT5671_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
  7658. +#define RT5671_DAC_R1_STO_R_VOL_SFT 5
  7659. +#define RT5671_M_DAC_R2 (0x1 << 4)
  7660. +#define RT5671_M_DAC_R2_SFT 4
  7661. +#define RT5671_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
  7662. +#define RT5671_DAC_R2_STO_R_VOL_SFT 3
  7663. +#define RT5671_M_ANC_DAC_R (0x1 << 2)
  7664. +#define RT5671_M_ANC_DAC_R_SFT 2
  7665. +#define RT5671_M_DAC_L1_STO_R (0x1 << 1)
  7666. +#define RT5671_M_DAC_L1_STO_R_SFT 1
  7667. +#define RT5671_DAC_L1_STO_R_VOL_MASK (0x1)
  7668. +#define RT5671_DAC_L1_STO_R_VOL_SFT 0
  7669. +
  7670. +/* Mono DAC Mixer Control (0x2b) */
  7671. +#define RT5671_M_DAC_L1_MONO_L (0x1 << 14)
  7672. +#define RT5671_M_DAC_L1_MONO_L_SFT 14
  7673. +#define RT5671_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
  7674. +#define RT5671_DAC_L1_MONO_L_VOL_SFT 13
  7675. +#define RT5671_M_DAC_L2_MONO_L (0x1 << 12)
  7676. +#define RT5671_M_DAC_L2_MONO_L_SFT 12
  7677. +#define RT5671_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
  7678. +#define RT5671_DAC_L2_MONO_L_VOL_SFT 11
  7679. +#define RT5671_M_DAC_R2_MONO_L (0x1 << 10)
  7680. +#define RT5671_M_DAC_R2_MONO_L_SFT 10
  7681. +#define RT5671_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
  7682. +#define RT5671_DAC_R2_MONO_L_VOL_SFT 9
  7683. +#define RT5671_M_DAC_R1_MONO_R (0x1 << 6)
  7684. +#define RT5671_M_DAC_R1_MONO_R_SFT 6
  7685. +#define RT5671_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
  7686. +#define RT5671_DAC_R1_MONO_R_VOL_SFT 5
  7687. +#define RT5671_M_DAC_R2_MONO_R (0x1 << 4)
  7688. +#define RT5671_M_DAC_R2_MONO_R_SFT 4
  7689. +#define RT5671_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
  7690. +#define RT5671_DAC_R2_MONO_R_VOL_SFT 3
  7691. +#define RT5671_M_DAC_L2_MONO_R (0x1 << 2)
  7692. +#define RT5671_M_DAC_L2_MONO_R_SFT 2
  7693. +#define RT5671_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
  7694. +#define RT5671_DAC_L2_MONO_R_VOL_SFT 1
  7695. +
  7696. +/* Digital Mixer Control (0x2c) */
  7697. +#define RT5671_M_STO_L_DAC_L (0x1 << 15)
  7698. +#define RT5671_M_STO_L_DAC_L_SFT 15
  7699. +#define RT5671_STO_L_DAC_L_VOL_MASK (0x1 << 14)
  7700. +#define RT5671_STO_L_DAC_L_VOL_SFT 14
  7701. +#define RT5671_M_DAC_L2_DAC_L (0x1 << 13)
  7702. +#define RT5671_M_DAC_L2_DAC_L_SFT 13
  7703. +#define RT5671_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
  7704. +#define RT5671_DAC_L2_DAC_L_VOL_SFT 12
  7705. +#define RT5671_M_STO_R_DAC_R (0x1 << 11)
  7706. +#define RT5671_M_STO_R_DAC_R_SFT 11
  7707. +#define RT5671_STO_R_DAC_R_VOL_MASK (0x1 << 10)
  7708. +#define RT5671_STO_R_DAC_R_VOL_SFT 10
  7709. +#define RT5671_M_DAC_R2_DAC_R (0x1 << 9)
  7710. +#define RT5671_M_DAC_R2_DAC_R_SFT 9
  7711. +#define RT5671_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
  7712. +#define RT5671_DAC_R2_DAC_R_VOL_SFT 8
  7713. +#define RT5671_M_DAC_R2_DAC_L (0x1 << 7)
  7714. +#define RT5671_M_DAC_R2_DAC_L_SFT 7
  7715. +#define RT5671_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
  7716. +#define RT5671_DAC_R2_DAC_L_VOL_SFT 6
  7717. +#define RT5671_M_DAC_L2_DAC_R (0x1 << 5)
  7718. +#define RT5671_M_DAC_L2_DAC_R_SFT 5
  7719. +#define RT5671_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
  7720. +#define RT5671_DAC_L2_DAC_R_VOL_SFT 4
  7721. +
  7722. +/* DSP Path Control 1 (0x2d) */
  7723. +#define RT5671_RXDP_SEL_MASK (0x7 << 13)
  7724. +#define RT5671_RXDP_SEL_SFT 13
  7725. +#define RT5671_RXDP_SRC_MASK (0x3 << 11)
  7726. +#define RT5671_RXDP_SRC_SFT 11
  7727. +#define RT5671_RXDP_SRC_NOR (0x0 << 11)
  7728. +#define RT5671_RXDP_SRC_DIV2 (0x1 << 11)
  7729. +#define RT5671_RXDP_SRC_DIV3 (0x2 << 11)
  7730. +#define RT5671_TXDP_SRC_MASK (0x3 << 4)
  7731. +#define RT5671_TXDP_SRC_SFT 4
  7732. +#define RT5671_TXDP_SRC_NOR (0x0 << 4)
  7733. +#define RT5671_TXDP_SRC_DIV2 (0x1 << 4)
  7734. +#define RT5671_TXDP_SRC_DIV3 (0x2 << 4)
  7735. +#define RT5671_TXDP_SLOT_SEL_MASK (0x3 << 2)
  7736. +#define RT5671_TXDP_SLOT_SEL_SFT 2
  7737. +#define RT5671_DSP_UL_SEL (0x1 << 1)
  7738. +#define RT5671_DSP_UL_SFT 1
  7739. +#define RT5671_DSP_DL_SEL 0x1
  7740. +#define RT5671_DSP_DL_SFT 0
  7741. +
  7742. +/* DSP Path Control 2 (0x2e) */
  7743. +#define RT5671_TXDP_L_VOL_MASK (0x7f << 8)
  7744. +#define RT5671_TXDP_L_VOL_SFT 8
  7745. +#define RT5671_TXDP_R_VOL_MASK (0x7f)
  7746. +#define RT5671_TXDP_R_VOL_SFT 0
  7747. +
  7748. +/* Digital Interface Data Control (0x2f) */
  7749. +#define RT5671_IF1_ADC2_IN_SEL (0x1 << 15)
  7750. +#define RT5671_IF1_ADC2_IN_SFT 15
  7751. +#define RT5671_IF2_ADC_IN_MASK (0x7 << 12)
  7752. +#define RT5671_IF2_ADC_IN_SFT 12
  7753. +#define RT5671_IF2_DAC_SEL_MASK (0x3 << 10)
  7754. +#define RT5671_IF2_DAC_SEL_SFT 10
  7755. +#define RT5671_IF2_ADC_SEL_MASK (0x3 << 8)
  7756. +#define RT5671_IF2_ADC_SEL_SFT 8
  7757. +#define RT5671_IF3_DAC_SEL_MASK (0x3 << 6)
  7758. +#define RT5671_IF3_DAC_SEL_SFT 6
  7759. +#define RT5671_IF3_ADC_SEL_MASK (0x3 << 4)
  7760. +#define RT5671_IF3_ADC_SEL_SFT 4
  7761. +#define RT5671_IF3_ADC_IN_MASK (0x7)
  7762. +#define RT5671_IF3_ADC_IN_SFT 0
  7763. +
  7764. +/* Digital Interface Data Control (0x30) */
  7765. +#define RT5671_IF4_ADC_IN_MASK (0x3 << 4)
  7766. +#define RT5671_IF4_ADC_IN_SFT 4
  7767. +
  7768. +/* PDM Output Control (0x31) */
  7769. +#define RT5671_PDM1_L_MASK (0x1 << 15)
  7770. +#define RT5671_PDM1_L_SFT 15
  7771. +#define RT5671_M_PDM1_L (0x1 << 14)
  7772. +#define RT5671_M_PDM1_L_SFT 14
  7773. +#define RT5671_PDM1_R_MASK (0x1 << 13)
  7774. +#define RT5671_PDM1_R_SFT 13
  7775. +#define RT5671_M_PDM1_R (0x1 << 12)
  7776. +#define RT5671_M_PDM1_R_SFT 12
  7777. +#define RT5671_PDM2_L_MASK (0x1 << 11)
  7778. +#define RT5671_PDM2_L_SFT 11
  7779. +#define RT5671_M_PDM2_L (0x1 << 10)
  7780. +#define RT5671_M_PDM2_L_SFT 10
  7781. +#define RT5671_PDM2_R_MASK (0x1 << 9)
  7782. +#define RT5671_PDM2_R_SFT 9
  7783. +#define RT5671_M_PDM2_R (0x1 << 8)
  7784. +#define RT5671_M_PDM2_R_SFT 8
  7785. +#define RT5671_PDM2_BUSY (0x1 << 7)
  7786. +#define RT5671_PDM1_BUSY (0x1 << 6)
  7787. +#define RT5671_PDM_PATTERN (0x1 << 5)
  7788. +#define RT5671_PDM_GAIN (0x1 << 4)
  7789. +#define RT5671_PDM_DIV_MASK (0x3)
  7790. +
  7791. +/* REC Left Mixer Control 1 (0x3b) */
  7792. +#define RT5671_G_HP_L_RM_L_MASK (0x7 << 13)
  7793. +#define RT5671_G_HP_L_RM_L_SFT 13
  7794. +#define RT5671_G_IN_L_RM_L_MASK (0x7 << 10)
  7795. +#define RT5671_G_IN_L_RM_L_SFT 10
  7796. +#define RT5671_G_BST4_RM_L_MASK (0x7 << 7)
  7797. +#define RT5671_G_BST4_RM_L_SFT 7
  7798. +#define RT5671_G_BST3_RM_L_MASK (0x7 << 4)
  7799. +#define RT5671_G_BST3_RM_L_SFT 4
  7800. +#define RT5671_G_BST2_RM_L_MASK (0x7 << 1)
  7801. +#define RT5671_G_BST2_RM_L_SFT 1
  7802. +
  7803. +/* REC Left Mixer Control 2 (0x3c) */
  7804. +#define RT5671_G_BST1_RM_L_MASK (0x7 << 13)
  7805. +#define RT5671_G_BST1_RM_L_SFT 13
  7806. +#define RT5671_M_IN_L_RM_L (0x1 << 5)
  7807. +#define RT5671_M_IN_L_RM_L_SFT 5
  7808. +#define RT5671_M_BST4_RM_L (0x1 << 4)
  7809. +#define RT5671_M_BST4_RM_L_SFT 4
  7810. +#define RT5671_M_BST3_RM_L (0x1 << 3)
  7811. +#define RT5671_M_BST3_RM_L_SFT 3
  7812. +#define RT5671_M_BST2_RM_L (0x1 << 2)
  7813. +#define RT5671_M_BST2_RM_L_SFT 2
  7814. +#define RT5671_M_BST1_RM_L (0x1 << 1)
  7815. +#define RT5671_M_BST1_RM_L_SFT 1
  7816. +
  7817. +/* REC Right Mixer Control 1 (0x3d) */
  7818. +#define RT5671_G_HP_R_RM_R_MASK (0x7 << 13)
  7819. +#define RT5671_G_HP_R_RM_R_SFT 13
  7820. +#define RT5671_G_IN_R_RM_R_MASK (0x7 << 10)
  7821. +#define RT5671_G_IN_R_RM_R_SFT 10
  7822. +#define RT5671_G_BST4_RM_R_MASK (0x7 << 7)
  7823. +#define RT5671_G_BST4_RM_R_SFT 7
  7824. +#define RT5671_G_BST3_RM_R_MASK (0x7 << 4)
  7825. +#define RT5671_G_BST3_RM_R_SFT 4
  7826. +#define RT5671_G_BST2_RM_R_MASK (0x7 << 1)
  7827. +#define RT5671_G_BST2_RM_R_SFT 1
  7828. +
  7829. +/* REC Right Mixer Control 2 (0x3e) */
  7830. +#define RT5671_G_BST1_RM_R_MASK (0x7 << 13)
  7831. +#define RT5671_G_BST1_RM_R_SFT 13
  7832. +#define RT5671_M_IN_R_RM_R (0x1 << 5)
  7833. +#define RT5671_M_IN_R_RM_R_SFT 5
  7834. +#define RT5671_M_BST4_RM_R (0x1 << 4)
  7835. +#define RT5671_M_BST4_RM_R_SFT 4
  7836. +#define RT5671_M_BST3_RM_R (0x1 << 3)
  7837. +#define RT5671_M_BST3_RM_R_SFT 3
  7838. +#define RT5671_M_BST2_RM_R (0x1 << 2)
  7839. +#define RT5671_M_BST2_RM_R_SFT 2
  7840. +#define RT5671_M_BST1_RM_R (0x1 << 1)
  7841. +#define RT5671_M_BST1_RM_R_SFT 1
  7842. +
  7843. +/* REC Mono Mixer Control 2 (0x40) */
  7844. +#define RT5671_G_BST1_RM_M_MASK (0x7 << 13)
  7845. +#define RT5671_G_BST1_RM_M_SFT 13
  7846. +#define RT5671_M_BST4_RM_M (0x1 << 4)
  7847. +#define RT5671_M_BST4_RM_M_SFT 4
  7848. +#define RT5671_M_BST3_RM_M (0x1 << 3)
  7849. +#define RT5671_M_BST3_RM_M_SFT 3
  7850. +#define RT5671_M_BST2_RM_M (0x1 << 2)
  7851. +#define RT5671_M_BST2_RM_M_SFT 2
  7852. +#define RT5671_M_BST1_RM_M (0x1 << 1)
  7853. +#define RT5671_M_BST1_RM_M_SFT 1
  7854. +
  7855. +
  7856. +/* HPMIX Control (0x45) */
  7857. +#define RT5671_M_DAC2_HM (0x1 << 15)
  7858. +#define RT5671_M_DAC2_HM_SFT 15
  7859. +#define RT5671_M_HPVOL_HM (0x1 << 14)
  7860. +#define RT5671_M_HPVOL_HM_SFT 14
  7861. +#define RT5671_M_DAC1_HM (0x1 << 13)
  7862. +#define RT5671_M_DAC1_HM_SFT 13
  7863. +#define RT5671_G_HPOMIX_MASK (0x1 << 12)
  7864. +#define RT5671_G_HPOMIX_SFT 12
  7865. +#define RT5671_M_INR1_HMR (0x1 << 3)
  7866. +#define RT5671_M_INR1_HMR_SFT 3
  7867. +#define RT5671_M_DACR1_HMR (0x1 << 2)
  7868. +#define RT5671_M_DACR1_HMR_SFT 2
  7869. +#define RT5671_M_INL1_HML (0x1 << 1)
  7870. +#define RT5671_M_INL1_HML_SFT 1
  7871. +#define RT5671_M_DACL1_HML (0x1)
  7872. +#define RT5671_M_DACL1_HML_SFT 0
  7873. +
  7874. +/* Mono Output Mixer Control (0x4c) */
  7875. +#define RT5671_M_DAC_L1_MA (0x1 << 14)
  7876. +#define RT5671_M_DAC_L1_MA_SFT 14
  7877. +#define RT5671_M_OV_R_MM (0x1 << 13)
  7878. +#define RT5671_M_OV_R_MM_SFT 13
  7879. +#define RT5671_M_OV_L_MM (0x1 << 12)
  7880. +#define RT5671_M_OV_L_MM_SFT 12
  7881. +#define RT5671_G_MONOMIX_MASK (0x1 << 10)
  7882. +#define RT5671_G_MONOMIX_SFT 10
  7883. +#define RT5671_M_DAC_R2_MM (0x1 << 9)
  7884. +#define RT5671_M_DAC_R2_MM_SFT 9
  7885. +#define RT5671_M_DAC_L2_MM (0x1 << 8)
  7886. +#define RT5671_M_DAC_L2_MM_SFT 8
  7887. +#define RT5671_M_BST4_MM (0x1 << 7)
  7888. +#define RT5671_M_BST4_MM_SFT 7
  7889. +
  7890. +/* Output Left Mixer Control 1 (0x4d) */
  7891. +#define RT5671_G_BST3_OM_L_MASK (0x7 << 13)
  7892. +#define RT5671_G_BST3_OM_L_SFT 13
  7893. +#define RT5671_G_BST2_OM_L_MASK (0x7 << 10)
  7894. +#define RT5671_G_BST2_OM_L_SFT 10
  7895. +#define RT5671_G_BST1_OM_L_MASK (0x7 << 7)
  7896. +#define RT5671_G_BST1_OM_L_SFT 7
  7897. +#define RT5671_G_IN_L_OM_L_MASK (0x7 << 4)
  7898. +#define RT5671_G_IN_L_OM_L_SFT 4
  7899. +#define RT5671_G_RM_L_OM_L_MASK (0x7 << 1)
  7900. +#define RT5671_G_RM_L_OM_L_SFT 1
  7901. +
  7902. +/* Output Left Mixer Control 2 (0x4e) */
  7903. +#define RT5671_G_DAC_R2_OM_L_MASK (0x7 << 13)
  7904. +#define RT5671_G_DAC_R2_OM_L_SFT 13
  7905. +#define RT5671_G_DAC_L2_OM_L_MASK (0x7 << 10)
  7906. +#define RT5671_G_DAC_L2_OM_L_SFT 10
  7907. +#define RT5671_G_DAC_L1_OM_L_MASK (0x7 << 7)
  7908. +#define RT5671_G_DAC_L1_OM_L_SFT 7
  7909. +
  7910. +/* Output Left Mixer Control 3 (0x4f) */
  7911. +#define RT5671_M_BST2_OM_L (0x1 << 6)
  7912. +#define RT5671_M_BST2_OM_L_SFT 6
  7913. +#define RT5671_M_BST1_OM_L (0x1 << 5)
  7914. +#define RT5671_M_BST1_OM_L_SFT 5
  7915. +#define RT5671_M_IN_L_OM_L (0x1 << 4)
  7916. +#define RT5671_M_IN_L_OM_L_SFT 4
  7917. +#define RT5671_M_DAC_L2_OM_L (0x1 << 1)
  7918. +#define RT5671_M_DAC_L2_OM_L_SFT 1
  7919. +#define RT5671_M_DAC_L1_OM_L (0x1)
  7920. +#define RT5671_M_DAC_L1_OM_L_SFT 0
  7921. +
  7922. +/* Output Right Mixer Control 1 (0x50) */
  7923. +#define RT5671_G_BST4_OM_R_MASK (0x7 << 13)
  7924. +#define RT5671_G_BST4_OM_R_SFT 13
  7925. +#define RT5671_G_BST2_OM_R_MASK (0x7 << 10)
  7926. +#define RT5671_G_BST2_OM_R_SFT 10
  7927. +#define RT5671_G_BST1_OM_R_MASK (0x7 << 7)
  7928. +#define RT5671_G_BST1_OM_R_SFT 7
  7929. +#define RT5671_G_IN_R_OM_R_MASK (0x7 << 4)
  7930. +#define RT5671_G_IN_R_OM_R_SFT 4
  7931. +#define RT5671_G_RM_R_OM_R_MASK (0x7 << 1)
  7932. +#define RT5671_G_RM_R_OM_R_SFT 1
  7933. +
  7934. +/* Output Right Mixer Control 2 (0x51) */
  7935. +#define RT5671_G_DAC_L2_OM_R_MASK (0x7 << 13)
  7936. +#define RT5671_G_DAC_L2_OM_R_SFT 13
  7937. +#define RT5671_G_DAC_R2_OM_R_MASK (0x7 << 10)
  7938. +#define RT5671_G_DAC_R2_OM_R_SFT 10
  7939. +#define RT5671_G_DAC_R1_OM_R_MASK (0x7 << 7)
  7940. +#define RT5671_G_DAC_R1_OM_R_SFT 7
  7941. +
  7942. +/* Output Right Mixer Control 3 (0x52) */
  7943. +#define RT5671_M_BST4_OM_R (0x1 << 7)
  7944. +#define RT5671_M_BST4_OM_R_SFT 7
  7945. +#define RT5671_M_BST3_OM_R (0x1 << 6)
  7946. +#define RT5671_M_BST3_OM_R_SFT 6
  7947. +#define RT5671_M_IN_R_OM_R (0x1 << 4)
  7948. +#define RT5671_M_IN_R_OM_R_SFT 4
  7949. +#define RT5671_M_DAC_R2_OM_R (0x1 << 1)
  7950. +#define RT5671_M_DAC_R2_OM_R_SFT 1
  7951. +#define RT5671_M_DAC_R1_OM_R (0x1)
  7952. +#define RT5671_M_DAC_R1_OM_R_SFT 0
  7953. +
  7954. +/* LOUT Mixer Control (0x53) */
  7955. +#define RT5671_M_DAC_L1_LM (0x1 << 15)
  7956. +#define RT5671_M_DAC_L1_LM_SFT 15
  7957. +#define RT5671_M_DAC_R1_LM (0x1 << 14)
  7958. +#define RT5671_M_DAC_R1_LM_SFT 14
  7959. +#define RT5671_M_OV_L_LM (0x1 << 13)
  7960. +#define RT5671_M_OV_L_LM_SFT 13
  7961. +#define RT5671_M_OV_R_LM (0x1 << 12)
  7962. +#define RT5671_M_OV_R_LM_SFT 12
  7963. +#define RT5671_G_LOUTMIX_MASK (0x1 << 11)
  7964. +#define RT5671_G_LOUTMIX_SFT 11
  7965. +
  7966. +/* Power Management for Digital 1 (0x61) */
  7967. +#define RT5671_PWR_I2S1 (0x1 << 15)
  7968. +#define RT5671_PWR_I2S1_BIT 15
  7969. +#define RT5671_PWR_I2S2 (0x1 << 14)
  7970. +#define RT5671_PWR_I2S2_BIT 14
  7971. +#define RT5671_PWR_I2S3 (0x1 << 13)
  7972. +#define RT5671_PWR_I2S3_BIT 13
  7973. +#define RT5671_PWR_DAC_L1 (0x1 << 12)
  7974. +#define RT5671_PWR_DAC_L1_BIT 12
  7975. +#define RT5671_PWR_DAC_R1 (0x1 << 11)
  7976. +#define RT5671_PWR_DAC_R1_BIT 11
  7977. +#define RT5671_PWR_I2S4 (0x1 << 10)
  7978. +#define RT5671_PWR_I2S4_BIT 10
  7979. +#define RT5671_PWR_DAC_L2 (0x1 << 7)
  7980. +#define RT5671_PWR_DAC_L2_BIT 7
  7981. +#define RT5671_PWR_DAC_R2 (0x1 << 6)
  7982. +#define RT5671_PWR_DAC_R2_BIT 6
  7983. +#define RT5671_PWR_ADC_3 (0x1 << 3)
  7984. +#define RT5671_PWR_ADC_3_BIT 3
  7985. +#define RT5671_PWR_ADC_L (0x1 << 2)
  7986. +#define RT5671_PWR_ADC_L_BIT 2
  7987. +#define RT5671_PWR_ADC_R (0x1 << 1)
  7988. +#define RT5671_PWR_ADC_R_BIT 1
  7989. +#define RT5671_PWR_CLS_D (0x1)
  7990. +#define RT5671_PWR_CLS_D_BIT 0
  7991. +
  7992. +/* Power Management for Digital 2 (0x62) */
  7993. +#define RT5671_PWR_ADC_S1F (0x1 << 15)
  7994. +#define RT5671_PWR_ADC_S1F_BIT 15
  7995. +#define RT5671_PWR_ADC_MF_L (0x1 << 14)
  7996. +#define RT5671_PWR_ADC_MF_L_BIT 14
  7997. +#define RT5671_PWR_ADC_MF_R (0x1 << 13)
  7998. +#define RT5671_PWR_ADC_MF_R_BIT 13
  7999. +#define RT5671_PWR_I2S_DSP (0x1 << 12)
  8000. +#define RT5671_PWR_I2S_DSP_BIT 12
  8001. +#define RT5671_PWR_DAC_S1F (0x1 << 11)
  8002. +#define RT5671_PWR_DAC_S1F_BIT 11
  8003. +#define RT5671_PWR_DAC_MF_L (0x1 << 10)
  8004. +#define RT5671_PWR_DAC_MF_L_BIT 10
  8005. +#define RT5671_PWR_DAC_MF_R (0x1 << 9)
  8006. +#define RT5671_PWR_DAC_MF_R_BIT 9
  8007. +#define RT5671_PWR_ADC_S2F (0x1 << 8)
  8008. +#define RT5671_PWR_ADC_S2F_BIT 8
  8009. +#define RT5671_PWR_PDM1 (0x1 << 7)
  8010. +#define RT5671_PWR_PDM1_BIT 7
  8011. +#define RT5671_PWR_PDM2 (0x1 << 6)
  8012. +#define RT5671_PWR_PDM2_BIT 6
  8013. +
  8014. +/* Power Management for Analog 1 (0x63) */
  8015. +#define RT5671_PWR_VREF1 (0x1 << 15)
  8016. +#define RT5671_PWR_VREF1_BIT 15
  8017. +#define RT5671_PWR_FV1 (0x1 << 14)
  8018. +#define RT5671_PWR_FV1_BIT 14
  8019. +#define RT5671_PWR_MB (0x1 << 13)
  8020. +#define RT5671_PWR_MB_BIT 13
  8021. +#define RT5671_PWR_LM (0x1 << 12)
  8022. +#define RT5671_PWR_LM_BIT 12
  8023. +#define RT5671_PWR_BG (0x1 << 11)
  8024. +#define RT5671_PWR_BG_BIT 11
  8025. +#define RT5671_PWR_MA (0x1 << 10)
  8026. +#define RT5671_PWR_MA_BIT 10
  8027. +#define RT5671_PWR_MM (0x1 << 9)
  8028. +#define RT5671_PWR_MM_BIT 9
  8029. +#define RT5671_PWR_HP_L (0x1 << 7)
  8030. +#define RT5671_PWR_HP_L_BIT 7
  8031. +#define RT5671_PWR_HP_R (0x1 << 6)
  8032. +#define RT5671_PWR_HP_R_BIT 6
  8033. +#define RT5671_PWR_HA (0x1 << 5)
  8034. +#define RT5671_PWR_HA_BIT 5
  8035. +#define RT5671_PWR_VREF2 (0x1 << 4)
  8036. +#define RT5671_PWR_VREF2_BIT 4
  8037. +#define RT5671_PWR_FV2 (0x1 << 3)
  8038. +#define RT5671_PWR_FV2_BIT 3
  8039. +#define RT5671_LDO_SEL_MASK (0x7)
  8040. +#define RT5671_LDO_SEL_SFT 0
  8041. +
  8042. +/* Power Management for Analog 2 (0x64) */
  8043. +#define RT5671_PWR_BST1 (0x1 << 15)
  8044. +#define RT5671_PWR_BST1_BIT 15
  8045. +#define RT5671_PWR_BST2 (0x1 << 14)
  8046. +#define RT5671_PWR_BST2_BIT 14
  8047. +#define RT5671_PWR_BST3 (0x1 << 13)
  8048. +#define RT5671_PWR_BST3_BIT 13
  8049. +#define RT5671_PWR_BST4 (0x1 << 12)
  8050. +#define RT5671_PWR_BST4_BIT 12
  8051. +#define RT5671_PWR_MB1 (0x1 << 11)
  8052. +#define RT5671_PWR_MB1_BIT 11
  8053. +#define RT5671_PWR_MB2 (0x1 << 10)
  8054. +#define RT5671_PWR_MB2_BIT 10
  8055. +#define RT5671_PWR_PLL (0x1 << 9)
  8056. +#define RT5671_PWR_PLL_BIT 9
  8057. +#define RT5671_PWR_BST1_P (0x1 << 6)
  8058. +#define RT5671_PWR_BST1_P_BIT 6
  8059. +#define RT5671_PWR_BST2_P (0x1 << 5)
  8060. +#define RT5671_PWR_BST2_P_BIT 5
  8061. +#define RT5671_PWR_BST3_P (0x1 << 4)
  8062. +#define RT5671_PWR_BST3_P_BIT 4
  8063. +#define RT5671_PWR_BST4_P (0x1 << 3)
  8064. +#define RT5671_PWR_BST4_P_BIT 3
  8065. +#define RT5671_PWR_JD1 (0x1 << 2)
  8066. +#define RT5671_PWR_JD1_BIT 2
  8067. +#define RT5671_PWR_JD (0x1 << 1)
  8068. +#define RT5671_PWR_JD_BIT 1
  8069. +
  8070. +/* Power Management for Mixer (0x65) */
  8071. +#define RT5671_PWR_OM_L (0x1 << 15)
  8072. +#define RT5671_PWR_OM_L_BIT 15
  8073. +#define RT5671_PWR_OM_R (0x1 << 14)
  8074. +#define RT5671_PWR_OM_R_BIT 14
  8075. +#define RT5671_PWR_RM_L (0x1 << 11)
  8076. +#define RT5671_PWR_RM_L_BIT 11
  8077. +#define RT5671_PWR_RM_R (0x1 << 10)
  8078. +#define RT5671_PWR_RM_R_BIT 10
  8079. +#define RT5671_PWR_RM_M (0x1 << 9)
  8080. +#define RT5671_PWR_RM_M_BIT 9
  8081. +
  8082. +/* Power Management for Volume (0x66) */
  8083. +#define RT5671_PWR_HV_L (0x1 << 11)
  8084. +#define RT5671_PWR_HV_L_BIT 11
  8085. +#define RT5671_PWR_HV_R (0x1 << 10)
  8086. +#define RT5671_PWR_HV_R_BIT 10
  8087. +#define RT5671_PWR_IN_L (0x1 << 9)
  8088. +#define RT5671_PWR_IN_L_BIT 9
  8089. +#define RT5671_PWR_IN_R (0x1 << 8)
  8090. +#define RT5671_PWR_IN_R_BIT 8
  8091. +#define RT5671_PWR_MIC_DET (0x1 << 5)
  8092. +#define RT5671_PWR_MIC_DET_BIT 5
  8093. +
  8094. +/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
  8095. +#define RT5671_I2S_MS_MASK (0x1 << 15)
  8096. +#define RT5671_I2S_MS_SFT 15
  8097. +#define RT5671_I2S_MS_M (0x0 << 15)
  8098. +#define RT5671_I2S_MS_S (0x1 << 15)
  8099. +#define RT5671_I2S_IF_MASK (0x7 << 12)
  8100. +#define RT5671_I2S_IF_SFT 12
  8101. +#define RT5671_I2S_O_CP_MASK (0x3 << 10)
  8102. +#define RT5671_I2S_O_CP_SFT 10
  8103. +#define RT5671_I2S_O_CP_OFF (0x0 << 10)
  8104. +#define RT5671_I2S_O_CP_U_LAW (0x1 << 10)
  8105. +#define RT5671_I2S_O_CP_A_LAW (0x2 << 10)
  8106. +#define RT5671_I2S_I_CP_MASK (0x3 << 8)
  8107. +#define RT5671_I2S_I_CP_SFT 8
  8108. +#define RT5671_I2S_I_CP_OFF (0x0 << 8)
  8109. +#define RT5671_I2S_I_CP_U_LAW (0x1 << 8)
  8110. +#define RT5671_I2S_I_CP_A_LAW (0x2 << 8)
  8111. +#define RT5671_I2S_BP_MASK (0x1 << 7)
  8112. +#define RT5671_I2S_BP_SFT 7
  8113. +#define RT5671_I2S_BP_NOR (0x0 << 7)
  8114. +#define RT5671_I2S_BP_INV (0x1 << 7)
  8115. +#define RT5671_I2S_DL_MASK (0x3 << 2)
  8116. +#define RT5671_I2S_DL_SFT 2
  8117. +#define RT5671_I2S_DL_16 (0x0 << 2)
  8118. +#define RT5671_I2S_DL_20 (0x1 << 2)
  8119. +#define RT5671_I2S_DL_24 (0x2 << 2)
  8120. +#define RT5671_I2S_DL_8 (0x3 << 2)
  8121. +#define RT5671_I2S_DF_MASK (0x3)
  8122. +#define RT5671_I2S_DF_SFT 0
  8123. +#define RT5671_I2S_DF_I2S (0x0)
  8124. +#define RT5671_I2S_DF_LEFT (0x1)
  8125. +#define RT5671_I2S_DF_PCM_A (0x2)
  8126. +#define RT5671_I2S_DF_PCM_B (0x3)
  8127. +
  8128. +/* I2S2 Audio Serial Data Port Control (0x71) */
  8129. +#define RT5671_I2S2_SDI_MASK (0x1 << 6)
  8130. +#define RT5671_I2S2_SDI_SFT 6
  8131. +#define RT5671_I2S2_SDI_I2S1 (0x0 << 6)
  8132. +#define RT5671_I2S2_SDI_I2S2 (0x1 << 6)
  8133. +
  8134. +/* ADC/DAC Clock Control 1 (0x73) */
  8135. +#define RT5671_I2S_PD1_MASK (0x7 << 12)
  8136. +#define RT5671_I2S_PD1_SFT 12
  8137. +#define RT5671_I2S_PD1_1 (0x0 << 12)
  8138. +#define RT5671_I2S_PD1_2 (0x1 << 12)
  8139. +#define RT5671_I2S_PD1_3 (0x2 << 12)
  8140. +#define RT5671_I2S_PD1_4 (0x3 << 12)
  8141. +#define RT5671_I2S_PD1_6 (0x4 << 12)
  8142. +#define RT5671_I2S_PD1_8 (0x5 << 12)
  8143. +#define RT5671_I2S_PD1_12 (0x6 << 12)
  8144. +#define RT5671_I2S_PD1_16 (0x7 << 12)
  8145. +#define RT5671_I2S_BCLK_MS2_MASK (0x1 << 11)
  8146. +#define RT5671_I2S_BCLK_MS2_SFT 11
  8147. +#define RT5671_I2S_BCLK_MS2_32 (0x0 << 11)
  8148. +#define RT5671_I2S_BCLK_MS2_64 (0x1 << 11)
  8149. +#define RT5671_I2S_PD2_MASK (0x7 << 8)
  8150. +#define RT5671_I2S_PD2_SFT 8
  8151. +#define RT5671_I2S_PD2_1 (0x0 << 8)
  8152. +#define RT5671_I2S_PD2_2 (0x1 << 8)
  8153. +#define RT5671_I2S_PD2_3 (0x2 << 8)
  8154. +#define RT5671_I2S_PD2_4 (0x3 << 8)
  8155. +#define RT5671_I2S_PD2_6 (0x4 << 8)
  8156. +#define RT5671_I2S_PD2_8 (0x5 << 8)
  8157. +#define RT5671_I2S_PD2_12 (0x6 << 8)
  8158. +#define RT5671_I2S_PD2_16 (0x7 << 8)
  8159. +#define RT5671_I2S_BCLK_MS3_MASK (0x1 << 7)
  8160. +#define RT5671_I2S_BCLK_MS3_SFT 7
  8161. +#define RT5671_I2S_BCLK_MS3_32 (0x0 << 7)
  8162. +#define RT5671_I2S_BCLK_MS3_64 (0x1 << 7)
  8163. +#define RT5671_I2S_PD3_MASK (0x7 << 4)
  8164. +#define RT5671_I2S_PD3_SFT 4
  8165. +#define RT5671_I2S_PD3_1 (0x0 << 4)
  8166. +#define RT5671_I2S_PD3_2 (0x1 << 4)
  8167. +#define RT5671_I2S_PD3_3 (0x2 << 4)
  8168. +#define RT5671_I2S_PD3_4 (0x3 << 4)
  8169. +#define RT5671_I2S_PD3_6 (0x4 << 4)
  8170. +#define RT5671_I2S_PD3_8 (0x5 << 4)
  8171. +#define RT5671_I2S_PD3_12 (0x6 << 4)
  8172. +#define RT5671_I2S_PD3_16 (0x7 << 4)
  8173. +#define RT5671_DAC_OSR_MASK (0x3 << 2)
  8174. +#define RT5671_DAC_OSR_SFT 2
  8175. +#define RT5671_DAC_OSR_128 (0x0 << 2)
  8176. +#define RT5671_DAC_OSR_64 (0x1 << 2)
  8177. +#define RT5671_DAC_OSR_32 (0x2 << 2)
  8178. +#define RT5671_DAC_OSR_16 (0x3 << 2)
  8179. +#define RT5671_ADC_OSR_MASK (0x3)
  8180. +#define RT5671_ADC_OSR_SFT 0
  8181. +#define RT5671_ADC_OSR_128 (0x0)
  8182. +#define RT5671_ADC_OSR_64 (0x1)
  8183. +#define RT5671_ADC_OSR_32 (0x2)
  8184. +#define RT5671_ADC_OSR_16 (0x3)
  8185. +
  8186. +/* ADC/DAC Clock Control 2 (0x74) */
  8187. +#define RT5671_DAC_L_OSR_MASK (0x3 << 14)
  8188. +#define RT5671_DAC_L_OSR_SFT 14
  8189. +#define RT5671_DAC_L_OSR_128 (0x0 << 14)
  8190. +#define RT5671_DAC_L_OSR_64 (0x1 << 14)
  8191. +#define RT5671_DAC_L_OSR_32 (0x2 << 14)
  8192. +#define RT5671_DAC_L_OSR_16 (0x3 << 14)
  8193. +#define RT5671_ADC_R_OSR_MASK (0x3 << 12)
  8194. +#define RT5671_ADC_R_OSR_SFT 12
  8195. +#define RT5671_ADC_R_OSR_128 (0x0 << 12)
  8196. +#define RT5671_ADC_R_OSR_64 (0x1 << 12)
  8197. +#define RT5671_ADC_R_OSR_32 (0x2 << 12)
  8198. +#define RT5671_ADC_R_OSR_16 (0x3 << 12)
  8199. +#define RT5671_DAHPF_EN (0x1 << 11)
  8200. +#define RT5671_DAHPF_EN_SFT 11
  8201. +#define RT5671_ADHPF_EN (0x1 << 10)
  8202. +#define RT5671_ADHPF_EN_SFT 10
  8203. +
  8204. +/* Digital Microphone Control (0x75) */
  8205. +#define RT5671_DMIC_1_EN_MASK (0x1 << 15)
  8206. +#define RT5671_DMIC_1_EN_SFT 15
  8207. +#define RT5671_DMIC_1_DIS (0x0 << 15)
  8208. +#define RT5671_DMIC_1_EN (0x1 << 15)
  8209. +#define RT5671_DMIC_2_EN_MASK (0x1 << 14)
  8210. +#define RT5671_DMIC_2_EN_SFT 14
  8211. +#define RT5671_DMIC_2_DIS (0x0 << 14)
  8212. +#define RT5671_DMIC_2_EN (0x1 << 14)
  8213. +#define RT5671_DMIC_1L_LH_MASK (0x1 << 13)
  8214. +#define RT5671_DMIC_1L_LH_SFT 13
  8215. +#define RT5671_DMIC_1L_LH_FALLING (0x0 << 13)
  8216. +#define RT5671_DMIC_1L_LH_RISING (0x1 << 13)
  8217. +#define RT5671_DMIC_1R_LH_MASK (0x1 << 12)
  8218. +#define RT5671_DMIC_1R_LH_SFT 12
  8219. +#define RT5671_DMIC_1R_LH_FALLING (0x0 << 12)
  8220. +#define RT5671_DMIC_1R_LH_RISING (0x1 << 12)
  8221. +#define RT5671_DMIC_2_DP_MASK (0x1 << 10)
  8222. +#define RT5671_DMIC_2_DP_SFT 10
  8223. +#define RT5671_DMIC_2_DP_GPIO4 (0x0 << 10)
  8224. +#define RT5671_DMIC_2_DP_IN1N (0x1 << 10)
  8225. +#define RT5671_DMIC_2L_LH_MASK (0x1 << 9)
  8226. +#define RT5671_DMIC_2L_LH_SFT 9
  8227. +#define RT5671_DMIC_2L_LH_FALLING (0x0 << 9)
  8228. +#define RT5671_DMIC_2L_LH_RISING (0x1 << 9)
  8229. +#define RT5671_DMIC_2R_LH_MASK (0x1 << 8)
  8230. +#define RT5671_DMIC_2R_LH_SFT 8
  8231. +#define RT5671_DMIC_2R_LH_FALLING (0x0 << 8)
  8232. +#define RT5671_DMIC_2R_LH_RISING (0x1 << 8)
  8233. +#define RT5671_DMIC_CLK_MASK (0x7 << 5)
  8234. +#define RT5671_DMIC_CLK_SFT 5
  8235. +#define RT5671_DMIC_3_EN_MASK (0x1 << 4)
  8236. +#define RT5671_DMIC_3_EN_SFT 4
  8237. +#define RT5671_DMIC_3_DIS (0x0 << 4)
  8238. +#define RT5671_DMIC_3_EN (0x1 << 4)
  8239. +#define RT5671_DMIC_1_DP_MASK (0x3 << 0)
  8240. +#define RT5671_DMIC_1_DP_SFT 0
  8241. +#define RT5671_DMIC_1_DP_GPIO6 (0x0 << 0)
  8242. +#define RT5671_DMIC_1_DP_IN2P (0x1 << 0)
  8243. +#define RT5671_DMIC_1_DP_GPIO7 (0x2 << 0)
  8244. +
  8245. +/* Clock Control 1 (0x7f) */
  8246. +#define RT5671_I2S_BCLK_MS4_MASK (0x1 << 15)
  8247. +#define RT5671_I2S_BCLK_MS4_SFT 15
  8248. +#define RT5671_I2S_BCLK_MS4_32 (0x0 << 15)
  8249. +#define RT5671_I2S_BCLK_MS4_64 (0x1 << 15)
  8250. +#define RT5671_I2S_PD4_MASK (0x7 << 12)
  8251. +#define RT5671_I2S_PD4_SFT 12
  8252. +#define RT5671_I2S_PD4_1 (0x0 << 12)
  8253. +#define RT5671_I2S_PD4_2 (0x1 << 12)
  8254. +#define RT5671_I2S_PD4_3 (0x2 << 12)
  8255. +#define RT5671_I2S_PD4_4 (0x3 << 12)
  8256. +#define RT5671_I2S_PD4_6 (0x4 << 12)
  8257. +#define RT5671_I2S_PD4_8 (0x5 << 12)
  8258. +#define RT5671_I2S_PD4_12 (0x6 << 12)
  8259. +#define RT5671_I2S_PD4_16 (0x7 << 12)
  8260. +
  8261. +/* Global Clock Control (0x80) */
  8262. +#define RT5671_SCLK_SRC_MASK (0x3 << 14)
  8263. +#define RT5671_SCLK_SRC_SFT 14
  8264. +#define RT5671_SCLK_SRC_MCLK (0x0 << 14)
  8265. +#define RT5671_SCLK_SRC_PLL1 (0x1 << 14)
  8266. +#define RT5671_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
  8267. +#define RT5671_PLL1_SRC_MASK (0x7 << 11)
  8268. +#define RT5671_PLL1_SRC_SFT 11
  8269. +#define RT5671_PLL1_SRC_MCLK (0x0 << 11)
  8270. +#define RT5671_PLL1_SRC_BCLK1 (0x1 << 11)
  8271. +#define RT5671_PLL1_SRC_BCLK2 (0x2 << 11)
  8272. +#define RT5671_PLL1_SRC_BCLK3 (0x3 << 11)
  8273. +#define RT5671_PLL1_SRC_BCLK4 (0x4 << 11)
  8274. +#define RT5671_PLL1_SRC_Int (0x5 << 11)
  8275. +#define RT5671_PLL1_PD_MASK (0x1 << 3)
  8276. +#define RT5671_PLL1_PD_SFT 3
  8277. +#define RT5671_PLL1_PD_1 (0x0 << 3)
  8278. +#define RT5671_PLL1_PD_2 (0x1 << 3)
  8279. +
  8280. +#define RT5671_PLL_INP_MAX 40000000
  8281. +#define RT5671_PLL_INP_MIN 256000
  8282. +/* PLL M/N/K Code Control 1 (0x81) */
  8283. +#define RT5671_PLL_N_MAX 0x1ff
  8284. +#define RT5671_PLL_N_MASK (RT5671_PLL_N_MAX << 7)
  8285. +#define RT5671_PLL_N_SFT 7
  8286. +#define RT5671_PLL_K_MAX 0x1f
  8287. +#define RT5671_PLL_K_MASK (RT5671_PLL_K_MAX)
  8288. +#define RT5671_PLL_K_SFT 0
  8289. +
  8290. +/* PLL M/N/K Code Control 2 (0x82) */
  8291. +#define RT5671_PLL_M_MAX 0xf
  8292. +#define RT5671_PLL_M_MASK (RT5671_PLL_M_MAX << 12)
  8293. +#define RT5671_PLL_M_SFT 12
  8294. +#define RT5671_PLL_M_BP (0x1 << 11)
  8295. +#define RT5671_PLL_M_BP_SFT 11
  8296. +
  8297. +/* ASRC Control 1 (0x83) */
  8298. +#define RT5671_STO_T_MASK (0x1 << 15)
  8299. +#define RT5671_STO_T_SFT 15
  8300. +#define RT5671_STO_T_SCLK (0x0 << 15)
  8301. +#define RT5671_STO_T_LRCK1 (0x1 << 15)
  8302. +#define RT5671_M1_T_MASK (0x1 << 14)
  8303. +#define RT5671_M1_T_SFT 14
  8304. +#define RT5671_M1_T_I2S2 (0x0 << 14)
  8305. +#define RT5671_M1_T_I2S2_D3 (0x1 << 14)
  8306. +#define RT5671_I2S2_F_MASK (0x1 << 12)
  8307. +#define RT5671_I2S2_F_SFT 12
  8308. +#define RT5671_I2S2_F_I2S2_D2 (0x0 << 12)
  8309. +#define RT5671_I2S2_F_I2S1_TCLK (0x1 << 12)
  8310. +#define RT5671_DMIC_1_M_MASK (0x1 << 9)
  8311. +#define RT5671_DMIC_1_M_SFT 9
  8312. +#define RT5671_DMIC_1_M_NOR (0x0 << 9)
  8313. +#define RT5671_DMIC_1_M_ASYN (0x1 << 9)
  8314. +#define RT5671_DMIC_2_M_MASK (0x1 << 8)
  8315. +#define RT5671_DMIC_2_M_SFT 8
  8316. +#define RT5671_DMIC_2_M_NOR (0x0 << 8)
  8317. +#define RT5671_DMIC_2_M_ASYN (0x1 << 8)
  8318. +
  8319. +/* ASRC Control 2 (0x84) */
  8320. +#define RT5671_MDA_L_M_MASK (0x1 << 15)
  8321. +#define RT5671_MDA_L_M_SFT 15
  8322. +#define RT5671_MDA_L_M_NOR (0x0 << 15)
  8323. +#define RT5671_MDA_L_M_ASYN (0x1 << 15)
  8324. +#define RT5671_MDA_R_M_MASK (0x1 << 14)
  8325. +#define RT5671_MDA_R_M_SFT 14
  8326. +#define RT5671_MDA_R_M_NOR (0x0 << 14)
  8327. +#define RT5671_MDA_R_M_ASYN (0x1 << 14)
  8328. +#define RT5671_MAD_L_M_MASK (0x1 << 13)
  8329. +#define RT5671_MAD_L_M_SFT 13
  8330. +#define RT5671_MAD_L_M_NOR (0x0 << 13)
  8331. +#define RT5671_MAD_L_M_ASYN (0x1 << 13)
  8332. +#define RT5671_MAD_R_M_MASK (0x1 << 12)
  8333. +#define RT5671_MAD_R_M_SFT 12
  8334. +#define RT5671_MAD_R_M_NOR (0x0 << 12)
  8335. +#define RT5671_MAD_R_M_ASYN (0x1 << 12)
  8336. +#define RT5671_ADC_M_MASK (0x1 << 11)
  8337. +#define RT5671_ADC_M_SFT 11
  8338. +#define RT5671_ADC_M_NOR (0x0 << 11)
  8339. +#define RT5671_ADC_M_ASYN (0x1 << 11)
  8340. +#define RT5671_STO_DAC_M_MASK (0x1 << 5)
  8341. +#define RT5671_STO_DAC_M_SFT 5
  8342. +#define RT5671_STO_DAC_M_NOR (0x0 << 5)
  8343. +#define RT5671_STO_DAC_M_ASYN (0x1 << 5)
  8344. +#define RT5671_I2S1_R_D_MASK (0x1 << 4)
  8345. +#define RT5671_I2S1_R_D_SFT 4
  8346. +#define RT5671_I2S1_R_D_DIS (0x0 << 4)
  8347. +#define RT5671_I2S1_R_D_EN (0x1 << 4)
  8348. +#define RT5671_I2S2_R_D_MASK (0x1 << 3)
  8349. +#define RT5671_I2S2_R_D_SFT 3
  8350. +#define RT5671_I2S2_R_D_DIS (0x0 << 3)
  8351. +#define RT5671_I2S2_R_D_EN (0x1 << 3)
  8352. +#define RT5671_PRE_SCLK_MASK (0x3)
  8353. +#define RT5671_PRE_SCLK_SFT 0
  8354. +#define RT5671_PRE_SCLK_512 (0x0)
  8355. +#define RT5671_PRE_SCLK_1024 (0x1)
  8356. +#define RT5671_PRE_SCLK_2048 (0x2)
  8357. +
  8358. +/* ASRC Control 3 (0x85) */
  8359. +#define RT5671_I2S1_RATE_MASK (0xf << 12)
  8360. +#define RT5671_I2S1_RATE_SFT 12
  8361. +#define RT5671_I2S2_RATE_MASK (0xf << 8)
  8362. +#define RT5671_I2S2_RATE_SFT 8
  8363. +
  8364. +/* ASRC Control 4 (0x89) */
  8365. +#define RT5671_I2S1_PD_MASK (0x7 << 12)
  8366. +#define RT5671_I2S1_PD_SFT 12
  8367. +#define RT5671_I2S2_PD_MASK (0x7 << 8)
  8368. +#define RT5671_I2S2_PD_SFT 8
  8369. +
  8370. +/* HPOUT Over Current Detection (0x8b) */
  8371. +#define RT5671_HP_OVCD_MASK (0x1 << 10)
  8372. +#define RT5671_HP_OVCD_SFT 10
  8373. +#define RT5671_HP_OVCD_DIS (0x0 << 10)
  8374. +#define RT5671_HP_OVCD_EN (0x1 << 10)
  8375. +#define RT5671_HP_OC_TH_MASK (0x3 << 8)
  8376. +#define RT5671_HP_OC_TH_SFT 8
  8377. +#define RT5671_HP_OC_TH_90 (0x0 << 8)
  8378. +#define RT5671_HP_OC_TH_105 (0x1 << 8)
  8379. +#define RT5671_HP_OC_TH_120 (0x2 << 8)
  8380. +#define RT5671_HP_OC_TH_135 (0x3 << 8)
  8381. +
  8382. +/* Class D Over Current Control (0x8c) */
  8383. +#define RT5671_CLSD_OC_MASK (0x1 << 9)
  8384. +#define RT5671_CLSD_OC_SFT 9
  8385. +#define RT5671_CLSD_OC_PU (0x0 << 9)
  8386. +#define RT5671_CLSD_OC_PD (0x1 << 9)
  8387. +#define RT5671_AUTO_PD_MASK (0x1 << 8)
  8388. +#define RT5671_AUTO_PD_SFT 8
  8389. +#define RT5671_AUTO_PD_DIS (0x0 << 8)
  8390. +#define RT5671_AUTO_PD_EN (0x1 << 8)
  8391. +#define RT5671_CLSD_OC_TH_MASK (0x3f)
  8392. +#define RT5671_CLSD_OC_TH_SFT 0
  8393. +
  8394. +/* Class D Output Control (0x8d) */
  8395. +#define RT5671_CLSD_RATIO_MASK (0xf << 12)
  8396. +#define RT5671_CLSD_RATIO_SFT 12
  8397. +#define RT5671_CLSD_OM_MASK (0x1 << 11)
  8398. +#define RT5671_CLSD_OM_SFT 11
  8399. +#define RT5671_CLSD_OM_MONO (0x0 << 11)
  8400. +#define RT5671_CLSD_OM_STO (0x1 << 11)
  8401. +#define RT5671_CLSD_SCH_MASK (0x1 << 10)
  8402. +#define RT5671_CLSD_SCH_SFT 10
  8403. +#define RT5671_CLSD_SCH_L (0x0 << 10)
  8404. +#define RT5671_CLSD_SCH_S (0x1 << 10)
  8405. +
  8406. +/* Depop Mode Control 1 (0x8e) */
  8407. +#define RT5671_SMT_TRIG_MASK (0x1 << 15)
  8408. +#define RT5671_SMT_TRIG_SFT 15
  8409. +#define RT5671_SMT_TRIG_DIS (0x0 << 15)
  8410. +#define RT5671_SMT_TRIG_EN (0x1 << 15)
  8411. +#define RT5671_HP_L_SMT_MASK (0x1 << 9)
  8412. +#define RT5671_HP_L_SMT_SFT 9
  8413. +#define RT5671_HP_L_SMT_DIS (0x0 << 9)
  8414. +#define RT5671_HP_L_SMT_EN (0x1 << 9)
  8415. +#define RT5671_HP_R_SMT_MASK (0x1 << 8)
  8416. +#define RT5671_HP_R_SMT_SFT 8
  8417. +#define RT5671_HP_R_SMT_DIS (0x0 << 8)
  8418. +#define RT5671_HP_R_SMT_EN (0x1 << 8)
  8419. +#define RT5671_HP_CD_PD_MASK (0x1 << 7)
  8420. +#define RT5671_HP_CD_PD_SFT 7
  8421. +#define RT5671_HP_CD_PD_DIS (0x0 << 7)
  8422. +#define RT5671_HP_CD_PD_EN (0x1 << 7)
  8423. +#define RT5671_RSTN_MASK (0x1 << 6)
  8424. +#define RT5671_RSTN_SFT 6
  8425. +#define RT5671_RSTN_DIS (0x0 << 6)
  8426. +#define RT5671_RSTN_EN (0x1 << 6)
  8427. +#define RT5671_RSTP_MASK (0x1 << 5)
  8428. +#define RT5671_RSTP_SFT 5
  8429. +#define RT5671_RSTP_DIS (0x0 << 5)
  8430. +#define RT5671_RSTP_EN (0x1 << 5)
  8431. +#define RT5671_HP_CO_MASK (0x1 << 4)
  8432. +#define RT5671_HP_CO_SFT 4
  8433. +#define RT5671_HP_CO_DIS (0x0 << 4)
  8434. +#define RT5671_HP_CO_EN (0x1 << 4)
  8435. +#define RT5671_HP_CP_MASK (0x1 << 3)
  8436. +#define RT5671_HP_CP_SFT 3
  8437. +#define RT5671_HP_CP_PD (0x0 << 3)
  8438. +#define RT5671_HP_CP_PU (0x1 << 3)
  8439. +#define RT5671_HP_SG_MASK (0x1 << 2)
  8440. +#define RT5671_HP_SG_SFT 2
  8441. +#define RT5671_HP_SG_DIS (0x0 << 2)
  8442. +#define RT5671_HP_SG_EN (0x1 << 2)
  8443. +#define RT5671_HP_DP_MASK (0x1 << 1)
  8444. +#define RT5671_HP_DP_SFT 1
  8445. +#define RT5671_HP_DP_PD (0x0 << 1)
  8446. +#define RT5671_HP_DP_PU (0x1 << 1)
  8447. +#define RT5671_HP_CB_MASK (0x1)
  8448. +#define RT5671_HP_CB_SFT 0
  8449. +#define RT5671_HP_CB_PD (0x0)
  8450. +#define RT5671_HP_CB_PU (0x1)
  8451. +
  8452. +/* Depop Mode Control 2 (0x8f) */
  8453. +#define RT5671_DEPOP_MASK (0x1 << 13)
  8454. +#define RT5671_DEPOP_SFT 13
  8455. +#define RT5671_DEPOP_AUTO (0x0 << 13)
  8456. +#define RT5671_DEPOP_MAN (0x1 << 13)
  8457. +#define RT5671_RAMP_MASK (0x1 << 12)
  8458. +#define RT5671_RAMP_SFT 12
  8459. +#define RT5671_RAMP_DIS (0x0 << 12)
  8460. +#define RT5671_RAMP_EN (0x1 << 12)
  8461. +#define RT5671_BPS_MASK (0x1 << 11)
  8462. +#define RT5671_BPS_SFT 11
  8463. +#define RT5671_BPS_DIS (0x0 << 11)
  8464. +#define RT5671_BPS_EN (0x1 << 11)
  8465. +#define RT5671_FAST_UPDN_MASK (0x1 << 10)
  8466. +#define RT5671_FAST_UPDN_SFT 10
  8467. +#define RT5671_FAST_UPDN_DIS (0x0 << 10)
  8468. +#define RT5671_FAST_UPDN_EN (0x1 << 10)
  8469. +#define RT5671_MRES_MASK (0x3 << 8)
  8470. +#define RT5671_MRES_SFT 8
  8471. +#define RT5671_MRES_15MO (0x0 << 8)
  8472. +#define RT5671_MRES_25MO (0x1 << 8)
  8473. +#define RT5671_MRES_35MO (0x2 << 8)
  8474. +#define RT5671_MRES_45MO (0x3 << 8)
  8475. +#define RT5671_VLO_MASK (0x1 << 7)
  8476. +#define RT5671_VLO_SFT 7
  8477. +#define RT5671_VLO_3V (0x0 << 7)
  8478. +#define RT5671_VLO_32V (0x1 << 7)
  8479. +#define RT5671_DIG_DP_MASK (0x1 << 6)
  8480. +#define RT5671_DIG_DP_SFT 6
  8481. +#define RT5671_DIG_DP_DIS (0x0 << 6)
  8482. +#define RT5671_DIG_DP_EN (0x1 << 6)
  8483. +#define RT5671_DP_TH_MASK (0x3 << 4)
  8484. +#define RT5671_DP_TH_SFT 4
  8485. +
  8486. +/* Depop Mode Control 3 (0x90) */
  8487. +#define RT5671_CP_SYS_MASK (0x7 << 12)
  8488. +#define RT5671_CP_SYS_SFT 12
  8489. +#define RT5671_CP_FQ1_MASK (0x7 << 8)
  8490. +#define RT5671_CP_FQ1_SFT 8
  8491. +#define RT5671_CP_FQ2_MASK (0x7 << 4)
  8492. +#define RT5671_CP_FQ2_SFT 4
  8493. +#define RT5671_CP_FQ3_MASK (0x7)
  8494. +#define RT5671_CP_FQ3_SFT 0
  8495. +#define RT5671_CP_FQ_1_5_KHZ 0
  8496. +#define RT5671_CP_FQ_3_KHZ 1
  8497. +#define RT5671_CP_FQ_6_KHZ 2
  8498. +#define RT5671_CP_FQ_12_KHZ 3
  8499. +#define RT5671_CP_FQ_24_KHZ 4
  8500. +#define RT5671_CP_FQ_48_KHZ 5
  8501. +#define RT5671_CP_FQ_96_KHZ 6
  8502. +#define RT5671_CP_FQ_192_KHZ 7
  8503. +
  8504. +/* HPOUT charge pump (0x91) */
  8505. +#define RT5671_OSW_L_MASK (0x1 << 11)
  8506. +#define RT5671_OSW_L_SFT 11
  8507. +#define RT5671_OSW_L_DIS (0x0 << 11)
  8508. +#define RT5671_OSW_L_EN (0x1 << 11)
  8509. +#define RT5671_OSW_R_MASK (0x1 << 10)
  8510. +#define RT5671_OSW_R_SFT 10
  8511. +#define RT5671_OSW_R_DIS (0x0 << 10)
  8512. +#define RT5671_OSW_R_EN (0x1 << 10)
  8513. +#define RT5671_PM_HP_MASK (0x3 << 8)
  8514. +#define RT5671_PM_HP_SFT 8
  8515. +#define RT5671_PM_HP_LV (0x0 << 8)
  8516. +#define RT5671_PM_HP_MV (0x1 << 8)
  8517. +#define RT5671_PM_HP_HV (0x2 << 8)
  8518. +#define RT5671_IB_HP_MASK (0x3 << 6)
  8519. +#define RT5671_IB_HP_SFT 6
  8520. +#define RT5671_IB_HP_125IL (0x0 << 6)
  8521. +#define RT5671_IB_HP_25IL (0x1 << 6)
  8522. +#define RT5671_IB_HP_5IL (0x2 << 6)
  8523. +#define RT5671_IB_HP_1IL (0x3 << 6)
  8524. +
  8525. +/* PV detection and SPK gain control (0x92) */
  8526. +#define RT5671_PVDD_DET_MASK (0x1 << 15)
  8527. +#define RT5671_PVDD_DET_SFT 15
  8528. +#define RT5671_PVDD_DET_DIS (0x0 << 15)
  8529. +#define RT5671_PVDD_DET_EN (0x1 << 15)
  8530. +#define RT5671_SPK_AG_MASK (0x1 << 14)
  8531. +#define RT5671_SPK_AG_SFT 14
  8532. +#define RT5671_SPK_AG_DIS (0x0 << 14)
  8533. +#define RT5671_SPK_AG_EN (0x1 << 14)
  8534. +
  8535. +/* Micbias Control (0x93) */
  8536. +#define RT5671_MIC1_BS_MASK (0x1 << 15)
  8537. +#define RT5671_MIC1_BS_SFT 15
  8538. +#define RT5671_MIC1_BS_9AV (0x0 << 15)
  8539. +#define RT5671_MIC1_BS_75AV (0x1 << 15)
  8540. +#define RT5671_MIC2_BS_MASK (0x1 << 14)
  8541. +#define RT5671_MIC2_BS_SFT 14
  8542. +#define RT5671_MIC2_BS_9AV (0x0 << 14)
  8543. +#define RT5671_MIC2_BS_75AV (0x1 << 14)
  8544. +#define RT5671_MIC1_CLK_MASK (0x1 << 13)
  8545. +#define RT5671_MIC1_CLK_SFT 13
  8546. +#define RT5671_MIC1_CLK_DIS (0x0 << 13)
  8547. +#define RT5671_MIC1_CLK_EN (0x1 << 13)
  8548. +#define RT5671_MIC2_CLK_MASK (0x1 << 12)
  8549. +#define RT5671_MIC2_CLK_SFT 12
  8550. +#define RT5671_MIC2_CLK_DIS (0x0 << 12)
  8551. +#define RT5671_MIC2_CLK_EN (0x1 << 12)
  8552. +#define RT5671_MIC1_OVCD_MASK (0x1 << 11)
  8553. +#define RT5671_MIC1_OVCD_SFT 11
  8554. +#define RT5671_MIC1_OVCD_DIS (0x0 << 11)
  8555. +#define RT5671_MIC1_OVCD_EN (0x1 << 11)
  8556. +#define RT5671_MIC1_OVTH_MASK (0x3 << 9)
  8557. +#define RT5671_MIC1_OVTH_SFT 9
  8558. +#define RT5671_MIC1_OVTH_600UA (0x0 << 9)
  8559. +#define RT5671_MIC1_OVTH_1500UA (0x1 << 9)
  8560. +#define RT5671_MIC1_OVTH_2000UA (0x2 << 9)
  8561. +#define RT5671_MIC2_OVCD_MASK (0x1 << 8)
  8562. +#define RT5671_MIC2_OVCD_SFT 8
  8563. +#define RT5671_MIC2_OVCD_DIS (0x0 << 8)
  8564. +#define RT5671_MIC2_OVCD_EN (0x1 << 8)
  8565. +#define RT5671_MIC2_OVTH_MASK (0x3 << 6)
  8566. +#define RT5671_MIC2_OVTH_SFT 6
  8567. +#define RT5671_MIC2_OVTH_600UA (0x0 << 6)
  8568. +#define RT5671_MIC2_OVTH_1500UA (0x1 << 6)
  8569. +#define RT5671_MIC2_OVTH_2000UA (0x2 << 6)
  8570. +#define RT5671_PWR_MB_MASK (0x1 << 5)
  8571. +#define RT5671_PWR_MB_SFT 5
  8572. +#define RT5671_PWR_MB_PD (0x0 << 5)
  8573. +#define RT5671_PWR_MB_PU (0x1 << 5)
  8574. +#define RT5671_PWR_CLK25M_MASK (0x1 << 4)
  8575. +#define RT5671_PWR_CLK25M_SFT 4
  8576. +#define RT5671_PWR_CLK25M_PD (0x0 << 4)
  8577. +#define RT5671_PWR_CLK25M_PU (0x1 << 4)
  8578. +
  8579. +/* VAD Control 4 (0x9d) */
  8580. +#define RT5671_VAD_SEL_MASK (0x3 << 8)
  8581. +#define RT5671_VAD_SEL_SFT 8
  8582. +
  8583. +/* EQ Control 1 (0xb0) */
  8584. +#define RT5671_EQ_SRC_MASK (0x1 << 15)
  8585. +#define RT5671_EQ_SRC_SFT 15
  8586. +#define RT5671_EQ_SRC_DAC (0x0 << 15)
  8587. +#define RT5671_EQ_SRC_ADC (0x1 << 15)
  8588. +#define RT5671_EQ_UPD (0x1 << 14)
  8589. +#define RT5671_EQ_UPD_BIT 14
  8590. +#define RT5671_EQ_CD_MASK (0x1 << 13)
  8591. +#define RT5671_EQ_CD_SFT 13
  8592. +#define RT5671_EQ_CD_DIS (0x0 << 13)
  8593. +#define RT5671_EQ_CD_EN (0x1 << 13)
  8594. +#define RT5671_EQ_DITH_MASK (0x3 << 8)
  8595. +#define RT5671_EQ_DITH_SFT 8
  8596. +#define RT5671_EQ_DITH_NOR (0x0 << 8)
  8597. +#define RT5671_EQ_DITH_LSB (0x1 << 8)
  8598. +#define RT5671_EQ_DITH_LSB_1 (0x2 << 8)
  8599. +#define RT5671_EQ_DITH_LSB_2 (0x3 << 8)
  8600. +
  8601. +/* EQ Control 2 (0xb1) */
  8602. +#define RT5671_EQ_HPF1_M_MASK (0x1 << 8)
  8603. +#define RT5671_EQ_HPF1_M_SFT 8
  8604. +#define RT5671_EQ_HPF1_M_HI (0x0 << 8)
  8605. +#define RT5671_EQ_HPF1_M_1ST (0x1 << 8)
  8606. +#define RT5671_EQ_LPF1_M_MASK (0x1 << 7)
  8607. +#define RT5671_EQ_LPF1_M_SFT 7
  8608. +#define RT5671_EQ_LPF1_M_LO (0x0 << 7)
  8609. +#define RT5671_EQ_LPF1_M_1ST (0x1 << 7)
  8610. +#define RT5671_EQ_HPF2_MASK (0x1 << 6)
  8611. +#define RT5671_EQ_HPF2_SFT 6
  8612. +#define RT5671_EQ_HPF2_DIS (0x0 << 6)
  8613. +#define RT5671_EQ_HPF2_EN (0x1 << 6)
  8614. +#define RT5671_EQ_HPF1_MASK (0x1 << 5)
  8615. +#define RT5671_EQ_HPF1_SFT 5
  8616. +#define RT5671_EQ_HPF1_DIS (0x0 << 5)
  8617. +#define RT5671_EQ_HPF1_EN (0x1 << 5)
  8618. +#define RT5671_EQ_BPF4_MASK (0x1 << 4)
  8619. +#define RT5671_EQ_BPF4_SFT 4
  8620. +#define RT5671_EQ_BPF4_DIS (0x0 << 4)
  8621. +#define RT5671_EQ_BPF4_EN (0x1 << 4)
  8622. +#define RT5671_EQ_BPF3_MASK (0x1 << 3)
  8623. +#define RT5671_EQ_BPF3_SFT 3
  8624. +#define RT5671_EQ_BPF3_DIS (0x0 << 3)
  8625. +#define RT5671_EQ_BPF3_EN (0x1 << 3)
  8626. +#define RT5671_EQ_BPF2_MASK (0x1 << 2)
  8627. +#define RT5671_EQ_BPF2_SFT 2
  8628. +#define RT5671_EQ_BPF2_DIS (0x0 << 2)
  8629. +#define RT5671_EQ_BPF2_EN (0x1 << 2)
  8630. +#define RT5671_EQ_BPF1_MASK (0x1 << 1)
  8631. +#define RT5671_EQ_BPF1_SFT 1
  8632. +#define RT5671_EQ_BPF1_DIS (0x0 << 1)
  8633. +#define RT5671_EQ_BPF1_EN (0x1 << 1)
  8634. +#define RT5671_EQ_LPF_MASK (0x1)
  8635. +#define RT5671_EQ_LPF_SFT 0
  8636. +#define RT5671_EQ_LPF_DIS (0x0)
  8637. +#define RT5671_EQ_LPF_EN (0x1)
  8638. +#define RT5671_EQ_CTRL_MASK (0x7f)
  8639. +
  8640. +/* Memory Test (0xb2) */
  8641. +#define RT5671_MT_MASK (0x1 << 15)
  8642. +#define RT5671_MT_SFT 15
  8643. +#define RT5671_MT_DIS (0x0 << 15)
  8644. +#define RT5671_MT_EN (0x1 << 15)
  8645. +
  8646. +/* DRC/AGC Control 1 (0xb4) */
  8647. +#define RT5671_DRC_AGC_P_MASK (0x1 << 15)
  8648. +#define RT5671_DRC_AGC_P_SFT 15
  8649. +#define RT5671_DRC_AGC_P_DAC (0x0 << 15)
  8650. +#define RT5671_DRC_AGC_P_ADC (0x1 << 15)
  8651. +#define RT5671_DRC_AGC_MASK (0x1 << 14)
  8652. +#define RT5671_DRC_AGC_SFT 14
  8653. +#define RT5671_DRC_AGC_DIS (0x0 << 14)
  8654. +#define RT5671_DRC_AGC_EN (0x1 << 14)
  8655. +#define RT5671_DRC_AGC_UPD (0x1 << 13)
  8656. +#define RT5671_DRC_AGC_UPD_BIT 13
  8657. +#define RT5671_DRC_AGC_AR_MASK (0x1f << 8)
  8658. +#define RT5671_DRC_AGC_AR_SFT 8
  8659. +#define RT5671_DRC_AGC_R_MASK (0x7 << 5)
  8660. +#define RT5671_DRC_AGC_R_SFT 5
  8661. +#define RT5671_DRC_AGC_R_48K (0x1 << 5)
  8662. +#define RT5671_DRC_AGC_R_96K (0x2 << 5)
  8663. +#define RT5671_DRC_AGC_R_192K (0x3 << 5)
  8664. +#define RT5671_DRC_AGC_R_441K (0x5 << 5)
  8665. +#define RT5671_DRC_AGC_R_882K (0x6 << 5)
  8666. +#define RT5671_DRC_AGC_R_1764K (0x7 << 5)
  8667. +#define RT5671_DRC_AGC_RC_MASK (0x1f)
  8668. +#define RT5671_DRC_AGC_RC_SFT 0
  8669. +
  8670. +/* DRC/AGC Control 2 (0xb5) */
  8671. +#define RT5671_DRC_AGC_POB_MASK (0x3f << 8)
  8672. +#define RT5671_DRC_AGC_POB_SFT 8
  8673. +#define RT5671_DRC_AGC_CP_MASK (0x1 << 7)
  8674. +#define RT5671_DRC_AGC_CP_SFT 7
  8675. +#define RT5671_DRC_AGC_CP_DIS (0x0 << 7)
  8676. +#define RT5671_DRC_AGC_CP_EN (0x1 << 7)
  8677. +#define RT5671_DRC_AGC_CPR_MASK (0x3 << 5)
  8678. +#define RT5671_DRC_AGC_CPR_SFT 5
  8679. +#define RT5671_DRC_AGC_CPR_1_1 (0x0 << 5)
  8680. +#define RT5671_DRC_AGC_CPR_1_2 (0x1 << 5)
  8681. +#define RT5671_DRC_AGC_CPR_1_3 (0x2 << 5)
  8682. +#define RT5671_DRC_AGC_CPR_1_4 (0x3 << 5)
  8683. +#define RT5671_DRC_AGC_PRB_MASK (0x1f)
  8684. +#define RT5671_DRC_AGC_PRB_SFT 0
  8685. +
  8686. +/* DRC/AGC Control 3 (0xb6) */
  8687. +#define RT5671_DRC_AGC_NGB_MASK (0xf << 12)
  8688. +#define RT5671_DRC_AGC_NGB_SFT 12
  8689. +#define RT5671_DRC_AGC_TAR_MASK (0x1f << 7)
  8690. +#define RT5671_DRC_AGC_TAR_SFT 7
  8691. +#define RT5671_DRC_AGC_NG_MASK (0x1 << 6)
  8692. +#define RT5671_DRC_AGC_NG_SFT 6
  8693. +#define RT5671_DRC_AGC_NG_DIS (0x0 << 6)
  8694. +#define RT5671_DRC_AGC_NG_EN (0x1 << 6)
  8695. +#define RT5671_DRC_AGC_NGH_MASK (0x1 << 5)
  8696. +#define RT5671_DRC_AGC_NGH_SFT 5
  8697. +#define RT5671_DRC_AGC_NGH_DIS (0x0 << 5)
  8698. +#define RT5671_DRC_AGC_NGH_EN (0x1 << 5)
  8699. +#define RT5671_DRC_AGC_NGT_MASK (0x1f)
  8700. +#define RT5671_DRC_AGC_NGT_SFT 0
  8701. +
  8702. +/* Jack Detect Control (0xbb) */
  8703. +#define RT5671_JD_MASK (0x7 << 13)
  8704. +#define RT5671_JD_SFT 13
  8705. +#define RT5671_JD_DIS (0x0 << 13)
  8706. +#define RT5671_JD_GPIO1 (0x1 << 13)
  8707. +#define RT5671_JD_JD1_IN4P (0x2 << 13)
  8708. +#define RT5671_JD_JD2_IN4N (0x3 << 13)
  8709. +#define RT5671_JD_GPIO2 (0x4 << 13)
  8710. +#define RT5671_JD_GPIO3 (0x5 << 13)
  8711. +#define RT5671_JD_GPIO4 (0x6 << 13)
  8712. +#define RT5671_JD_HP_MASK (0x1 << 11)
  8713. +#define RT5671_JD_HP_SFT 11
  8714. +#define RT5671_JD_HP_DIS (0x0 << 11)
  8715. +#define RT5671_JD_HP_EN (0x1 << 11)
  8716. +#define RT5671_JD_HP_TRG_MASK (0x1 << 10)
  8717. +#define RT5671_JD_HP_TRG_SFT 10
  8718. +#define RT5671_JD_HP_TRG_LO (0x0 << 10)
  8719. +#define RT5671_JD_HP_TRG_HI (0x1 << 10)
  8720. +#define RT5671_JD_SPL_MASK (0x1 << 9)
  8721. +#define RT5671_JD_SPL_SFT 9
  8722. +#define RT5671_JD_SPL_DIS (0x0 << 9)
  8723. +#define RT5671_JD_SPL_EN (0x1 << 9)
  8724. +#define RT5671_JD_SPL_TRG_MASK (0x1 << 8)
  8725. +#define RT5671_JD_SPL_TRG_SFT 8
  8726. +#define RT5671_JD_SPL_TRG_LO (0x0 << 8)
  8727. +#define RT5671_JD_SPL_TRG_HI (0x1 << 8)
  8728. +#define RT5671_JD_SPR_MASK (0x1 << 7)
  8729. +#define RT5671_JD_SPR_SFT 7
  8730. +#define RT5671_JD_SPR_DIS (0x0 << 7)
  8731. +#define RT5671_JD_SPR_EN (0x1 << 7)
  8732. +#define RT5671_JD_SPR_TRG_MASK (0x1 << 6)
  8733. +#define RT5671_JD_SPR_TRG_SFT 6
  8734. +#define RT5671_JD_SPR_TRG_LO (0x0 << 6)
  8735. +#define RT5671_JD_SPR_TRG_HI (0x1 << 6)
  8736. +#define RT5671_JD_MO_MASK (0x1 << 5)
  8737. +#define RT5671_JD_MO_SFT 5
  8738. +#define RT5671_JD_MO_DIS (0x0 << 5)
  8739. +#define RT5671_JD_MO_EN (0x1 << 5)
  8740. +#define RT5671_JD_MO_TRG_MASK (0x1 << 4)
  8741. +#define RT5671_JD_MO_TRG_SFT 4
  8742. +#define RT5671_JD_MO_TRG_LO (0x0 << 4)
  8743. +#define RT5671_JD_MO_TRG_HI (0x1 << 4)
  8744. +#define RT5671_JD_LO_MASK (0x1 << 3)
  8745. +#define RT5671_JD_LO_SFT 3
  8746. +#define RT5671_JD_LO_DIS (0x0 << 3)
  8747. +#define RT5671_JD_LO_EN (0x1 << 3)
  8748. +#define RT5671_JD_LO_TRG_MASK (0x1 << 2)
  8749. +#define RT5671_JD_LO_TRG_SFT 2
  8750. +#define RT5671_JD_LO_TRG_LO (0x0 << 2)
  8751. +#define RT5671_JD_LO_TRG_HI (0x1 << 2)
  8752. +#define RT5671_JD1_IN4P_MASK (0x1 << 1)
  8753. +#define RT5671_JD1_IN4P_SFT 1
  8754. +#define RT5671_JD1_IN4P_DIS (0x0 << 1)
  8755. +#define RT5671_JD1_IN4P_EN (0x1 << 1)
  8756. +#define RT5671_JD2_IN4N_MASK (0x1)
  8757. +#define RT5671_JD2_IN4N_SFT 0
  8758. +#define RT5671_JD2_IN4N_DIS (0x0)
  8759. +#define RT5671_JD2_IN4N_EN (0x1)
  8760. +
  8761. +/* IRQ Control 1 (0xbd) */
  8762. +#define RT5671_IRQ_JD_MASK (0x1 << 15)
  8763. +#define RT5671_IRQ_JD_SFT 15
  8764. +#define RT5671_IRQ_JD_BP (0x0 << 15)
  8765. +#define RT5671_IRQ_JD_NOR (0x1 << 15)
  8766. +#define RT5671_IRQ_OT_MASK (0x1 << 14)
  8767. +#define RT5671_IRQ_OT_SFT 14
  8768. +#define RT5671_IRQ_OT_BP (0x0 << 14)
  8769. +#define RT5671_IRQ_OT_NOR (0x1 << 14)
  8770. +#define RT5671_JD_STKY_MASK (0x1 << 13)
  8771. +#define RT5671_JD_STKY_SFT 13
  8772. +#define RT5671_JD_STKY_DIS (0x0 << 13)
  8773. +#define RT5671_JD_STKY_EN (0x1 << 13)
  8774. +#define RT5671_OT_STKY_MASK (0x1 << 12)
  8775. +#define RT5671_OT_STKY_SFT 12
  8776. +#define RT5671_OT_STKY_DIS (0x0 << 12)
  8777. +#define RT5671_OT_STKY_EN (0x1 << 12)
  8778. +#define RT5671_JD_P_MASK (0x1 << 11)
  8779. +#define RT5671_JD_P_SFT 11
  8780. +#define RT5671_JD_P_NOR (0x0 << 11)
  8781. +#define RT5671_JD_P_INV (0x1 << 11)
  8782. +#define RT5671_OT_P_MASK (0x1 << 10)
  8783. +#define RT5671_OT_P_SFT 10
  8784. +#define RT5671_OT_P_NOR (0x0 << 10)
  8785. +#define RT5671_OT_P_INV (0x1 << 10)
  8786. +
  8787. +/* IRQ Control 2 (0xbe) */
  8788. +#define RT5671_IRQ_MB1_OC_MASK (0x1 << 15)
  8789. +#define RT5671_IRQ_MB1_OC_SFT 15
  8790. +#define RT5671_IRQ_MB1_OC_BP (0x0 << 15)
  8791. +#define RT5671_IRQ_MB1_OC_NOR (0x1 << 15)
  8792. +#define RT5671_IRQ_MB2_OC_MASK (0x1 << 14)
  8793. +#define RT5671_IRQ_MB2_OC_SFT 14
  8794. +#define RT5671_IRQ_MB2_OC_BP (0x0 << 14)
  8795. +#define RT5671_IRQ_MB2_OC_NOR (0x1 << 14)
  8796. +#define RT5671_MB1_OC_STKY_MASK (0x1 << 11)
  8797. +#define RT5671_MB1_OC_STKY_SFT 11
  8798. +#define RT5671_MB1_OC_STKY_DIS (0x0 << 11)
  8799. +#define RT5671_MB1_OC_STKY_EN (0x1 << 11)
  8800. +#define RT5671_MB2_OC_STKY_MASK (0x1 << 10)
  8801. +#define RT5671_MB2_OC_STKY_SFT 10
  8802. +#define RT5671_MB2_OC_STKY_DIS (0x0 << 10)
  8803. +#define RT5671_MB2_OC_STKY_EN (0x1 << 10)
  8804. +#define RT5671_MB1_OC_P_MASK (0x1 << 7)
  8805. +#define RT5671_MB1_OC_P_SFT 7
  8806. +#define RT5671_MB1_OC_P_NOR (0x0 << 7)
  8807. +#define RT5671_MB1_OC_P_INV (0x1 << 7)
  8808. +#define RT5671_MB2_OC_P_MASK (0x1 << 6)
  8809. +#define RT5671_MB2_OC_P_SFT 6
  8810. +#define RT5671_MB2_OC_P_NOR (0x0 << 6)
  8811. +#define RT5671_MB2_OC_P_INV (0x1 << 6)
  8812. +#define RT5671_MB1_OC_CLR (0x1 << 3)
  8813. +#define RT5671_MB1_OC_CLR_SFT 3
  8814. +#define RT5671_MB2_OC_CLR (0x1 << 2)
  8815. +#define RT5671_MB2_OC_CLR_SFT 2
  8816. +
  8817. +/* GPIO Control 1 (0xc0) */
  8818. +#define RT5671_GP1_PIN_MASK (0x1 << 15)
  8819. +#define RT5671_GP1_PIN_SFT 15
  8820. +#define RT5671_GP1_PIN_GPIO1 (0x0 << 15)
  8821. +#define RT5671_GP1_PIN_IRQ (0x1 << 15)
  8822. +#define RT5671_GP2_PIN_MASK (0x1 << 14)
  8823. +#define RT5671_GP2_PIN_SFT 14
  8824. +#define RT5671_GP2_PIN_GPIO2 (0x0 << 14)
  8825. +#define RT5671_GP2_PIN_DMIC1_SCL (0x1 << 14)
  8826. +#define RT5671_GP3_PIN_MASK (0x3 << 12)
  8827. +#define RT5671_GP3_PIN_SFT 12
  8828. +#define RT5671_GP3_PIN_GPIO3 (0x0 << 12)
  8829. +#define RT5671_GP3_PIN_DMIC1_SDA (0x1 << 12)
  8830. +#define RT5671_GP3_PIN_IRQ (0x2 << 12)
  8831. +#define RT5671_GP4_PIN_MASK (0x1 << 11)
  8832. +#define RT5671_GP4_PIN_SFT 11
  8833. +#define RT5671_GP4_PIN_GPIO4 (0x0 << 11)
  8834. +#define RT5671_GP4_PIN_DMIC2_SDA (0x1 << 11)
  8835. +#define RT5671_DP_SIG_MASK (0x1 << 10)
  8836. +#define RT5671_DP_SIG_SFT 10
  8837. +#define RT5671_DP_SIG_TEST (0x0 << 10)
  8838. +#define RT5671_DP_SIG_AP (0x1 << 10)
  8839. +#define RT5671_GPIO_M_MASK (0x1 << 9)
  8840. +#define RT5671_GPIO_M_SFT 9
  8841. +#define RT5671_GPIO_M_FLT (0x0 << 9)
  8842. +#define RT5671_GPIO_M_PH (0x1 << 9)
  8843. +#define RT5671_I2S2_PIN_MASK (0x1 << 8)
  8844. +#define RT5671_I2S2_PIN_SFT 8
  8845. +#define RT5671_I2S2_PIN_I2S (0x0 << 8)
  8846. +#define RT5671_I2S2_PIN_GPIO (0x1 << 8)
  8847. +#define RT5671_GP5_PIN_MASK (0x1 << 7)
  8848. +#define RT5671_GP5_PIN_SFT 7
  8849. +#define RT5671_GP5_PIN_GPIO5 (0x0 << 7)
  8850. +#define RT5671_GP5_PIN_DMIC3_SCL (0x1 << 7)
  8851. +#define RT5671_GP6_PIN_MASK (0x1 << 6)
  8852. +#define RT5671_GP6_PIN_SFT 6
  8853. +#define RT5671_GP6_PIN_GPIO6 (0x0 << 6)
  8854. +#define RT5671_GP6_PIN_DMIC1_SDA (0x1 << 6)
  8855. +#define RT5671_GP7_PIN_MASK (0x3 << 4)
  8856. +#define RT5671_GP7_PIN_SFT 4
  8857. +#define RT5671_GP7_PIN_GPIO7 (0x0 << 4)
  8858. +#define RT5671_GP7_PIN_DMIC1_SDA (0x1 << 4)
  8859. +#define RT5671_GP7_PIN_PDM_SCL2 (0x2 << 4)
  8860. +#define RT5671_GP8_PIN_MASK (0x1 << 3)
  8861. +#define RT5671_GP8_PIN_SFT 3
  8862. +#define RT5671_GP8_PIN_GPIO8 (0x0 << 3)
  8863. +#define RT5671_GP8_PIN_DMIC2_SDA (0x1 << 3)
  8864. +#define RT5671_GP9_PIN_MASK (0x1 << 2)
  8865. +#define RT5671_GP9_PIN_SFT 2
  8866. +#define RT5671_GP9_PIN_GPIO9 (0x0 << 2)
  8867. +#define RT5671_GP9_PIN_DMIC3_SDA (0x1 << 2)
  8868. +#define RT5671_GP10_PIN_MASK (0x3)
  8869. +#define RT5671_GP10_PIN_SFT 0
  8870. +#define RT5671_GP10_PIN_GPIO9 (0x0)
  8871. +#define RT5671_GP10_PIN_DMIC3_SDA (0x1)
  8872. +#define RT5671_GP10_PIN_PDM_ADT2 (0x2)
  8873. +
  8874. +/* GPIO Control 3 (0xc2) */
  8875. +#define RT5671_GP4_PF_MASK (0x1 << 11)
  8876. +#define RT5671_GP4_PF_SFT 11
  8877. +#define RT5671_GP4_PF_IN (0x0 << 11)
  8878. +#define RT5671_GP4_PF_OUT (0x1 << 11)
  8879. +#define RT5671_GP4_OUT_MASK (0x1 << 10)
  8880. +#define RT5671_GP4_OUT_SFT 10
  8881. +#define RT5671_GP4_OUT_LO (0x0 << 10)
  8882. +#define RT5671_GP4_OUT_HI (0x1 << 10)
  8883. +#define RT5671_GP4_P_MASK (0x1 << 9)
  8884. +#define RT5671_GP4_P_SFT 9
  8885. +#define RT5671_GP4_P_NOR (0x0 << 9)
  8886. +#define RT5671_GP4_P_INV (0x1 << 9)
  8887. +#define RT5671_GP3_PF_MASK (0x1 << 8)
  8888. +#define RT5671_GP3_PF_SFT 8
  8889. +#define RT5671_GP3_PF_IN (0x0 << 8)
  8890. +#define RT5671_GP3_PF_OUT (0x1 << 8)
  8891. +#define RT5671_GP3_OUT_MASK (0x1 << 7)
  8892. +#define RT5671_GP3_OUT_SFT 7
  8893. +#define RT5671_GP3_OUT_LO (0x0 << 7)
  8894. +#define RT5671_GP3_OUT_HI (0x1 << 7)
  8895. +#define RT5671_GP3_P_MASK (0x1 << 6)
  8896. +#define RT5671_GP3_P_SFT 6
  8897. +#define RT5671_GP3_P_NOR (0x0 << 6)
  8898. +#define RT5671_GP3_P_INV (0x1 << 6)
  8899. +#define RT5671_GP2_PF_MASK (0x1 << 5)
  8900. +#define RT5671_GP2_PF_SFT 5
  8901. +#define RT5671_GP2_PF_IN (0x0 << 5)
  8902. +#define RT5671_GP2_PF_OUT (0x1 << 5)
  8903. +#define RT5671_GP2_OUT_MASK (0x1 << 4)
  8904. +#define RT5671_GP2_OUT_SFT 4
  8905. +#define RT5671_GP2_OUT_LO (0x0 << 4)
  8906. +#define RT5671_GP2_OUT_HI (0x1 << 4)
  8907. +#define RT5671_GP2_P_MASK (0x1 << 3)
  8908. +#define RT5671_GP2_P_SFT 3
  8909. +#define RT5671_GP2_P_NOR (0x0 << 3)
  8910. +#define RT5671_GP2_P_INV (0x1 << 3)
  8911. +#define RT5671_GP1_PF_MASK (0x1 << 2)
  8912. +#define RT5671_GP1_PF_SFT 2
  8913. +#define RT5671_GP1_PF_IN (0x0 << 2)
  8914. +#define RT5671_GP1_PF_OUT (0x1 << 2)
  8915. +#define RT5671_GP1_OUT_MASK (0x1 << 1)
  8916. +#define RT5671_GP1_OUT_SFT 1
  8917. +#define RT5671_GP1_OUT_LO (0x0 << 1)
  8918. +#define RT5671_GP1_OUT_HI (0x1 << 1)
  8919. +#define RT5671_GP1_P_MASK (0x1)
  8920. +#define RT5671_GP1_P_SFT 0
  8921. +#define RT5671_GP1_P_NOR (0x0)
  8922. +#define RT5671_GP1_P_INV (0x1)
  8923. +
  8924. +/* Scramble Function (0xcd) */
  8925. +#define RT5671_SCB_KEY_MASK (0xff)
  8926. +#define RT5671_SCB_KEY_SFT 0
  8927. +
  8928. +/* Scramble Control (0xce) */
  8929. +#define RT5671_SCB_SWAP_MASK (0x1 << 15)
  8930. +#define RT5671_SCB_SWAP_SFT 15
  8931. +#define RT5671_SCB_SWAP_DIS (0x0 << 15)
  8932. +#define RT5671_SCB_SWAP_EN (0x1 << 15)
  8933. +#define RT5671_SCB_MASK (0x1 << 14)
  8934. +#define RT5671_SCB_SFT 14
  8935. +#define RT5671_SCB_DIS (0x0 << 14)
  8936. +#define RT5671_SCB_EN (0x1 << 14)
  8937. +
  8938. +/* Baseback Control (0xcf) */
  8939. +#define RT5671_BB_MASK (0x1 << 15)
  8940. +#define RT5671_BB_SFT 15
  8941. +#define RT5671_BB_DIS (0x0 << 15)
  8942. +#define RT5671_BB_EN (0x1 << 15)
  8943. +#define RT5671_BB_CT_MASK (0x7 << 12)
  8944. +#define RT5671_BB_CT_SFT 12
  8945. +#define RT5671_BB_CT_A (0x0 << 12)
  8946. +#define RT5671_BB_CT_B (0x1 << 12)
  8947. +#define RT5671_BB_CT_C (0x2 << 12)
  8948. +#define RT5671_BB_CT_D (0x3 << 12)
  8949. +#define RT5671_M_BB_L_MASK (0x1 << 9)
  8950. +#define RT5671_M_BB_L_SFT 9
  8951. +#define RT5671_M_BB_R_MASK (0x1 << 8)
  8952. +#define RT5671_M_BB_R_SFT 8
  8953. +#define RT5671_M_BB_HPF_L_MASK (0x1 << 7)
  8954. +#define RT5671_M_BB_HPF_L_SFT 7
  8955. +#define RT5671_M_BB_HPF_R_MASK (0x1 << 6)
  8956. +#define RT5671_M_BB_HPF_R_SFT 6
  8957. +#define RT5671_G_BB_BST_MASK (0x3f)
  8958. +#define RT5671_G_BB_BST_SFT 0
  8959. +
  8960. +/* MP3 Plus Control 1 (0xd0) */
  8961. +#define RT5671_M_MP3_L_MASK (0x1 << 15)
  8962. +#define RT5671_M_MP3_L_SFT 15
  8963. +#define RT5671_M_MP3_R_MASK (0x1 << 14)
  8964. +#define RT5671_M_MP3_R_SFT 14
  8965. +#define RT5671_M_MP3_MASK (0x1 << 13)
  8966. +#define RT5671_M_MP3_SFT 13
  8967. +#define RT5671_M_MP3_DIS (0x0 << 13)
  8968. +#define RT5671_M_MP3_EN (0x1 << 13)
  8969. +#define RT5671_EG_MP3_MASK (0x1f << 8)
  8970. +#define RT5671_EG_MP3_SFT 8
  8971. +#define RT5671_MP3_HLP_MASK (0x1 << 7)
  8972. +#define RT5671_MP3_HLP_SFT 7
  8973. +#define RT5671_MP3_HLP_DIS (0x0 << 7)
  8974. +#define RT5671_MP3_HLP_EN (0x1 << 7)
  8975. +#define RT5671_M_MP3_ORG_L_MASK (0x1 << 6)
  8976. +#define RT5671_M_MP3_ORG_L_SFT 6
  8977. +#define RT5671_M_MP3_ORG_R_MASK (0x1 << 5)
  8978. +#define RT5671_M_MP3_ORG_R_SFT 5
  8979. +
  8980. +/* MP3 Plus Control 2 (0xd1) */
  8981. +#define RT5671_MP3_WT_MASK (0x1 << 13)
  8982. +#define RT5671_MP3_WT_SFT 13
  8983. +#define RT5671_MP3_WT_1_4 (0x0 << 13)
  8984. +#define RT5671_MP3_WT_1_2 (0x1 << 13)
  8985. +#define RT5671_OG_MP3_MASK (0x1f << 8)
  8986. +#define RT5671_OG_MP3_SFT 8
  8987. +#define RT5671_HG_MP3_MASK (0x3f)
  8988. +#define RT5671_HG_MP3_SFT 0
  8989. +
  8990. +/* 3D HP Control 1 (0xd2) */
  8991. +#define RT5671_3D_CF_MASK (0x1 << 15)
  8992. +#define RT5671_3D_CF_SFT 15
  8993. +#define RT5671_3D_CF_DIS (0x0 << 15)
  8994. +#define RT5671_3D_CF_EN (0x1 << 15)
  8995. +#define RT5671_3D_HP_MASK (0x1 << 14)
  8996. +#define RT5671_3D_HP_SFT 14
  8997. +#define RT5671_3D_HP_DIS (0x0 << 14)
  8998. +#define RT5671_3D_HP_EN (0x1 << 14)
  8999. +#define RT5671_3D_BT_MASK (0x1 << 13)
  9000. +#define RT5671_3D_BT_SFT 13
  9001. +#define RT5671_3D_BT_DIS (0x0 << 13)
  9002. +#define RT5671_3D_BT_EN (0x1 << 13)
  9003. +#define RT5671_3D_1F_MIX_MASK (0x3 << 11)
  9004. +#define RT5671_3D_1F_MIX_SFT 11
  9005. +#define RT5671_3D_HP_M_MASK (0x1 << 10)
  9006. +#define RT5671_3D_HP_M_SFT 10
  9007. +#define RT5671_3D_HP_M_SUR (0x0 << 10)
  9008. +#define RT5671_3D_HP_M_FRO (0x1 << 10)
  9009. +#define RT5671_M_3D_HRTF_MASK (0x1 << 9)
  9010. +#define RT5671_M_3D_HRTF_SFT 9
  9011. +#define RT5671_M_3D_D2H_MASK (0x1 << 8)
  9012. +#define RT5671_M_3D_D2H_SFT 8
  9013. +#define RT5671_M_3D_D2R_MASK (0x1 << 7)
  9014. +#define RT5671_M_3D_D2R_SFT 7
  9015. +#define RT5671_M_3D_REVB_MASK (0x1 << 6)
  9016. +#define RT5671_M_3D_REVB_SFT 6
  9017. +
  9018. +/* Adjustable high pass filter control 1 (0xd3) */
  9019. +#define RT5671_2ND_HPF_MASK (0x1 << 15)
  9020. +#define RT5671_2ND_HPF_SFT 15
  9021. +#define RT5671_2ND_HPF_DIS (0x0 << 15)
  9022. +#define RT5671_2ND_HPF_EN (0x1 << 15)
  9023. +#define RT5671_HPF_CF_L_MASK (0x7 << 12)
  9024. +#define RT5671_HPF_CF_L_SFT 12
  9025. +#define RT5671_1ST_HPF_MASK (0x1 << 11)
  9026. +#define RT5671_1ST_HPF_SFT 11
  9027. +#define RT5671_1ST_HPF_DIS (0x0 << 11)
  9028. +#define RT5671_1ST_HPF_EN (0x1 << 11)
  9029. +#define RT5671_HPF_CF_R_MASK (0x7 << 8)
  9030. +#define RT5671_HPF_CF_R_SFT 8
  9031. +#define RT5671_ZD_T_MASK (0x3 << 6)
  9032. +#define RT5671_ZD_T_SFT 6
  9033. +#define RT5671_ZD_F_MASK (0x3 << 4)
  9034. +#define RT5671_ZD_F_SFT 4
  9035. +#define RT5671_ZD_F_IM (0x0 << 4)
  9036. +#define RT5671_ZD_F_ZC_IM (0x1 << 4)
  9037. +#define RT5671_ZD_F_ZC_IOD (0x2 << 4)
  9038. +#define RT5671_ZD_F_UN (0x3 << 4)
  9039. +
  9040. +/* HP calibration control and Amp detection (0xd6) */
  9041. +#define RT5671_SI_DAC_MASK (0x1 << 11)
  9042. +#define RT5671_SI_DAC_SFT 11
  9043. +#define RT5671_SI_DAC_AUTO (0x0 << 11)
  9044. +#define RT5671_SI_DAC_TEST (0x1 << 11)
  9045. +#define RT5671_DC_CAL_M_MASK (0x1 << 10)
  9046. +#define RT5671_DC_CAL_M_SFT 10
  9047. +#define RT5671_DC_CAL_M_CAL (0x0 << 10)
  9048. +#define RT5671_DC_CAL_M_NOR (0x1 << 10)
  9049. +#define RT5671_DC_CAL_MASK (0x1 << 9)
  9050. +#define RT5671_DC_CAL_SFT 9
  9051. +#define RT5671_DC_CAL_DIS (0x0 << 9)
  9052. +#define RT5671_DC_CAL_EN (0x1 << 9)
  9053. +#define RT5671_HPD_RCV_MASK (0x7 << 6)
  9054. +#define RT5671_HPD_RCV_SFT 6
  9055. +#define RT5671_HPD_PS_MASK (0x1 << 5)
  9056. +#define RT5671_HPD_PS_SFT 5
  9057. +#define RT5671_HPD_PS_DIS (0x0 << 5)
  9058. +#define RT5671_HPD_PS_EN (0x1 << 5)
  9059. +#define RT5671_CAL_M_MASK (0x1 << 4)
  9060. +#define RT5671_CAL_M_SFT 4
  9061. +#define RT5671_CAL_M_DEP (0x0 << 4)
  9062. +#define RT5671_CAL_M_CAL (0x1 << 4)
  9063. +#define RT5671_CAL_MASK (0x1 << 3)
  9064. +#define RT5671_CAL_SFT 3
  9065. +#define RT5671_CAL_DIS (0x0 << 3)
  9066. +#define RT5671_CAL_EN (0x1 << 3)
  9067. +#define RT5671_CAL_TEST_MASK (0x1 << 2)
  9068. +#define RT5671_CAL_TEST_SFT 2
  9069. +#define RT5671_CAL_TEST_DIS (0x0 << 2)
  9070. +#define RT5671_CAL_TEST_EN (0x1 << 2)
  9071. +#define RT5671_CAL_P_MASK (0x3)
  9072. +#define RT5671_CAL_P_SFT 0
  9073. +#define RT5671_CAL_P_NONE (0x0)
  9074. +#define RT5671_CAL_P_CAL (0x1)
  9075. +#define RT5671_CAL_P_DAC_CAL (0x2)
  9076. +
  9077. +/* Soft volume and zero cross control 1 (0xd9) */
  9078. +#define RT5671_SV_MASK (0x1 << 15)
  9079. +#define RT5671_SV_SFT 15
  9080. +#define RT5671_SV_DIS (0x0 << 15)
  9081. +#define RT5671_SV_EN (0x1 << 15)
  9082. +#define RT5671_SPO_SV_MASK (0x1 << 14)
  9083. +#define RT5671_SPO_SV_SFT 14
  9084. +#define RT5671_SPO_SV_DIS (0x0 << 14)
  9085. +#define RT5671_SPO_SV_EN (0x1 << 14)
  9086. +#define RT5671_OUT_SV_MASK (0x1 << 13)
  9087. +#define RT5671_OUT_SV_SFT 13
  9088. +#define RT5671_OUT_SV_DIS (0x0 << 13)
  9089. +#define RT5671_OUT_SV_EN (0x1 << 13)
  9090. +#define RT5671_HP_SV_MASK (0x1 << 12)
  9091. +#define RT5671_HP_SV_SFT 12
  9092. +#define RT5671_HP_SV_DIS (0x0 << 12)
  9093. +#define RT5671_HP_SV_EN (0x1 << 12)
  9094. +#define RT5671_ZCD_DIG_MASK (0x1 << 11)
  9095. +#define RT5671_ZCD_DIG_SFT 11
  9096. +#define RT5671_ZCD_DIG_DIS (0x0 << 11)
  9097. +#define RT5671_ZCD_DIG_EN (0x1 << 11)
  9098. +#define RT5671_ZCD_MASK (0x1 << 10)
  9099. +#define RT5671_ZCD_SFT 10
  9100. +#define RT5671_ZCD_PD (0x0 << 10)
  9101. +#define RT5671_ZCD_PU (0x1 << 10)
  9102. +#define RT5671_M_ZCD_MASK (0x3f << 4)
  9103. +#define RT5671_M_ZCD_SFT 4
  9104. +#define RT5671_M_ZCD_RM_L (0x1 << 9)
  9105. +#define RT5671_M_ZCD_RM_R (0x1 << 8)
  9106. +#define RT5671_M_ZCD_SM_L (0x1 << 7)
  9107. +#define RT5671_M_ZCD_SM_R (0x1 << 6)
  9108. +#define RT5671_M_ZCD_OM_L (0x1 << 5)
  9109. +#define RT5671_M_ZCD_OM_R (0x1 << 4)
  9110. +#define RT5671_SV_DLY_MASK (0xf)
  9111. +#define RT5671_SV_DLY_SFT 0
  9112. +
  9113. +/* Soft volume and zero cross control 2 (0xda) */
  9114. +#define RT5671_ZCD_HP_MASK (0x1 << 15)
  9115. +#define RT5671_ZCD_HP_SFT 15
  9116. +#define RT5671_ZCD_HP_DIS (0x0 << 15)
  9117. +#define RT5671_ZCD_HP_EN (0x1 << 15)
  9118. +
  9119. +
  9120. +/* Codec Private Register definition */
  9121. +/* 3D Speaker Control (0x63) */
  9122. +#define RT5671_3D_SPK_MASK (0x1 << 15)
  9123. +#define RT5671_3D_SPK_SFT 15
  9124. +#define RT5671_3D_SPK_DIS (0x0 << 15)
  9125. +#define RT5671_3D_SPK_EN (0x1 << 15)
  9126. +#define RT5671_3D_SPK_M_MASK (0x3 << 13)
  9127. +#define RT5671_3D_SPK_M_SFT 13
  9128. +#define RT5671_3D_SPK_CG_MASK (0x1f << 8)
  9129. +#define RT5671_3D_SPK_CG_SFT 8
  9130. +#define RT5671_3D_SPK_SG_MASK (0x1f)
  9131. +#define RT5671_3D_SPK_SG_SFT 0
  9132. +
  9133. +/* Wind Noise Detection Control 1 (0x6c) */
  9134. +#define RT5671_WND_MASK (0x1 << 15)
  9135. +#define RT5671_WND_SFT 15
  9136. +#define RT5671_WND_DIS (0x0 << 15)
  9137. +#define RT5671_WND_EN (0x1 << 15)
  9138. +
  9139. +/* Wind Noise Detection Control 2 (0x6d) */
  9140. +#define RT5671_WND_FC_NW_MASK (0x3f << 10)
  9141. +#define RT5671_WND_FC_NW_SFT 10
  9142. +#define RT5671_WND_FC_WK_MASK (0x3f << 4)
  9143. +#define RT5671_WND_FC_WK_SFT 4
  9144. +
  9145. +/* Wind Noise Detection Control 3 (0x6e) */
  9146. +#define RT5671_HPF_FC_MASK (0x3f << 6)
  9147. +#define RT5671_HPF_FC_SFT 6
  9148. +#define RT5671_WND_FC_ST_MASK (0x3f)
  9149. +#define RT5671_WND_FC_ST_SFT 0
  9150. +
  9151. +/* Wind Noise Detection Control 4 (0x6f) */
  9152. +#define RT5671_WND_TH_LO_MASK (0x3ff)
  9153. +#define RT5671_WND_TH_LO_SFT 0
  9154. +
  9155. +/* Wind Noise Detection Control 5 (0x70) */
  9156. +#define RT5671_WND_TH_HI_MASK (0x3ff)
  9157. +#define RT5671_WND_TH_HI_SFT 0
  9158. +
  9159. +/* Wind Noise Detection Control 8 (0x73) */
  9160. +#define RT5671_WND_WIND_MASK (0x1 << 13) /* Read-Only */
  9161. +#define RT5671_WND_WIND_SFT 13
  9162. +#define RT5671_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
  9163. +#define RT5671_WND_STRONG_SFT 12
  9164. +enum {
  9165. + RT5671_NO_WIND,
  9166. + RT5671_BREEZE,
  9167. + RT5671_STORM,
  9168. +};
  9169. +
  9170. +/* Dipole Speaker Interface (0x75) */
  9171. +#define RT5671_DP_ATT_MASK (0x3 << 14)
  9172. +#define RT5671_DP_ATT_SFT 14
  9173. +#define RT5671_DP_SPK_MASK (0x1 << 10)
  9174. +#define RT5671_DP_SPK_SFT 10
  9175. +#define RT5671_DP_SPK_DIS (0x0 << 10)
  9176. +#define RT5671_DP_SPK_EN (0x1 << 10)
  9177. +
  9178. +/* EQ Pre Volume Control (0xb3) */
  9179. +#define RT5671_EQ_PRE_VOL_MASK (0xffff)
  9180. +#define RT5671_EQ_PRE_VOL_SFT 0
  9181. +
  9182. +/* EQ Post Volume Control (0xb4) */
  9183. +#define RT5671_EQ_PST_VOL_MASK (0xffff)
  9184. +#define RT5671_EQ_PST_VOL_SFT 0
  9185. +
  9186. +/* Jack Detect Control 3 (0xf8) */
  9187. +#define RT5671_CMP_MIC_IN_DET_MASK (0x7 << 12)
  9188. +#define RT5671_JD_CBJ_EN (0x1 << 7)
  9189. +#define RT5671_JD_CBJ_POL (0x1 << 6)
  9190. +#define RT5671_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
  9191. +#define RT5671_JD_TRI_CBJ_SEL_SFT (3)
  9192. +#define RT5671_JD_TRI_HPO_SEL_MASK (0x7)
  9193. +#define RT5671_JD_TRI_HPO_SEL_SFT (0)
  9194. +#define RT5671_JD_F_GPIO_JD1 (0x0)
  9195. +#define RT5671_JD_F_JD1_1 (0x1)
  9196. +#define RT5671_JD_F_JD1_2 (0x2)
  9197. +#define RT5671_JD_F_JD2 (0x3)
  9198. +#define RT5671_JD_F_JD3 (0x4)
  9199. +#define RT5671_JD_F_GPIO_JD2 (0x5)
  9200. +#define RT5671_JD_F_MX0B_12 (0x6)
  9201. +
  9202. +/* Digital Misc Control (0xfa) */
  9203. +#define RT5671_RST_DSP (0x1 << 13)
  9204. +#define RT5671_IF1_ADC1_IN1_SEL (0x1 << 12)
  9205. +#define RT5671_IF1_ADC1_IN1_SFT 12
  9206. +#define RT5671_IF1_ADC1_IN2_SEL (0x1 << 11)
  9207. +#define RT5671_IF1_ADC1_IN2_SFT 11
  9208. +#define RT5671_IF1_ADC2_IN1_SEL (0x1 << 10)
  9209. +#define RT5671_IF1_ADC2_IN1_SFT 10
  9210. +
  9211. +/* General Control2 (0xfb) */
  9212. +#define RT5671_RXDC_SRC_MASK (0x1 << 7)
  9213. +#define RT5671_RXDC_SRC_STO (0x0 << 7)
  9214. +#define RT5671_RXDC_SRC_MONO (0x1 << 7)
  9215. +#define RT5671_RXDC_SRC_SFT (7)
  9216. +#define RT5671_RXDP2_SEL_MASK (0x1 << 3)
  9217. +#define RT5671_RXDP2_SEL_IF2 (0x0 << 3)
  9218. +#define RT5671_RXDP2_SEL_ADC (0x1 << 3)
  9219. +#define RT5671_RXDP2_SEL_SFT (3)
  9220. +
  9221. +
  9222. +/* Vendor ID (0xfd) */
  9223. +#define RT5671_VER_C 0x2
  9224. +#define RT5671_VER_D 0x3
  9225. +
  9226. +
  9227. +/* Volume Rescale */
  9228. +#define RT5671_VOL_RSCL_MAX 0x27
  9229. +#define RT5671_VOL_RSCL_RANGE 0x1F
  9230. +/* Debug String Length */
  9231. +#define RT5671_REG_DISP_LEN 13
  9232. +
  9233. +#define RT5671_NO_JACK BIT(0)
  9234. +#define RT5671_HEADSET_DET BIT(1)
  9235. +#define RT5671_HEADPHO_DET BIT(2)
  9236. +
  9237. +int rt5671_headset_detect(struct snd_soc_codec *codec, int jack_insert);
  9238. +
  9239. +/* System Clock Source */
  9240. +enum {
  9241. + RT5671_SCLK_S_MCLK,
  9242. + RT5671_SCLK_S_PLL1,
  9243. + RT5671_SCLK_S_RCCLK,
  9244. +};
  9245. +
  9246. +/* PLL1 Source */
  9247. +enum {
  9248. + RT5671_PLL1_S_MCLK,
  9249. + RT5671_PLL1_S_BCLK1,
  9250. + RT5671_PLL1_S_BCLK2,
  9251. + RT5671_PLL1_S_BCLK3,
  9252. + RT5671_PLL1_S_BCLK4,
  9253. +};
  9254. +
  9255. +enum {
  9256. + RT5671_AIF1,
  9257. + RT5671_AIF2,
  9258. + RT5671_AIF3,
  9259. + RT5671_AIF4,
  9260. + RT5671_AIFS,
  9261. +};
  9262. +
  9263. +enum {
  9264. + RT5671_BTN_EVENT = BIT(0), /* Button Push */
  9265. + RT5671_BR_EVENT = BIT(1), /* Button Release */
  9266. + RT5671_J_IN_EVENT = BIT(2), /* Jack insert */
  9267. + RT5671_J_OUT_EVENT = BIT(3), /* Jack evulse */
  9268. + RT5671_VAD_EVENT = BIT(4), /* VAD Triggered */
  9269. + RT5671_UN_EVENT = BIT(5), /* Unknown */
  9270. +};
  9271. +
  9272. +#define RT5671_U_IF1 (0x1)
  9273. +#define RT5671_U_IF2 (0x1 << 1)
  9274. +#define RT5671_U_IF3 (0x1 << 2)
  9275. +#define RT5671_U_IF4 (0x1 << 3)
  9276. +
  9277. +enum {
  9278. + RT5671_DMIC_DIS,
  9279. + RT5671_DMIC1,
  9280. + RT5671_DMIC2,
  9281. + RT5671_DMIC3,
  9282. +};
  9283. +
  9284. +struct rt5671_pll_code {
  9285. + bool m_bp; /* Indicates bypass m code or not. */
  9286. + int m_code;
  9287. + int n_code;
  9288. + int k_code;
  9289. +};
  9290. +
  9291. +struct rt5671_priv {
  9292. + struct snd_soc_codec *codec;
  9293. + struct rt5670_platform_data pdata;
  9294. + struct snd_soc_jack hp_jack;
  9295. + struct snd_soc_jack_gpio hp_gpio;
  9296. +
  9297. + int aif_pu;
  9298. + int sysclk;
  9299. + int sysclk_src;
  9300. + int lrck[RT5671_AIFS];
  9301. + int bclk[RT5671_AIFS];
  9302. + int master[RT5671_AIFS];
  9303. +
  9304. + int pll_src;
  9305. + int pll_in;
  9306. + int pll_out;
  9307. +
  9308. + int dmic_en;
  9309. + bool combo_jack_en;
  9310. + int dsp_sw; /* expected parameter setting */
  9311. + int drc_mode;
  9312. + bool dsp_inited;
  9313. + int jack_type;
  9314. + unsigned int adb_register;
  9315. + unsigned int adb_reg_addr[0x100];
  9316. + unsigned int adb_reg_value[0x100];
  9317. + unsigned char adb_reg_num;
  9318. +};
  9319. +
  9320. +int rt5671_conn_mux_path(struct snd_soc_codec *codec,
  9321. + char *widget_name, char *path_name);
  9322. +
  9323. +#endif /* __RT5671_H__ */
  9324. diff --git a/sound/soc/codecs/rt5671_ioctl.c b/sound/soc/codecs/rt5671_ioctl.c
  9325. new file mode 100644
  9326. index 0000000..9fa040e
  9327. --- /dev/null
  9328. +++ b/sound/soc/codecs/rt5671_ioctl.c
  9329. @@ -0,0 +1,138 @@
  9330. +/*
  9331. + * rt5671_ioctl.h -- RT5671 ALSA SoC audio driver IO control
  9332. + *
  9333. + * Copyright 2012 Realtek Microelectronics
  9334. + * Copyright (C) 2016 XiaoMi, Inc.
  9335. + * Author: Bard <bardliao@realtek.com>
  9336. + *
  9337. + * This program is free software; you can redistribute it and/or modify
  9338. + * it under the terms of the GNU General Public License version 2 as
  9339. + * published by the Free Software Foundation.
  9340. + */
  9341. +
  9342. +#include <linux/spi/spi.h>
  9343. +#include <sound/soc.h>
  9344. +#include "rt_codec_ioctl.h"
  9345. +#include "rt5671_ioctl.h"
  9346. +#include "rt5671.h"
  9347. +#include "rt5671-dsp.h"
  9348. +
  9349. +static struct hweq_t hweq_param[] = {
  9350. + {/* NORMAL */
  9351. + {0},
  9352. + {0},
  9353. + 0x0000,
  9354. + },
  9355. + {/* SPK */
  9356. + {0},
  9357. + {0x1c10, 0x01f4, 0xc5e9, 0x1a98, 0x1d2c, 0xc882, 0x1c10,
  9358. + 0x01f4, 0xe904, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4,
  9359. + 0x1c10, 0x01f4, 0x2000, 0x0000, 0x2000},
  9360. + 0x0000,
  9361. + },
  9362. + {/* HP */
  9363. + {0},
  9364. + {0x1c10, 0x01f4, 0xc5e9, 0x1a98, 0x1d2c, 0xc882, 0x1c10,
  9365. + 0x01f4, 0xe904, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4,
  9366. + 0x1c10, 0x01f4, 0x2000, 0x0000, 0x2000},
  9367. + 0x0000,
  9368. + },
  9369. +};
  9370. +#define RT5671_HWEQ_LEN ARRAY_SIZE(hweq_param)
  9371. +
  9372. +int eqreg[EQ_CH_NUM][EQ_REG_NUM] = {
  9373. + {0xa4, 0xa5, 0xeb, 0xec, 0xed, 0xee, 0xe7, 0xe8, 0xe9, 0xea, 0xe5,
  9374. + 0xe6, 0xae, 0xaf, 0xb0, 0xb4, 0xb5, 0xb6, 0xba, 0xbb, 0xbc, 0xc0,
  9375. + 0xc1, 0xc4, 0xc5, 0xc6, 0xca, 0xcc},
  9376. + {0xa6, 0xa7, 0xf5, 0xf6, 0xf7, 0xf8, 0xf1, 0xf2, 0xf3, 0xf4, 0xef,
  9377. + 0xf0, 0xb1, 0xb2, 0xb3, 0xb7, 0xb8, 0xb9, 0xbd, 0xbe, 0xbf, 0xc2,
  9378. + 0xc3, 0xc7, 0xc8, 0xc9, 0xcb, 0xcd},
  9379. + {0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8,
  9380. + 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xe1, 0xe2},
  9381. +};
  9382. +
  9383. +int rt5671_update_eqmode(
  9384. + struct snd_soc_codec *codec, int channel, int mode)
  9385. +{
  9386. + struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
  9387. + int i;
  9388. +
  9389. + if (codec == NULL || mode >= RT5671_HWEQ_LEN)
  9390. + return -EINVAL;
  9391. +
  9392. + dev_dbg(codec->dev, "%s(): mode=%d\n", __func__, mode);
  9393. +
  9394. + for (i = 0; i <= EQ_REG_NUM; i++)
  9395. + hweq_param[mode].reg[i] = eqreg[channel][i];
  9396. +
  9397. + for (i = 0; i <= EQ_REG_NUM; i++) {
  9398. + if (hweq_param[mode].reg[i])
  9399. + ioctl_ops->index_write(codec, hweq_param[mode].reg[i],
  9400. + hweq_param[mode].value[i]);
  9401. + else
  9402. + break;
  9403. + }
  9404. + snd_soc_update_bits(codec, RT5671_EQ_CTRL2, RT5671_EQ_CTRL_MASK,
  9405. + hweq_param[mode].ctrl);
  9406. + snd_soc_update_bits(codec, RT5671_EQ_CTRL1,
  9407. + RT5671_EQ_UPD, RT5671_EQ_UPD);
  9408. + snd_soc_update_bits(codec, RT5671_EQ_CTRL1, RT5671_EQ_UPD, 0);
  9409. +
  9410. + return 0;
  9411. +}
  9412. +
  9413. +int rt5671_ioctl_common(struct snd_hwdep *hw, struct file *file,
  9414. + unsigned int cmd, unsigned long arg)
  9415. +{
  9416. + struct snd_soc_codec *codec = hw->private_data;
  9417. + struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
  9418. + struct rt_codec_cmd rt_codec;
  9419. + int *buf;
  9420. + static int eq_mode[EQ_CH_NUM];
  9421. +
  9422. + if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
  9423. + dev_err(codec->dev, "copy_from_user faild\n");
  9424. + return -EFAULT;
  9425. + }
  9426. + dev_dbg(codec->dev, "%s(): rt_codec.number=%d, cmd=%d\n",
  9427. + __func__, rt_codec.number, cmd);
  9428. + buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
  9429. + if (buf == NULL)
  9430. + return -ENOMEM;
  9431. + if (copy_from_user(buf, rt_codec.buf,
  9432. + sizeof(*buf) * rt_codec.number))
  9433. + goto err;
  9434. +
  9435. + switch (cmd) {
  9436. + case RT_SET_CODEC_HWEQ_IOCTL:
  9437. + if (*buf >= EQ_CH_NUM)
  9438. + break;
  9439. + if (eq_mode[*buf] == *(buf + 1))
  9440. + break;
  9441. + eq_mode[*buf] = *(buf + 1);
  9442. + rt5671_update_eqmode(codec, eq_mode[*buf], *buf);
  9443. + break;
  9444. +
  9445. + case RT_GET_CODEC_ID:
  9446. + *buf = snd_soc_read(codec, RT5671_VENDOR_ID2);
  9447. + if (copy_to_user(rt_codec.buf, buf,
  9448. + sizeof(*buf) * rt_codec.number))
  9449. + goto err;
  9450. + break;
  9451. + case RT_READ_CODEC_DSP_IOCTL:
  9452. + case RT_WRITE_CODEC_DSP_IOCTL:
  9453. + case RT_GET_CODEC_DSP_MODE_IOCTL:
  9454. + return rt5671_dsp_ioctl_common(hw, file, cmd, arg);
  9455. + break;
  9456. + default:
  9457. + break;
  9458. + }
  9459. +
  9460. + kfree(buf);
  9461. + return 0;
  9462. +
  9463. +err:
  9464. + kfree(buf);
  9465. + return -EFAULT;
  9466. +}
  9467. +EXPORT_SYMBOL_GPL(rt5671_ioctl_common);
  9468. diff --git a/sound/soc/codecs/rt5671_ioctl.h b/sound/soc/codecs/rt5671_ioctl.h
  9469. new file mode 100644
  9470. index 0000000..558c9ad
  9471. --- /dev/null
  9472. +++ b/sound/soc/codecs/rt5671_ioctl.h
  9473. @@ -0,0 +1,45 @@
  9474. +/*
  9475. + * rt5671_ioctl.h -- RT5671 ALSA SoC audio driver IO control
  9476. + *
  9477. + * Copyright 2012 Realtek Microelectronics
  9478. + * Copyright (C) 2016 XiaoMi, Inc.
  9479. + * Author: Bard <bardliao@realtek.com>
  9480. + *
  9481. + * This program is free software; you can redistribute it and/or modify
  9482. + * it under the terms of the GNU General Public License version 2 as
  9483. + * published by the Free Software Foundation.
  9484. + */
  9485. +
  9486. +#ifndef __RT5671_IOCTL_H__
  9487. +#define __RT5671_IOCTL_H__
  9488. +
  9489. +#include <sound/hwdep.h>
  9490. +#include <linux/ioctl.h>
  9491. +
  9492. +enum {
  9493. + NORMAL = 0,
  9494. + SPK,
  9495. + HP,
  9496. + MODE_NUM,
  9497. +};
  9498. +
  9499. +enum {
  9500. + EQ_CH_DACL = 0,
  9501. + EQ_CH_DACR,
  9502. + EQ_CH_ADC,
  9503. + EQ_CH_NUM,
  9504. +};
  9505. +
  9506. +#define EQ_REG_NUM 28
  9507. +struct hweq_t {
  9508. + unsigned int reg[EQ_REG_NUM];
  9509. + unsigned int value[EQ_REG_NUM];
  9510. + unsigned int ctrl;
  9511. +};
  9512. +
  9513. +int rt5671_ioctl_common(struct snd_hwdep *hw, struct file *file,
  9514. + unsigned int cmd, unsigned long arg);
  9515. +int rt5671_update_eqmode(
  9516. + struct snd_soc_codec *codec, int channel, int mode);
  9517. +
  9518. +#endif /* __RT5671_IOCTL_H__ */
  9519. diff --git a/sound/soc/codecs/rt56xx_ioctl.c b/sound/soc/codecs/rt56xx_ioctl.c
  9520. index 23ebf2a..96d0279 100644
  9521. --- a/sound/soc/codecs/rt56xx_ioctl.c
  9522. +++ b/sound/soc/codecs/rt56xx_ioctl.c
  9523. @@ -145,7 +145,7 @@ static int rt56xx_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
  9524. return 0;
  9525. }
  9526.  
  9527. -int realtek_ce_init_hwdep(struct snd_soc_codec *codec)
  9528. +int rt56xx_init_hwdep(struct snd_soc_codec *codec)
  9529. {
  9530. struct snd_hwdep *hw;
  9531. struct snd_card *card = codec->card->snd_card;
  9532. @@ -165,7 +165,7 @@ int realtek_ce_init_hwdep(struct snd_soc_codec *codec)
  9533.  
  9534. return 0;
  9535. }
  9536. -EXPORT_SYMBOL_GPL(realtek_ce_init_hwdep);
  9537. +EXPORT_SYMBOL_GPL(rt56xx_init_hwdep);
  9538. #endif
  9539.  
  9540. struct rt56xx_ops *rt56xx_get_ioctl_ops(void)
  9541. diff --git a/sound/soc/codecs/rt56xx_ioctl.h b/sound/soc/codecs/rt56xx_ioctl.h
  9542. index caadd91..a60fc18 100644
  9543. --- a/sound/soc/codecs/rt56xx_ioctl.h
  9544. +++ b/sound/soc/codecs/rt56xx_ioctl.h
  9545. @@ -73,6 +73,7 @@ enum {
  9546. };
  9547.  
  9548. int realtek_ce_init_hwdep(struct snd_soc_codec *codec);
  9549. +int rt56xx_init_hwdep(struct snd_soc_codec *codec);
  9550. struct rt56xx_ops *rt56xx_get_ioctl_ops(void);
  9551.  
  9552. #endif /* __RT56XX_IOCTL_H__ */
  9553. diff --git a/sound/soc/codecs/rt_codec_ioctl.c b/sound/soc/codecs/rt_codec_ioctl.c
  9554. index a41c683..7675af1 100644
  9555. --- a/sound/soc/codecs/rt_codec_ioctl.c
  9556. +++ b/sound/soc/codecs/rt_codec_ioctl.c
  9557. @@ -8,7 +8,6 @@
  9558. * it under the terms of the GNU General Public License version 2 as
  9559. * published by the Free Software Foundation.
  9560. */
  9561. -#define DEBUG 1
  9562. #include <linux/spi/spi.h>
  9563. #include <sound/soc.h>
  9564. #include "rt_codec_ioctl.h"
  9565. @@ -162,7 +161,8 @@ int realtek_ce_init_hwdep(struct snd_soc_codec *codec)
  9566.  
  9567. dev_dbg(codec->dev, "enter %s\n", __func__);
  9568.  
  9569. - if ((err = snd_hwdep_new(card, RT_CE_CODEC_HWDEP_NAME, 0, &hw)) < 0)
  9570. + err = snd_hwdep_new(card, RT_CE_CODEC_HWDEP_NAME, 0, &hw);
  9571. + if (err < 0)
  9572. return err;
  9573.  
  9574. strcpy(hw->name, RT_CE_CODEC_HWDEP_NAME);
  9575. diff --git a/sound/soc/codecs/spdif_transciever.c b/sound/soc/codecs/spdif_transciever.c
  9576. index 8efbda4..d20801d 100644
  9577. --- a/sound/soc/codecs/spdif_transciever.c
  9578. +++ b/sound/soc/codecs/spdif_transciever.c
  9579. @@ -34,12 +34,6 @@ static int spdif_probe(struct snd_soc_codec *codec) {
  9580. return 0;
  9581. }
  9582.  
  9583. -static const struct snd_soc_dapm_widget spdif_dapm_widgets[] = {
  9584. - SND_SOC_DAPM_VMID("spdif dummy Vmid"),
  9585. - SND_SOC_DAPM_OUTPUT("OUT"),
  9586. - SND_SOC_DAPM_INPUT("IN"),
  9587. -};
  9588. -
  9589. static const struct snd_soc_dapm_route spdif_intercon[] = {
  9590. { "OUT", NULL, "Playback" },
  9591. { "Capture", NULL, "IN" },
  9592. @@ -57,8 +51,6 @@ static unsigned int spdif_read(struct snd_soc_codec *codec, unsigned int reg) {
  9593.  
  9594. static struct snd_soc_codec_driver soc_codec_spdif_dit = {
  9595. .probe = spdif_probe,
  9596. - .dapm_widgets = spdif_dapm_widgets,
  9597. - .num_dapm_widgets = ARRAY_SIZE(spdif_dapm_widgets),
  9598. .dapm_routes = spdif_intercon,
  9599. .num_dapm_routes = ARRAY_SIZE(spdif_intercon),
  9600. .read = spdif_read,
  9601. diff --git a/sound/soc/codecs/tfa98xx.c b/sound/soc/codecs/tfa98xx.c
  9602. new file mode 100644
  9603. index 0000000..21b5339
  9604. --- /dev/null
  9605. +++ b/sound/soc/codecs/tfa98xx.c
  9606. @@ -0,0 +1,1513 @@
  9607. +/*
  9608. + * tfa98xx.c -- codec driver for TFA98XX
  9609. + *
  9610. + * Copyright (C) 2014 Xiaomi Corporation
  9611. + * Copyright (C) 2016 XiaoMi, Inc.
  9612. + *
  9613. + * Author: Xiang Xiao <xiaoxiang@xiaomi.com>
  9614. + *
  9615. + * This program is free software; you can redistribute it and/or modify it
  9616. + * under the terms of the GNU General Public License as published by the
  9617. + * Free Software Foundation; either version 2 of the License, or (at your
  9618. + * option) any later version.
  9619. + *
  9620. + */
  9621. +
  9622. +#include <linux/delay.h>
  9623. +#include <linux/firmware.h>
  9624. +#include <linux/i2c.h>
  9625. +#include <linux/module.h>
  9626. +#include <linux/slab.h>
  9627. +#include <linux/workqueue.h>
  9628. +#include <sound/pcm_params.h>
  9629. +#include <sound/soc.h>
  9630. +#include <sound/tlv.h>
  9631. +
  9632. +#include "tfa98xx.h"
  9633. +
  9634. +#define TFA98XX_STATUSREG_UP (TFA98XX_STATUSREG_PLLS | \
  9635. + TFA98XX_STATUSREG_CLKS | \
  9636. + TFA98XX_STATUSREG_AREFS)
  9637. +#define TFA98XX_STATUSREG_UP_MSK (TFA98XX_STATUSREG_PLLS_MSK | \
  9638. + TFA98XX_STATUSREG_MTPB_MSK | \
  9639. + TFA98XX_STATUSREG_CLKS_MSK | \
  9640. + TFA98XX_STATUSREG_AREFS_MSK)
  9641. +
  9642. +#define TFA98XX_STATUSREG_ERR1 (TFA98XX_STATUSREG_OCDS)
  9643. +#define TFA98XX_STATUSREG_ERR1_MSK (TFA98XX_STATUSREG_OCDS_MSK)
  9644. +
  9645. +#define TFA98XX_STATUSREG_ERR2 (TFA98XX_STATUSREG_ACS | \
  9646. + TFA98XX_STATUSREG_WDS)
  9647. +#define TFA98XX_STATUSREG_ERR2_MSK (TFA98XX_STATUSREG_ACS_MSK | \
  9648. + TFA98XX_STATUSREG_WDS_MSK)
  9649. +
  9650. +#define TFA98XX_I2SCTRL_MSB_J (2 << TFA98XX_I2SREG_I2SF_POS)
  9651. +#define TFA98XX_I2SCTRL_PHILIPS (3 << TFA98XX_I2SREG_I2SF_POS)
  9652. +#define TFA98XX_I2SCTRL_LSB_J_16 (4 << TFA98XX_I2SREG_I2SF_POS)
  9653. +#define TFA98XX_I2SCTRL_LSB_J_18 (5 << TFA98XX_I2SREG_I2SF_POS)
  9654. +#define TFA98XX_I2SCTRL_LSB_J_20 (6 << TFA98XX_I2SREG_I2SF_POS)
  9655. +#define TFA98XX_I2SCTRL_LSB_J_24 (7 << TFA98XX_I2SREG_I2SF_POS)
  9656. +
  9657. +#define TFA98XX_I2SCTRL_RATE_08000 (0 << TFA98XX_I2SREG_I2SSR_POS)
  9658. +#define TFA98XX_I2SCTRL_RATE_11025 (1 << TFA98XX_I2SREG_I2SSR_POS)
  9659. +#define TFA98XX_I2SCTRL_RATE_12000 (2 << TFA98XX_I2SREG_I2SSR_POS)
  9660. +#define TFA98XX_I2SCTRL_RATE_16000 (3 << TFA98XX_I2SREG_I2SSR_POS)
  9661. +#define TFA98XX_I2SCTRL_RATE_22050 (4 << TFA98XX_I2SREG_I2SSR_POS)
  9662. +#define TFA98XX_I2SCTRL_RATE_24000 (5 << TFA98XX_I2SREG_I2SSR_POS)
  9663. +#define TFA98XX_I2SCTRL_RATE_32000 (6 << TFA98XX_I2SREG_I2SSR_POS)
  9664. +#define TFA98XX_I2SCTRL_RATE_44100 (7 << TFA98XX_I2SREG_I2SSR_POS)
  9665. +#define TFA98XX_I2SCTRL_RATE_48000 (8 << TFA98XX_I2SREG_I2SSR_POS)
  9666. +
  9667. +#define TFA98XX_MUTE_OFF 0
  9668. +#define TFA98XX_MUTE_DIGITAL 1
  9669. +#define TFA98XX_MUTE_AMPLIFIER 2
  9670. +
  9671. +#define TFA98XX_MODULE_SPEAKERBOOST (128 + 1)
  9672. +#define TFA98XX_MODULE_BIQUADFILTERBANK (128 + 2)
  9673. +
  9674. +#define TFA98XX_PARAM_SET_LSMODEL 0x06
  9675. +#define TFA98XX_PARAM_SET_PRESET 0x0D
  9676. +#define TFA98XX_PARAM_SET_CONFIG 0x0E
  9677. +
  9678. +#define TFA98XX_FW_BOOT 0
  9679. +#define TFA98XX_FW_ROM 1
  9680. +#define TFA98XX_FW_SPEAKER 2
  9681. +#define TFA98XX_FW_CONFIG 3
  9682. +#define TFA98XX_FW_PRESET 4
  9683. +#define TFA98XX_FW_EQUALIZER 5
  9684. +#define TFA98XX_FW_NUMBER 6
  9685. +
  9686. +struct tfa98xx_priv {
  9687. + struct mutex fw_lock;
  9688. + bool fw_chg[TFA98XX_FW_NUMBER];
  9689. + char fw_name[TFA98XX_FW_NUMBER][512];
  9690. + const struct firmware *fw[TFA98XX_FW_NUMBER];
  9691. + struct workqueue_struct *workqueue;
  9692. + struct delayed_work monitor_work;
  9693. + struct delayed_work download_work;
  9694. + struct snd_soc_codec *codec;
  9695. + unsigned int pilot_tone;
  9696. + unsigned int reg_addr;
  9697. + unsigned int fmt;
  9698. + bool dsp_crash;
  9699. + bool recalib;
  9700. +};
  9701. +
  9702. +static int tfa98xx_bulk_read(struct snd_soc_codec *codec,
  9703. + unsigned int reg_,
  9704. + void *data, size_t len)
  9705. +{
  9706. + struct i2c_client *client = to_i2c_client(codec->dev);
  9707. + struct i2c_msg msgs[2];
  9708. + u8 reg = reg_;
  9709. + int ret;
  9710. +
  9711. + msgs[0].addr = client->addr;
  9712. + msgs[0].flags = client->flags;
  9713. + msgs[0].len = 1;
  9714. + msgs[0].buf = &reg;
  9715. + msgs[1].addr = client->addr;
  9716. + msgs[1].flags = client->flags | I2C_M_RD;
  9717. + msgs[1].len = len;
  9718. + msgs[1].buf = data;
  9719. +
  9720. + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  9721. + if (ret > 0)
  9722. + ret = 0;
  9723. +
  9724. + return ret;
  9725. +}
  9726. +
  9727. +static int tfa98xx_bulk_write(struct snd_soc_codec *codec,
  9728. + unsigned int reg,
  9729. + const void *data, size_t len)
  9730. +{
  9731. + struct i2c_client *client = to_i2c_client(codec->dev);
  9732. + struct i2c_msg msg;
  9733. + u8 buf[len + 1];
  9734. + int ret;
  9735. +
  9736. + buf[0] = reg;
  9737. + memcpy(buf + 1, data, len);
  9738. +
  9739. + msg.addr = client->addr;
  9740. + msg.flags = client->flags;
  9741. + msg.len = len + 1;
  9742. + msg.buf = buf;
  9743. +
  9744. + ret = i2c_transfer(client->adapter, &msg, 1);
  9745. + if (ret > 0)
  9746. + ret = 0;
  9747. +
  9748. + return ret;
  9749. +}
  9750. +
  9751. +static unsigned int tfa98xx_read(struct snd_soc_codec *codec, unsigned int reg)
  9752. +{
  9753. + unsigned int val;
  9754. + u8 buf[3];
  9755. + int ret;
  9756. +
  9757. + if (reg >= codec->driver->reg_cache_size ||
  9758. + snd_soc_codec_volatile_register(codec, reg) ||
  9759. + codec->cache_bypass) {
  9760. + if (codec->cache_only)
  9761. + return -EINVAL;
  9762. +
  9763. + ret = tfa98xx_bulk_read(codec, reg, buf, reg == TFA98XX_CF_MEM ? 3 : 2);
  9764. + if (ret < 0)
  9765. + return ret;
  9766. + else if (reg == TFA98XX_CF_MEM)
  9767. + return (buf[0] << 16) | (buf[1] << 8) | buf[2];
  9768. + else
  9769. + return (buf[0] << 8) | buf[1];
  9770. + }
  9771. +
  9772. + ret = snd_soc_cache_read(codec, reg, &val);
  9773. + if (ret < 0)
  9774. + return ret;
  9775. + return val;
  9776. +}
  9777. +
  9778. +static int tfa98xx_write(struct snd_soc_codec *codec, unsigned int reg,
  9779. + unsigned int value)
  9780. +{
  9781. + u8 buf[3];
  9782. + size_t sz;
  9783. + int ret;
  9784. +
  9785. + if (!snd_soc_codec_volatile_register(codec, reg) &&
  9786. + reg < codec->driver->reg_cache_size &&
  9787. + !codec->cache_bypass) {
  9788. + ret = snd_soc_cache_write(codec, reg, value);
  9789. + if (ret < 0)
  9790. + return ret;
  9791. + }
  9792. +
  9793. + if (codec->cache_only) {
  9794. + codec->cache_sync = 1;
  9795. + return 0;
  9796. + }
  9797. +
  9798. + if (reg == TFA98XX_CF_MEM) {
  9799. + buf[0] = value >> 16;
  9800. + buf[1] = value >> 8;
  9801. + buf[2] = value >> 0;
  9802. + sz = 3;
  9803. + } else {
  9804. + buf[0] = value >> 8;
  9805. + buf[1] = value >> 0;
  9806. + sz = 2;
  9807. + }
  9808. +
  9809. + return tfa98xx_bulk_write(codec, reg, buf, sz);
  9810. +}
  9811. +
  9812. +static unsigned int tfa98xx_read_dsp(struct snd_soc_codec *codec, unsigned int reg)
  9813. +{
  9814. + int ret;
  9815. +
  9816. + ret = snd_soc_write(codec, TFA98XX_CF_CONTROLS, (reg >> 15) & 0x0E);
  9817. + if (ret < 0)
  9818. + return ret;
  9819. +
  9820. + ret = snd_soc_write(codec, TFA98XX_CF_MAD, reg & 0xFFFF);
  9821. + if (ret < 0)
  9822. + return ret;
  9823. +
  9824. + return snd_soc_read(codec, TFA98XX_CF_MEM);
  9825. +}
  9826. +
  9827. +static int tfa98xx_reset(struct snd_soc_codec *codec)
  9828. +{
  9829. + struct i2c_client *client = to_i2c_client(codec->dev);
  9830. + int ret;
  9831. +
  9832. + /* use the low level function to bypass the codec cache */
  9833. + ret = i2c_smbus_write_word_swapped(client, TFA98XX_SYS_CTRL, TFA98XX_SYS_CTRL_I2CR);
  9834. + if (ret < 0)
  9835. + return ret;
  9836. +
  9837. + /* apply the current setting after reset */
  9838. + codec->cache_sync = 1;
  9839. + ret = snd_soc_cache_sync(codec);
  9840. + if (ret < 0)
  9841. + return ret;
  9842. +
  9843. + return ret;
  9844. +}
  9845. +
  9846. +static int tfa98xx_reset_dsp(struct snd_soc_codec *codec)
  9847. +{
  9848. + unsigned int sense4;
  9849. + int ret;
  9850. +
  9851. + /* temporarily disable clock gating when dsp reset */
  9852. + sense4 = snd_soc_read(codec, TFA98XX_CURRENTSENSE4);
  9853. + ret = snd_soc_write(codec, TFA98XX_CURRENTSENSE4,
  9854. + sense4 | TFA9897_CURRENTSENSE4_2);
  9855. + if (ret < 0)
  9856. + return ret;
  9857. +
  9858. + ret = snd_soc_update_bits(codec, TFA98XX_CF_CONTROLS,
  9859. + TFA98XX_CF_CONTROLS_RST_MSK, TFA98XX_CF_CONTROLS_RST);
  9860. + /* clock gating restore */
  9861. + snd_soc_write(codec, TFA98XX_CURRENTSENSE4, sense4);
  9862. +
  9863. + return ret;
  9864. +}
  9865. +
  9866. +static int tfa98xx_wait_clock(struct snd_soc_codec *codec)
  9867. +{
  9868. + unsigned int status;
  9869. + int tries;
  9870. +
  9871. + for (tries = 10; tries > 0; tries--) {
  9872. + status = snd_soc_read(codec, TFA98XX_STATUSREG);
  9873. + if ((status & TFA98XX_STATUSREG_UP_MSK) == TFA98XX_STATUSREG_UP)
  9874. + break;
  9875. + mdelay(1);
  9876. + }
  9877. + if (tries == 0) {
  9878. + dev_err(codec->dev, "Fail to sync i2s clock on time(%x)\n", status);
  9879. + return -EBUSY;
  9880. + }
  9881. +
  9882. + return 0;
  9883. +}
  9884. +
  9885. +static int tfa98xx_power(struct snd_soc_codec *codec, bool on)
  9886. +{
  9887. + int ret;
  9888. +
  9889. + ret = snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  9890. + TFA98XX_SYS_CTRL_PWDN_MSK, on ? 0 : TFA98XX_SYS_CTRL_PWDN);
  9891. + if (ret < 0)
  9892. + return ret;
  9893. + if (on)
  9894. + ret = tfa98xx_wait_clock(codec);
  9895. + return ret;
  9896. +}
  9897. +
  9898. +static int tfa98xx_mute(struct snd_soc_codec *codec, int mute)
  9899. +{
  9900. + unsigned int status;
  9901. + int ret = 0, tries;
  9902. +
  9903. + switch (mute) {
  9904. + case TFA98XX_MUTE_OFF:
  9905. + ret = snd_soc_update_bits_locked(codec,
  9906. + TFA98XX_AUDIO_CTR, TFA98XX_AUDIO_CTR_CFSM_MSK, 0);
  9907. + if (ret < 0)
  9908. + return ret;
  9909. + ret = snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  9910. + TFA98XX_SYS_CTRL_DCA_MSK | TFA98XX_SYS_CTRL_AMPE_MSK,
  9911. + TFA98XX_SYS_CTRL_DCA | TFA98XX_SYS_CTRL_AMPE);
  9912. + if (ret < 0)
  9913. + return ret;
  9914. + break;
  9915. + case TFA98XX_MUTE_DIGITAL:
  9916. + ret = snd_soc_update_bits_locked(codec, TFA98XX_AUDIO_CTR,
  9917. + TFA98XX_AUDIO_CTR_CFSM_MSK, TFA98XX_AUDIO_CTR_CFSM);
  9918. + if (ret < 0)
  9919. + return ret;
  9920. + ret = snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  9921. + TFA98XX_SYS_CTRL_DCA_MSK | TFA98XX_SYS_CTRL_AMPE_MSK,
  9922. + TFA98XX_SYS_CTRL_AMPE);
  9923. + if (ret < 0)
  9924. + return ret;
  9925. + break;
  9926. + case TFA98XX_MUTE_AMPLIFIER:
  9927. + ret = snd_soc_update_bits_locked(codec,
  9928. + TFA98XX_AUDIO_CTR, TFA98XX_AUDIO_CTR_CFSM_MSK, 0);
  9929. + if (ret < 0)
  9930. + return ret;
  9931. + ret = snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  9932. + TFA98XX_SYS_CTRL_DCA_MSK | TFA98XX_SYS_CTRL_AMPE_MSK,
  9933. + 0);
  9934. + if (ret < 0)
  9935. + return ret;
  9936. +
  9937. + /* wait for amplifier to stop switching */
  9938. + for (tries = 10; tries > 0; tries--) {
  9939. + status = snd_soc_read(codec, TFA98XX_STATUSREG);
  9940. + if (!(status & TFA98XX_STATUSREG_SWS_MSK))
  9941. + break;
  9942. + msleep(10);
  9943. + }
  9944. + if (tries == 0)
  9945. + dev_warn(codec->dev, "Fail to stop amplifier on time\n");
  9946. + break;
  9947. + }
  9948. +
  9949. + return ret;
  9950. +}
  9951. +
  9952. +static int tfa98xx_enable_otc(struct snd_soc_codec *codec, bool recalib)
  9953. +{
  9954. + unsigned int mtp, status;
  9955. + int ret = 0, tries;
  9956. +
  9957. + mtp = snd_soc_read(codec, TFA98XX_MTP_SPKR_CAL);
  9958. + if (recalib || !(mtp & TFA98XX_MTP_SPKR_CAL_MTPOTC_MSK)) {
  9959. + ret = snd_soc_write(codec, TFA98XX_MTPKEY2_REG, 0x5A);
  9960. + if (ret < 0) {
  9961. + dev_err(codec->dev, "Fail to unlock key(%d)\n", ret);
  9962. + return ret;
  9963. + }
  9964. +
  9965. + mtp &= ~TFA98XX_MTP_SPKR_CAL_MTPEX_MSK;
  9966. + mtp |= TFA98XX_MTP_SPKR_CAL_MTPOTC_MSK;
  9967. + ret = snd_soc_write(codec, TFA98XX_MTP_SPKR_CAL, mtp);
  9968. + if (ret < 0) {
  9969. + dev_err(codec->dev, "Fail to update mtp(%d)\n", ret);
  9970. + return ret;
  9971. + }
  9972. +
  9973. + ret = snd_soc_update_bits(codec, TFA98XX_MTP_CTRL_REG3,
  9974. + TFA98XX_MTP_CTRL_REG3_CIMTP_MSK, TFA98XX_MTP_CTRL_REG3_CIMTP);
  9975. + if (ret < 0) {
  9976. + dev_err(codec->dev, "Fail to enable mtp copy(%d)\n", ret);
  9977. + return ret;
  9978. + }
  9979. +
  9980. + for (tries = 10; tries > 0; tries--) {
  9981. + status = snd_soc_read(codec, TFA98XX_STATUSREG);
  9982. + if (!(status & TFA98XX_STATUSREG_MTPB_MSK))
  9983. + break;
  9984. + msleep(100);
  9985. + }
  9986. + if (tries == 0) {
  9987. + dev_err(codec->dev, "Fail to copy mtp on time\n");
  9988. + return -EBUSY;
  9989. + }
  9990. + }
  9991. +
  9992. + return ret;
  9993. +}
  9994. +
  9995. +static int tfa98xx_download_patch(struct snd_soc_codec *codec,
  9996. + const struct firmware *fw)
  9997. +{
  9998. + int ret = -EINVAL;
  9999. + size_t i, sz;
  10000. +
  10001. + /* start from 6 to skip the patch header */
  10002. + for (i = 6; i < fw->size; i += sz) {
  10003. + sz = fw->data[i++];
  10004. + sz += fw->data[i++] << 8;
  10005. +
  10006. + if (i + sz > fw->size) {
  10007. + dev_err(codec->dev,
  10008. + "Invalid patch format(%x, %x)\n", i, sz);
  10009. + return -EINVAL;
  10010. + }
  10011. +
  10012. + dev_dbg(codec->dev,
  10013. + "Download patch offset = %x, size = %x\n", i, sz);
  10014. +
  10015. + ret = snd_soc_bulk_write_raw(codec,
  10016. + fw->data[i], &fw->data[i + 1], sz - 1);
  10017. + if (ret < 0) {
  10018. + dev_err(codec->dev,
  10019. + "Fail to download patch(%x, %x, %d)\n", i, sz, ret);
  10020. + return ret;
  10021. + }
  10022. + }
  10023. +
  10024. + return ret;
  10025. +}
  10026. +
  10027. +static int tfa98xx_upload_file(struct snd_soc_codec *codec,
  10028. + int module_id, int param_id,
  10029. + void *data, size_t size)
  10030. +{
  10031. + unsigned int status;
  10032. + int ret, tries;
  10033. + u8 buf[7];
  10034. +
  10035. + /* step 1: write the header */
  10036. + buf[0] = 0x00; /* CF_CONTROLS: req=0, int=0, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10037. + buf[1] = 0x02;
  10038. + buf[2] = 0x00; /* CF_MAD: addr=1(ID) */
  10039. + buf[3] = 0x01;
  10040. + buf[4] = 0x00; /* CF_MEM */
  10041. + buf[5] = module_id;
  10042. + buf[6] = param_id;
  10043. +
  10044. + ret = snd_soc_bulk_write_raw(codec, TFA98XX_CF_CONTROLS, buf, 7);
  10045. + if (ret < 0) {
  10046. + dev_err(codec->dev, "Fail to write data header(%d)\n", ret);
  10047. + return ret;
  10048. + }
  10049. +
  10050. + /* step 2: wake up dsp and wait done */
  10051. + /* CF_CONTROLS: req=1, int=1, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10052. + ret = snd_soc_write(codec, TFA98XX_CF_CONTROLS, 0x0112);
  10053. + if (ret < 0) {
  10054. + dev_err(codec->dev, "Fail to wake up dsp(%d)\n", ret);
  10055. + return ret;
  10056. + }
  10057. +
  10058. + for (tries = 10; tries > 0; tries--) {
  10059. + status = snd_soc_read(codec, TFA98XX_CF_STATUS);
  10060. + if ((status & TFA98XX_CF_STATUS_ACK_MSK) == 0x0100)
  10061. + break;
  10062. + mdelay(1);
  10063. + }
  10064. + if (tries == 0) {
  10065. + dev_err(codec->dev, "Fail to response on time\n");
  10066. + return -EBUSY;
  10067. + }
  10068. +
  10069. + /* step 3: check dsp result */
  10070. + buf[0] = 0x00; /* CF_CONTROLS: req=0, int=0, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10071. + buf[1] = 0x02;
  10072. + buf[2] = 0x00; /* CF_MAD: addr=0(STATUS) */
  10073. + buf[3] = 0x00;
  10074. +
  10075. + ret = snd_soc_bulk_write_raw(codec, TFA98XX_CF_CONTROLS, buf, 4);
  10076. + if (ret < 0) {
  10077. + dev_err(codec->dev, "Fail to write status header(%d)\n", ret);
  10078. + return ret;
  10079. + }
  10080. +
  10081. + status = snd_soc_read(codec, TFA98XX_CF_MEM);
  10082. + if (status != 0) {
  10083. + dev_err(codec->dev, "Fail to upload file(%d)\n", status);
  10084. + return -EINVAL;
  10085. + }
  10086. +
  10087. + /* step 4: read the data */
  10088. + ret = snd_soc_write(codec, TFA98XX_CF_MAD, 0x0002);
  10089. + if (ret < 0) {
  10090. + dev_err(codec->dev, "Fail to write memory address(%d)\n", ret);
  10091. + return ret;
  10092. + }
  10093. +
  10094. + ret = tfa98xx_bulk_read(codec, TFA98XX_CF_MEM, data, size);
  10095. + if (ret < 0) {
  10096. + dev_err(codec->dev, "Fail to read data(%d)\n", ret);
  10097. + return ret;
  10098. + }
  10099. +
  10100. + return ret;
  10101. +}
  10102. +
  10103. +static int tfa98xx_download_file(struct snd_soc_codec *codec,
  10104. + int module_id, int param_id,
  10105. + const void *data, size_t size)
  10106. +{
  10107. + unsigned int status;
  10108. + int ret, tries;
  10109. + u8 buf[7];
  10110. +
  10111. + /* step 1: write the header */
  10112. + buf[0] = 0x00; /* CF_CONTROLS: req=0, int=0, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10113. + buf[1] = 0x02;
  10114. + buf[2] = 0x00; /* CF_MAD: addr=1(ID) */
  10115. + buf[3] = 0x01;
  10116. + buf[4] = 0x00; /* CF_MEM */
  10117. + buf[5] = module_id;
  10118. + buf[6] = param_id;
  10119. +
  10120. + ret = snd_soc_bulk_write_raw(codec, TFA98XX_CF_CONTROLS, buf, 7);
  10121. + if (ret < 0) {
  10122. + dev_err(codec->dev, "Fail to write data header(%d)\n", ret);
  10123. + return ret;
  10124. + }
  10125. +
  10126. + /* step 2: write the data */
  10127. + ret = snd_soc_bulk_write_raw(codec, TFA98XX_CF_MEM, data, size);
  10128. + if (ret < 0) {
  10129. + dev_err(codec->dev, "Fail to write data(%d)\n", ret);
  10130. + return ret;
  10131. + }
  10132. +
  10133. + /* step 3: wake up dsp and wait done */
  10134. + /* CF_CONTROLS: req=1, int=1, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10135. + ret = snd_soc_write(codec, TFA98XX_CF_CONTROLS, 0x0112);
  10136. + if (ret < 0) {
  10137. + dev_err(codec->dev, "Fail to wake up dsp(%d)\n", ret);
  10138. + return ret;
  10139. + }
  10140. +
  10141. + for (tries = 10; tries > 0; tries--) {
  10142. + status = snd_soc_read(codec, TFA98XX_CF_STATUS);
  10143. + if ((status & TFA98XX_CF_STATUS_ACK_MSK) == 0x0100)
  10144. + break;
  10145. + mdelay(1);
  10146. + }
  10147. + if (tries == 0) {
  10148. + dev_err(codec->dev, "Fail to response on time\n");
  10149. + return -EBUSY;
  10150. + }
  10151. +
  10152. + /* step 4: check dsp result */
  10153. + buf[0] = 0x00; /* CF_CONTROLS: req=0, int=0, aif=0, dmem=1(XMEM), rst_dsp=0 */
  10154. + buf[1] = 0x02;
  10155. + buf[2] = 0x00; /* CF_MAD: addr=0(STATUS) */
  10156. + buf[3] = 0x00;
  10157. +
  10158. + ret = snd_soc_bulk_write_raw(codec, TFA98XX_CF_CONTROLS, buf, 4);
  10159. + if (ret < 0) {
  10160. + dev_err(codec->dev, "Fail to write status header(%d)\n", ret);
  10161. + return ret;
  10162. + }
  10163. +
  10164. + status = snd_soc_read(codec, TFA98XX_CF_MEM);
  10165. + if (status != 0) {
  10166. + dev_err(codec->dev, "Fail to download file(%d)\n", status);
  10167. + return -EINVAL;
  10168. + }
  10169. +
  10170. + return ret;
  10171. +}
  10172. +
  10173. +static int tfa98xx_download_and_verify_file(struct snd_soc_codec *codec,
  10174. + int module_id, int param_id,
  10175. + const void *data, size_t size)
  10176. +{
  10177. + u8 buf[size];
  10178. + int ret;
  10179. +
  10180. + ret = tfa98xx_download_file(codec, module_id, param_id, data, size);
  10181. + if (ret < 0)
  10182. + return ret;
  10183. + ret = tfa98xx_upload_file(codec, module_id, param_id, buf, size);
  10184. + if (ret < 0)
  10185. + return ret;
  10186. + if (memcmp(data, buf, size) != 0) {
  10187. + dev_err(codec->dev, "Write then read mismatch:\n");
  10188. + print_hex_dump(KERN_ERR, "WR ",
  10189. + DUMP_PREFIX_ADDRESS, 16, 1, data, size, true);
  10190. + print_hex_dump(KERN_ERR, "RD ",
  10191. + DUMP_PREFIX_ADDRESS, 16, 1, buf, size, true);
  10192. + return -EINVAL;
  10193. + }
  10194. +
  10195. + return ret;
  10196. +}
  10197. +
  10198. +static void tfa98xx_download(struct work_struct *work)
  10199. +{
  10200. + struct tfa98xx_priv *tfa98xx;
  10201. + struct snd_soc_codec *codec;
  10202. + struct delayed_work *dwork;
  10203. + unsigned int mtp;
  10204. + int ret = 0, id, tries;
  10205. +
  10206. + dwork = to_delayed_work(work);
  10207. + tfa98xx = container_of(dwork, struct tfa98xx_priv, download_work);
  10208. + codec = tfa98xx->codec;
  10209. +
  10210. + mutex_lock(&tfa98xx->fw_lock);
  10211. +
  10212. + /* wait the clock stable */
  10213. + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
  10214. + goto unlock; /* impossible to get the clock */
  10215. +
  10216. + ret = tfa98xx_wait_clock(codec);
  10217. + if (ret < 0)
  10218. + goto unlock;
  10219. +
  10220. + ret = tfa98xx_enable_otc(codec, tfa98xx->recalib);
  10221. + if (ret < 0)
  10222. + goto unlock;
  10223. + tfa98xx->recalib = false;
  10224. +
  10225. + ret = tfa98xx_mute(codec, TFA98XX_MUTE_DIGITAL);
  10226. + if (ret < 0)
  10227. + goto unlock;
  10228. +
  10229. + for (id = 0; id < TFA98XX_FW_NUMBER; id++) {
  10230. + if (tfa98xx->fw[id] == NULL)
  10231. + goto unmute;
  10232. + if (!tfa98xx->fw_chg[id])
  10233. + continue;
  10234. +
  10235. + dev_info(codec->dev,
  10236. + "Download firmware %s\n", tfa98xx->fw_name[id]);
  10237. +
  10238. + switch (id) {
  10239. + case TFA98XX_FW_BOOT:
  10240. + ret = tfa98xx_reset_dsp(codec);
  10241. + if (ret < 0)
  10242. + goto unmute;
  10243. + ret = tfa98xx_wait_clock(codec);
  10244. + if (ret < 0)
  10245. + goto unmute;
  10246. + ret = tfa98xx_download_patch(codec, tfa98xx->fw[id]);
  10247. + if (ret < 0)
  10248. + goto unmute;
  10249. + /* reload rom patch */
  10250. + tfa98xx->fw_chg[TFA98XX_FW_ROM] = true;
  10251. + break;
  10252. + case TFA98XX_FW_ROM:
  10253. + ret = tfa98xx_download_patch(codec, tfa98xx->fw[id]);
  10254. + if (ret < 0)
  10255. + goto unmute;
  10256. + /* reload all setting */
  10257. + tfa98xx->fw_chg[TFA98XX_FW_SPEAKER] = true;
  10258. + tfa98xx->fw_chg[TFA98XX_FW_CONFIG] = true;
  10259. + tfa98xx->fw_chg[TFA98XX_FW_PRESET] = true;
  10260. + tfa98xx->fw_chg[TFA98XX_FW_EQUALIZER] = true;
  10261. + break;
  10262. + case TFA98XX_FW_SPEAKER:
  10263. + ret = tfa98xx_download_and_verify_file(codec,
  10264. + TFA98XX_MODULE_SPEAKERBOOST,
  10265. + TFA98XX_PARAM_SET_LSMODEL,
  10266. + tfa98xx->fw[id]->data,
  10267. + tfa98xx->fw[id]->size);
  10268. + if (ret < 0)
  10269. + goto unmute;
  10270. + break;
  10271. + case TFA98XX_FW_CONFIG:
  10272. + ret = tfa98xx_download_and_verify_file(codec,
  10273. + TFA98XX_MODULE_SPEAKERBOOST,
  10274. + TFA98XX_PARAM_SET_CONFIG,
  10275. + tfa98xx->fw[id]->data,
  10276. + tfa98xx->fw[id]->size);
  10277. + if (ret < 0)
  10278. + goto unmute;
  10279. + break;
  10280. + case TFA98XX_FW_PRESET:
  10281. + ret = tfa98xx_download_and_verify_file(codec,
  10282. + TFA98XX_MODULE_SPEAKERBOOST,
  10283. + TFA98XX_PARAM_SET_PRESET,
  10284. + tfa98xx->fw[id]->data,
  10285. + tfa98xx->fw[id]->size);
  10286. + if (ret < 0)
  10287. + goto unmute;
  10288. + break;
  10289. + case TFA98XX_FW_EQUALIZER:
  10290. + ret = tfa98xx_download_and_verify_file(codec,
  10291. + TFA98XX_MODULE_BIQUADFILTERBANK,
  10292. + 0,
  10293. + tfa98xx->fw[id]->data,
  10294. + tfa98xx->fw[id]->size);
  10295. + if (ret < 0)
  10296. + goto unmute;
  10297. + break;
  10298. + }
  10299. +
  10300. + /* done, clear dirty flag */
  10301. + tfa98xx->fw_chg[id] = false;
  10302. + }
  10303. +
  10304. + /* signal dsp to load the setting */
  10305. + mtp = snd_soc_read(codec, TFA98XX_MTP_SPKR_CAL);
  10306. + if (!(mtp & TFA98XX_MTP_SPKR_CAL_MTPEX_MSK))
  10307. + dev_info(codec->dev, "Start one time calibration\n");
  10308. + else
  10309. + dev_info(codec->dev, "Load the calibration value from mtp\n");
  10310. +
  10311. + snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  10312. + TFA98XX_SYS_CTRL_SBSL_MSK, TFA98XX_SYS_CTRL_SBSL);
  10313. +
  10314. + for (tries = 10; tries > 0; tries--) {
  10315. + mtp = snd_soc_read(codec, TFA98XX_MTP_SPKR_CAL);
  10316. + if (mtp & TFA98XX_MTP_SPKR_CAL_MTPEX_MSK)
  10317. + break;
  10318. + msleep(100);
  10319. + }
  10320. +
  10321. + if (tries == 0)
  10322. + dev_warn(codec->dev, "Fail to calibrate on time\n");
  10323. + else
  10324. + dev_info(codec->dev, "Finish one time calibration\n");
  10325. +
  10326. +unmute:
  10327. + tfa98xx_mute(codec, TFA98XX_MUTE_OFF);
  10328. +unlock:
  10329. + mutex_unlock(&tfa98xx->fw_lock);
  10330. +
  10331. + /* retry in a late time if fail */
  10332. + if (ret < 0) {
  10333. + queue_delayed_work(tfa98xx->workqueue,
  10334. + &tfa98xx->download_work, msecs_to_jiffies(10));
  10335. + }
  10336. +}
  10337. +
  10338. +static bool tfa98xx_start_download(struct tfa98xx_priv *tfa98xx, bool force)
  10339. +{
  10340. + bool sched = force;
  10341. + int id;
  10342. +
  10343. + mutex_lock(&tfa98xx->fw_lock);
  10344. + if (force) { /* re-download all firmware */
  10345. + for (id = 0; id < TFA98XX_FW_NUMBER; id++)
  10346. + tfa98xx->fw_chg[id] = true;
  10347. + } else { /* check the pending change exist */
  10348. + for (id = 0; id < TFA98XX_FW_NUMBER; id++) {
  10349. + if (tfa98xx->fw_chg[id]) {
  10350. + sched = true;
  10351. + break;
  10352. + }
  10353. + }
  10354. + }
  10355. + mutex_unlock(&tfa98xx->fw_lock);
  10356. +
  10357. + if (sched)
  10358. + queue_delayed_work(tfa98xx->workqueue, &tfa98xx->download_work, 0);
  10359. + return sched;
  10360. +}
  10361. +
  10362. +static void tfa98xx_stop_download(struct tfa98xx_priv *tfa98xx)
  10363. +{
  10364. + cancel_delayed_work_sync(&tfa98xx->download_work);
  10365. +}
  10366. +
  10367. +static void tfa98xx_start_monitor(struct tfa98xx_priv *tfa98xx)
  10368. +{
  10369. + queue_delayed_work(tfa98xx->workqueue,
  10370. + &tfa98xx->monitor_work, msecs_to_jiffies(5000));
  10371. +}
  10372. +
  10373. +static void tfa98xx_stop_monitor(struct tfa98xx_priv *tfa98xx)
  10374. +{
  10375. + cancel_delayed_work_sync(&tfa98xx->monitor_work);
  10376. +}
  10377. +
  10378. +static int tfa98xx_check_error(struct snd_soc_codec *codec)
  10379. +{
  10380. + unsigned int status;
  10381. +
  10382. + status = snd_soc_read(codec, TFA98XX_STATUSREG);
  10383. + if (status & TFA98XX_STATUSREG_ERR2_MSK)
  10384. + return 2;
  10385. + else if (status & TFA98XX_STATUSREG_ERR1_MSK)
  10386. + return 1;
  10387. +
  10388. + status = tfa98xx_read_dsp(codec, 0x666);
  10389. + if (status == 0x7FFFFF)
  10390. + return 2;
  10391. +
  10392. + return 0;
  10393. +}
  10394. +
  10395. +static void tfa98xx_monitor(struct work_struct *work)
  10396. +{
  10397. + struct tfa98xx_priv *tfa98xx;
  10398. + struct snd_soc_codec *codec;
  10399. + struct delayed_work *dwork;
  10400. +
  10401. + dwork = to_delayed_work(work);
  10402. + tfa98xx = container_of(dwork, struct tfa98xx_priv, monitor_work);
  10403. + codec = tfa98xx->codec;
  10404. +
  10405. + switch (tfa98xx_check_error(codec)) {
  10406. + case 2:
  10407. + dev_err(codec->dev, "Restart due to dsp crash\n");
  10408. + tfa98xx->dsp_crash = true; /* save crash info */
  10409. + tfa98xx->pilot_tone = tfa98xx_read_dsp(codec, 0x1029A);
  10410. + tfa98xx_reset(codec);
  10411. + tfa98xx_start_download(tfa98xx, true);
  10412. + break;
  10413. + case 1:
  10414. + dev_err(codec->dev, "Repower due to over condition\n");
  10415. + tfa98xx_power(codec, false);
  10416. + usleep_range(5000, 5000);
  10417. + tfa98xx_power(codec, true);
  10418. + break;
  10419. + }
  10420. +
  10421. + tfa98xx_start_monitor(tfa98xx);
  10422. +}
  10423. +
  10424. +static ssize_t tfa98xx_dsp_crash_show(struct device *dev,
  10425. + struct device_attribute *attr, char *buf)
  10426. +{
  10427. + struct i2c_client *client = to_i2c_client(dev);
  10428. + struct tfa98xx_priv *tfa98xx = i2c_get_clientdata(client);
  10429. +
  10430. + return sprintf(buf, "%d\n", tfa98xx->dsp_crash);
  10431. +}
  10432. +
  10433. +static ssize_t tfa98xx_crash_store(struct device *dev,
  10434. + struct device_attribute *attr, const char *buf, size_t count)
  10435. +{
  10436. + struct i2c_client *client = to_i2c_client(dev);
  10437. + struct tfa98xx_priv *tfa98xx = i2c_get_clientdata(client);
  10438. + unsigned long val;
  10439. + int ret;
  10440. +
  10441. + ret = strict_strtoul(buf, 0, &val);
  10442. + if (ret < 0)
  10443. + return ret;
  10444. + tfa98xx->dsp_crash = (val != 0);
  10445. +
  10446. + return count;
  10447. +}
  10448. +static DEVICE_ATTR(dsp_crash, 0664, tfa98xx_dsp_crash_show, tfa98xx_crash_store);
  10449. +
  10450. +
  10451. +static ssize_t tfa98xx_pilot_tone_show(struct device *dev,
  10452. + struct device_attribute *attr, char *buf)
  10453. +{
  10454. + struct i2c_client *client = to_i2c_client(dev);
  10455. + struct tfa98xx_priv *tfa98xx = i2c_get_clientdata(client);
  10456. +
  10457. + return sprintf(buf, "0x%06X\n", tfa98xx->pilot_tone);
  10458. +}
  10459. +static DEVICE_ATTR(pilot_tone, 0444, tfa98xx_pilot_tone_show, NULL);
  10460. +
  10461. +static int tfa98xx_probe(struct snd_soc_codec *codec)
  10462. +{
  10463. + struct tfa98xx_priv *tfa98xx;
  10464. + int ret;
  10465. +
  10466. + tfa98xx = kzalloc(sizeof(struct tfa98xx_priv), GFP_KERNEL);
  10467. + if (tfa98xx == NULL) {
  10468. + dev_err(codec->dev, "Failed to alloc tfa98xx_priv\n");
  10469. + return -ENOMEM;
  10470. + }
  10471. +
  10472. + tfa98xx->codec = codec;
  10473. + mutex_init(&tfa98xx->fw_lock);
  10474. +
  10475. + INIT_DELAYED_WORK(&tfa98xx->monitor_work, tfa98xx_monitor);
  10476. + INIT_DELAYED_WORK(&tfa98xx->download_work, tfa98xx_download);
  10477. +
  10478. + codec->bulk_write_raw = tfa98xx_bulk_write;
  10479. + snd_soc_codec_set_drvdata(codec, tfa98xx);
  10480. +
  10481. + tfa98xx->workqueue = create_singlethread_workqueue(dev_name(codec->dev));
  10482. + if (tfa98xx->workqueue == NULL) {
  10483. + dev_err(codec->dev, "Failed to create workqueue\n");
  10484. + ret = -ENOMEM;
  10485. + goto wq_fail;
  10486. + }
  10487. +
  10488. + ret = tfa98xx_reset(codec);
  10489. + if (ret < 0) {
  10490. + dev_err(codec->dev, "Failed to reset tf98xx(%d)\n", ret);
  10491. + goto reset_fail;
  10492. + }
  10493. +
  10494. + device_create_file(codec->dev, &dev_attr_dsp_crash);
  10495. + device_create_file(codec->dev, &dev_attr_pilot_tone);
  10496. +
  10497. + return ret;
  10498. +
  10499. +reset_fail:
  10500. + destroy_workqueue(tfa98xx->workqueue);
  10501. +wq_fail:
  10502. + kfree(tfa98xx);
  10503. + return ret;
  10504. +}
  10505. +
  10506. +static int tfa98xx_remove(struct snd_soc_codec *codec)
  10507. +{
  10508. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10509. + int id;
  10510. +
  10511. + tfa98xx_stop_monitor(tfa98xx);
  10512. + tfa98xx_stop_download(tfa98xx);
  10513. + destroy_workqueue(tfa98xx->workqueue);
  10514. +
  10515. + for (id = 0; id < TFA98XX_FW_NUMBER; id++)
  10516. + release_firmware(tfa98xx->fw[id]);
  10517. + kfree(tfa98xx);
  10518. +
  10519. + return 0;
  10520. +}
  10521. +
  10522. +static int tfa98xx_reg_addr_get(struct snd_kcontrol *kcontrol,
  10523. + struct snd_ctl_elem_value *ucontrol)
  10524. +{
  10525. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10526. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10527. +
  10528. + ucontrol->value.integer.value[0] = tfa98xx->reg_addr;
  10529. + return 0;
  10530. +}
  10531. +
  10532. +static int tfa98xx_reg_addr_put(struct snd_kcontrol *kcontrol,
  10533. + struct snd_ctl_elem_value *ucontrol)
  10534. +{
  10535. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10536. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10537. +
  10538. + tfa98xx->reg_addr = ucontrol->value.integer.value[0];
  10539. + return 0;
  10540. +}
  10541. +
  10542. +static int tfa98xx_reg_value_get(struct snd_kcontrol *kcontrol,
  10543. + struct snd_ctl_elem_value *ucontrol)
  10544. +{
  10545. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10546. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10547. +
  10548. + ucontrol->value.integer.value[0] = snd_soc_read(codec, tfa98xx->reg_addr);
  10549. + return 0;
  10550. +}
  10551. +
  10552. +static int tfa98xx_reg_value_put(struct snd_kcontrol *kcontrol,
  10553. + struct snd_ctl_elem_value *ucontrol)
  10554. +{
  10555. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10556. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10557. +
  10558. + return snd_soc_write(codec, tfa98xx->reg_addr, ucontrol->value.integer.value[0]);
  10559. +}
  10560. +
  10561. +static int tfa98xx_chsa_put(struct snd_kcontrol *kcontrol,
  10562. + struct snd_ctl_elem_value *ucontrol)
  10563. +{
  10564. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10565. + bool bypass = ucontrol->value.enumerated.item[0] < 2;
  10566. + int ret;
  10567. +
  10568. + ret = snd_soc_update_bits_locked(codec, TFA98XX_SYS_CTRL,
  10569. + TFA98XX_SYS_CTRL_CFE_MSK, bypass ? 0 : TFA98XX_SYS_CTRL_CFE);
  10570. + if (ret < 0)
  10571. + return ret;
  10572. +
  10573. + return snd_soc_put_enum_double(kcontrol, ucontrol);
  10574. +}
  10575. +
  10576. +static int tfa98xx_bsst_get(struct snd_kcontrol *kcontrol,
  10577. + struct snd_ctl_elem_value *ucontrol)
  10578. +{
  10579. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10580. + unsigned int bsss, bsst;
  10581. +
  10582. + bsss = snd_soc_read(codec, TFA98XX_AUDIO_CTR);
  10583. + bsss &= TFA989X_AUDIO_CTR_BSSS_MSK;
  10584. + bsss >>= TFA989X_AUDIO_CTR_BSSS_POS;
  10585. +
  10586. + bsst = snd_soc_read(codec, TFA98XX_BAT_PROT);
  10587. + bsst &= TFA989X_BAT_PROT_BSST_MSK;
  10588. + bsst >>= TFA989X_BAT_PROT_BSST_POS;
  10589. +
  10590. + ucontrol->value.enumerated.item[0] = (bsst << 1) | bsss;
  10591. + return 0;
  10592. +}
  10593. +
  10594. +static int tfa98xx_bsst_put(struct snd_kcontrol *kcontrol,
  10595. + struct snd_ctl_elem_value *ucontrol)
  10596. +{
  10597. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10598. + unsigned int bsss = ucontrol->value.enumerated.item[0] & 1;
  10599. + unsigned int bsst = ucontrol->value.enumerated.item[0] >> 1;
  10600. + int ret;
  10601. +
  10602. + ret = snd_soc_update_bits_locked(codec, TFA98XX_AUDIO_CTR,
  10603. + TFA989X_AUDIO_CTR_BSSS_MSK,
  10604. + bsss << TFA989X_AUDIO_CTR_BSSS_POS);
  10605. + if (ret < 0)
  10606. + return ret;
  10607. +
  10608. + ret = snd_soc_update_bits(codec, TFA98XX_BAT_PROT,
  10609. + TFA989X_BAT_PROT_BSST_MSK,
  10610. + bsst << TFA989X_BAT_PROT_BSST_POS);
  10611. + if (ret < 0)
  10612. + return ret;
  10613. +
  10614. + return ret;
  10615. +}
  10616. +
  10617. +static int tfa98xx_recalib_get(struct snd_kcontrol *kcontrol,
  10618. + struct snd_ctl_elem_value *ucontrol)
  10619. +{
  10620. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10621. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10622. +
  10623. + ucontrol->value.integer.value[0] = tfa98xx->recalib;
  10624. + return 0;
  10625. +}
  10626. +
  10627. +static int tfa98xx_recalib_put(struct snd_kcontrol *kcontrol,
  10628. + struct snd_ctl_elem_value *ucontrol)
  10629. +{
  10630. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10631. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10632. +
  10633. + tfa98xx->recalib = !!ucontrol->value.integer.value[0];
  10634. + if (tfa98xx->recalib)
  10635. + tfa98xx_start_download(tfa98xx, true);
  10636. +
  10637. + return 0;
  10638. +}
  10639. +
  10640. +static int tfa98xx_firmware_info(struct snd_kcontrol *kcontrol,
  10641. + struct snd_ctl_elem_info *uinfo)
  10642. +{
  10643. + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  10644. + uinfo->count = 512;
  10645. + return 0;
  10646. +}
  10647. +
  10648. +static int tfa98xx_firmware_get(struct snd_kcontrol *kcontrol,
  10649. + struct snd_ctl_elem_value *ucontrol)
  10650. +{
  10651. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10652. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10653. + unsigned long id = kcontrol->private_value;
  10654. +
  10655. + strcpy(ucontrol->value.bytes.data, tfa98xx->fw_name[id]);
  10656. + return 0;
  10657. +}
  10658. +
  10659. +static int tfa98xx_firmware_put(struct snd_kcontrol *kcontrol,
  10660. + struct snd_ctl_elem_value *ucontrol)
  10661. +{
  10662. + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  10663. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10664. + unsigned long id = kcontrol->private_value;
  10665. + const char *name = ucontrol->value.bytes.data;
  10666. + const struct firmware *fw;
  10667. + int ret;
  10668. +
  10669. + ret = request_firmware(&fw, name, codec->dev);
  10670. + if (ret < 0) {
  10671. + dev_err(codec->dev, "Failed to request %s(%d)\n", name, ret);
  10672. + return ret;
  10673. + }
  10674. +
  10675. + mutex_lock(&tfa98xx->fw_lock);
  10676. + strcpy(tfa98xx->fw_name[id], name);
  10677. + if (tfa98xx->fw[id] == NULL || /* no firmware yet */
  10678. + tfa98xx->fw[id]->size != fw->size || /* or change */
  10679. + memcmp(tfa98xx->fw[id]->data, fw->data, fw->size)) {
  10680. + tfa98xx->fw_chg[id] = true;
  10681. + swap(tfa98xx->fw[id], fw);
  10682. + }
  10683. + mutex_unlock(&tfa98xx->fw_lock);
  10684. +
  10685. + /* download in the background to unblock
  10686. + the caller to turn on the clock */
  10687. + tfa98xx_start_download(tfa98xx, false);
  10688. +
  10689. + release_firmware(fw);
  10690. + return ret;
  10691. +}
  10692. +
  10693. +#define TFA98XX_FIRMWARE(xname, id) \
  10694. + { \
  10695. + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  10696. + .name = xname, \
  10697. + .info = tfa98xx_firmware_info, \
  10698. + .get = tfa98xx_firmware_get, \
  10699. + .put = tfa98xx_firmware_put, \
  10700. + .private_value = id, \
  10701. + }
  10702. +
  10703. +static const char * const tfa98xx_chs12_text[] = {
  10704. + "Left", "Right", "Mono",
  10705. +};
  10706. +static const unsigned int tfa98xx_chs12_value[] = {
  10707. + 1, 2, 3,
  10708. +};
  10709. +static const SOC_VALUE_ENUM_SINGLE_DECL(
  10710. + tfa98xx_chs12_enum, TFA98XX_I2SREG,
  10711. + TFA98XX_I2SREG_CHS12_POS, TFA98XX_I2SREG_CHS12_MAX,
  10712. + tfa98xx_chs12_text, tfa98xx_chs12_value);
  10713. +
  10714. +static const char * const tfa98xx_chs3_text[] = {
  10715. + "Left", "Right",
  10716. +};
  10717. +static const SOC_ENUM_SINGLE_DECL(
  10718. + tfa98xx_chs3_enum, TFA98XX_I2SREG,
  10719. + TFA98XX_I2SREG_CHS3_POS, tfa98xx_chs3_text);
  10720. +
  10721. +static const char * const tfa98xx_chsa_text[] = {
  10722. + "Left", "Right", "DSP",
  10723. +};
  10724. +static const SOC_ENUM_SINGLE_DECL(
  10725. + tfa98xx_chsa_enum, TFA98XX_I2SREG,
  10726. + TFA98XX_I2SREG_CHSA_POS, tfa98xx_chsa_text);
  10727. +
  10728. +static const char * const tfa98xx_i2sdoc_text[] = {
  10729. + "DSP", "DATAI1", "DATAI2", "DATAI3",
  10730. +};
  10731. +static const SOC_ENUM_SINGLE_DECL(
  10732. + tfa98xx_i2sdoc_enum, TFA98XX_I2SREG,
  10733. + TFA9890_I2SREG_I2SDOC_POS, tfa98xx_i2sdoc_text);
  10734. +
  10735. +static const char * const tfa98xx_bsst_text[] = {
  10736. + "2.73V", "2.99V", "2.83V", "3.09V", "2.93V", "3.19V", "3.03V", "3.29V",
  10737. + "3.13V", "3.39V", "3.23V", "3.49V", "3.33V", "3.59V", "3.43V", "3.69V",
  10738. + "3.53V", "3.79V", "3.63V", "3.89V", "3.73V", "3.99V", "3.83V", "4.09V",
  10739. + "3.93V", "4.19V", "4.03V", "4.29V", "4.13V", "4.39V", "4.23V", "4.49V",
  10740. +};
  10741. +static const SOC_ENUM_SINGLE_EXT_DECL(
  10742. + tfa98xx_bsst_enum, tfa98xx_bsst_text);
  10743. +
  10744. +static const DECLARE_TLV_DB_SCALE(
  10745. + tfa98xx_vol_tlv, -12750, 50, 0);
  10746. +
  10747. +static const char * const tfa98xx_dcvo_text[] = {
  10748. + "6.0V", "6.5V", "7.0V", "7.5V", "8.0V", "8.5V", "9.0V", "9.5V",
  10749. +};
  10750. +static const SOC_ENUM_SINGLE_DECL(
  10751. + tfa98xx_dcvo_enum, TFA98XX_DCDCBOOST,
  10752. + TFA98XX_DCDCBOOST_DCVO_POS, tfa98xx_dcvo_text);
  10753. +
  10754. +static const char * const tfa98xx_dcmcc_text[] = {
  10755. + "0.5A", "1.0A", "1.4A", "1.9A", "2.4A", "2.9A", "3.3A", "3.8A",
  10756. +};
  10757. +static const SOC_ENUM_SINGLE_DECL(
  10758. + tfa98xx_dcmcc_enum, TFA98XX_DCDCBOOST,
  10759. + TFA98XX_DCDCBOOST_DCMCC_POS, tfa98xx_dcmcc_text);
  10760. +
  10761. +static const char * const tfa98xx_isel_text[] = {
  10762. + "Input1", "Input2",
  10763. +};
  10764. +static const SOC_ENUM_SINGLE_DECL(
  10765. + tfa98xx_isel_enum, TFA98XX_SYS_CTRL,
  10766. + TFA98XX_SYS_CTRL_ISEL_POS, tfa98xx_isel_text);
  10767. +
  10768. +static const char * const tfa98xx_dccv_text[] = {
  10769. + "0.7uH", "1uH", "1.5uH", "2.2uH",
  10770. +};
  10771. +static const SOC_ENUM_SINGLE_DECL(
  10772. + tfa98xx_dccv_enum, TFA98XX_SYS_CTRL,
  10773. + TFA98XX_SYS_CTRL_DCCV_POS, tfa98xx_dccv_text);
  10774. +
  10775. +static const char * const tfa98xx_spkr_text[] = {
  10776. + "Auto", "4Omh", "6Omh", "8Omh",
  10777. +};
  10778. +static const SOC_ENUM_SINGLE_DECL(
  10779. + tfa98xx_spkr_enum, TFA98XX_I2S_SEL_REG,
  10780. + TFA98XX_I2S_SEL_REG_SPKR_POS, tfa98xx_spkr_text);
  10781. +
  10782. +static const char * const tfa98xx_spkl_text[] = {
  10783. + "22uH", "27uH", "33uH", "39uH", "47uH", "56uH", "68uH", "82uH",
  10784. +};
  10785. +static const SOC_ENUM_SINGLE_DECL(
  10786. + tfa98xx_spkl_enum, TFA98XX_I2S_SEL_REG,
  10787. + TFA98XX_I2S_SEL_REG_SPKL_POS, tfa98xx_spkl_text);
  10788. +
  10789. +static const char * const tfa98xx_dos_text[] = {
  10790. + "Current", "Gain", "AEC", "Voltage", "DATAI3 Right", "DATAI3 Left",
  10791. +};
  10792. +static const SOC_ENUM_DOUBLE_DECL(
  10793. + tfa98xx_dos_enum, TFA98XX_I2S_SEL_REG,
  10794. + TFA98XX_I2S_SEL_REG_DOLS_POS, TFA98XX_I2S_SEL_REG_DORS_POS,
  10795. + tfa98xx_dos_text);
  10796. +
  10797. +static const struct snd_kcontrol_new tfa98xx_controls[] = {
  10798. + SOC_SINGLE_EXT("Reg Addr", SND_SOC_NOPM, 0, 0x8F, 0,
  10799. + tfa98xx_reg_addr_get, tfa98xx_reg_addr_put),
  10800. + SOC_SINGLE_EXT("Reg Value", SND_SOC_NOPM, 0, 0xFFFFFF, 0,
  10801. + tfa98xx_reg_value_get, tfa98xx_reg_value_put),
  10802. + SOC_SINGLE("Battery Voltage", TFA98XX_BATTERYVOLTAGE,
  10803. + TFA98XX_BATTERYVOLTAGE_BATS_POS, TFA98XX_BATTERYVOLTAGE_BATS_MAX, 0),
  10804. + SOC_SINGLE("Temperature", TFA98XX_TEMPERATURE,
  10805. + TFA98XX_TEMPERATURE_TEMPS_POS, TFA98XX_TEMPERATURE_TEMPS_MAX, 0),
  10806. + SOC_VALUE_ENUM("Input Channel Mux", tfa98xx_chs12_enum),
  10807. + SOC_ENUM("Gain Channel Mux", tfa98xx_chs3_enum),
  10808. + SOC_ENUM_EXT("Amplifier Channel Mux", tfa98xx_chsa_enum,
  10809. + snd_soc_get_enum_double, tfa98xx_chsa_put),
  10810. + SOC_ENUM("Output Interface Mux", tfa98xx_i2sdoc_enum),
  10811. + SOC_ENUM_EXT("Safeguard Threshold", tfa98xx_bsst_enum,
  10812. + tfa98xx_bsst_get, tfa98xx_bsst_put),
  10813. + SOC_SINGLE("Safeguard Bypass", TFA98XX_BAT_PROT,
  10814. + TFA989X_BAT_PROT_BSSBY_POS, TFA989X_BAT_PROT_BSSBY_MAX, 0),
  10815. + SOC_SINGLE_TLV("Digital Volume", TFA98XX_AUDIO_CTR,
  10816. + TFA98XX_AUDIO_CTR_VOL_POS, TFA98XX_AUDIO_CTR_VOL_MAX,
  10817. + 1, tfa98xx_vol_tlv),
  10818. + SOC_ENUM("Output Voltage", tfa98xx_dcvo_enum),
  10819. + SOC_ENUM("Max Coil Current", tfa98xx_dcmcc_enum),
  10820. + SOC_SINGLE("Use External Temperature", TFA98XX_SPKR_CALIBRATION,
  10821. + TFA98XX_SPKR_CALIBRATION_TROS_POS, TFA98XX_SPKR_CALIBRATION_TROS_MAX, 0),
  10822. + SOC_SINGLE("External Temperature", TFA98XX_SPKR_CALIBRATION,
  10823. + TFA98XX_SPKR_CALIBRATION_EXTTS_POS, TFA98XX_SPKR_CALIBRATION_EXTTS_MAX, 0),
  10824. + SOC_ENUM("Input Interface Mux", tfa98xx_isel_enum),
  10825. + SOC_ENUM("Coil Value", tfa98xx_dccv_enum),
  10826. + SOC_ENUM("Resistance", tfa98xx_spkr_enum),
  10827. + SOC_ENUM("Inductance", tfa98xx_spkl_enum),
  10828. + SOC_ENUM("Output Channel Mux", tfa98xx_dos_enum),
  10829. + SOC_SINGLE_BOOL_EXT("Recalibrate", 0,
  10830. + tfa98xx_recalib_get, tfa98xx_recalib_put),
  10831. + TFA98XX_FIRMWARE("Boot Patch", TFA98XX_FW_BOOT),
  10832. + TFA98XX_FIRMWARE("ROM Patch", TFA98XX_FW_ROM),
  10833. + TFA98XX_FIRMWARE("Speaker File", TFA98XX_FW_SPEAKER),
  10834. + TFA98XX_FIRMWARE("Config File", TFA98XX_FW_CONFIG),
  10835. + TFA98XX_FIRMWARE("Preset File", TFA98XX_FW_PRESET),
  10836. + TFA98XX_FIRMWARE("Equalizer File", TFA98XX_FW_EQUALIZER),
  10837. +};
  10838. +
  10839. +static const struct snd_soc_dapm_route tfa98xx_routes[] = {
  10840. + { "Capture", NULL, "Playback" },
  10841. +};
  10842. +
  10843. +static const u16 tfa98xx_reg[0x90] = {
  10844. + [TFA98XX_I2SREG] = 0x888B,
  10845. + [TFA98XX_BAT_PROT] = 0x9392,
  10846. + [TFA98XX_AUDIO_CTR] = 0x000F,
  10847. + [TFA98XX_DCDCBOOST] = 0x8FFF,
  10848. + [TFA98XX_SPKR_CALIBRATION] = 0x3800,
  10849. + [TFA98XX_SYS_CTRL] = 0x824D,
  10850. + [TFA98XX_I2S_SEL_REG] = 0x3EC3,
  10851. +
  10852. +
  10853. + [TFA98XX_INTERRUPT_REG] = 0x0040,
  10854. +
  10855. +
  10856. + [TFA98XX_CURRENTSENSE4] = 0xAD93,
  10857. +};
  10858. +
  10859. +static int tfa98xx_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
  10860. +{
  10861. + switch (reg) {
  10862. + case TFA98XX_I2SREG:
  10863. + case TFA98XX_BAT_PROT:
  10864. + case TFA98XX_AUDIO_CTR:
  10865. + case TFA98XX_DCDCBOOST:
  10866. + case TFA98XX_SPKR_CALIBRATION:
  10867. + case TFA98XX_SYS_CTRL:
  10868. + case TFA98XX_I2S_SEL_REG:
  10869. + case TFA98XX_INTERRUPT_REG:
  10870. + case TFA98XX_CURRENTSENSE4:
  10871. + return 0;
  10872. + default:
  10873. + return 1;
  10874. + }
  10875. +}
  10876. +
  10877. +static int tfa98xx_writable_register(struct snd_soc_codec *codec, unsigned int reg)
  10878. +{
  10879. + switch (reg) {
  10880. + case TFA98XX_STATUSREG:
  10881. + case TFA98XX_BATTERYVOLTAGE:
  10882. + case TFA98XX_TEMPERATURE:
  10883. + case TFA98XX_REVISIONNUMBER:
  10884. + case TFA9890_MTPF:
  10885. + return 0;
  10886. + default:
  10887. + return 1;
  10888. + }
  10889. +}
  10890. +
  10891. +static const struct snd_soc_codec_driver tfa98xx_drv = {
  10892. + .probe = tfa98xx_probe,
  10893. + .remove = tfa98xx_remove,
  10894. + .controls = tfa98xx_controls,
  10895. + .num_controls = ARRAY_SIZE(tfa98xx_controls),
  10896. + .dapm_routes = tfa98xx_routes,
  10897. + .num_dapm_routes = ARRAY_SIZE(tfa98xx_routes),
  10898. + .read = tfa98xx_read,
  10899. + .write = tfa98xx_write,
  10900. + .volatile_register = tfa98xx_volatile_register,
  10901. + .writable_register = tfa98xx_writable_register,
  10902. + .reg_cache_size = ARRAY_SIZE(tfa98xx_reg),
  10903. + .reg_word_size = sizeof(tfa98xx_reg[0]),
  10904. + .reg_cache_default = tfa98xx_reg,
  10905. + .idle_bias_off = 1,
  10906. +};
  10907. +
  10908. +#define TFA98XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  10909. + SNDRV_PCM_FMTBIT_S18_3LE | \
  10910. + SNDRV_PCM_FMTBIT_S20_3LE | \
  10911. + SNDRV_PCM_FMTBIT_S24_LE)
  10912. +
  10913. +#define TFA98XX_RATES SNDRV_PCM_RATE_8000_48000
  10914. +
  10915. +static int tfa98xx_set_format(struct snd_soc_dai *codec_dai, unsigned int fmt)
  10916. +{
  10917. + struct snd_soc_codec *codec = codec_dai->codec;
  10918. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10919. +
  10920. + /* interface format */
  10921. + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  10922. + case SND_SOC_DAIFMT_I2S:
  10923. + case SND_SOC_DAIFMT_RIGHT_J:
  10924. + case SND_SOC_DAIFMT_LEFT_J:
  10925. + break;
  10926. + default:
  10927. + dev_err(codec->dev, "Invalid interface format\n");
  10928. + return -EINVAL;
  10929. + }
  10930. +
  10931. + /* clock inversion */
  10932. + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  10933. + case SND_SOC_DAIFMT_NB_NF:
  10934. + break;
  10935. + default:
  10936. + dev_err(codec->dev, "Invalid clock inversion\n");
  10937. + return -EINVAL;
  10938. + }
  10939. +
  10940. + /* set master/slave audio interface */
  10941. + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  10942. + case SND_SOC_DAIFMT_CBS_CFS:
  10943. + break;
  10944. + default:
  10945. + dev_err(codec->dev, "Invalid master/slave setting\n");
  10946. + return -EINVAL;
  10947. + }
  10948. +
  10949. + /* save for later use */
  10950. + tfa98xx->fmt = fmt;
  10951. + return 0;
  10952. +}
  10953. +
  10954. +static int tfa98xx_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  10955. +{
  10956. + struct snd_soc_codec *codec = codec_dai->codec;
  10957. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10958. +
  10959. + if (mute) {
  10960. + tfa98xx_stop_monitor(tfa98xx);
  10961. + tfa98xx_stop_download(tfa98xx);
  10962. + tfa98xx_mute(codec, TFA98XX_MUTE_AMPLIFIER);
  10963. + tfa98xx_power(codec, false);
  10964. + usleep_range(5000, 5000);
  10965. + } else {
  10966. + usleep_range(5000, 5000);
  10967. + tfa98xx_power(codec, true);
  10968. + if (tfa98xx_start_download(tfa98xx, false))
  10969. + ; /* will turn off the mute after download */
  10970. + else
  10971. + tfa98xx_mute(codec, TFA98XX_MUTE_OFF);
  10972. + tfa98xx_start_monitor(tfa98xx);
  10973. + }
  10974. +
  10975. + return 0;
  10976. +}
  10977. +
  10978. +static int tfa98xx_hw_params(struct snd_pcm_substream *substream,
  10979. + struct snd_pcm_hw_params *params,
  10980. + struct snd_soc_dai *dai)
  10981. +{
  10982. + struct snd_soc_codec *codec = dai->codec;
  10983. + struct tfa98xx_priv *tfa98xx = snd_soc_codec_get_drvdata(codec);
  10984. + unsigned int value = 0;
  10985. +
  10986. + switch (tfa98xx->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  10987. + case SND_SOC_DAIFMT_I2S:
  10988. + value |= TFA98XX_I2SCTRL_PHILIPS;
  10989. + break;
  10990. + case SND_SOC_DAIFMT_RIGHT_J:
  10991. + switch (params_format(params)) {
  10992. + case SNDRV_PCM_FORMAT_S16_LE:
  10993. + value |= TFA98XX_I2SCTRL_LSB_J_16;
  10994. + break;
  10995. + case SNDRV_PCM_FORMAT_S18_3LE:
  10996. + value |= TFA98XX_I2SCTRL_LSB_J_18;
  10997. + break;
  10998. + case SNDRV_PCM_FORMAT_S20_3LE:
  10999. + value |= TFA98XX_I2SCTRL_LSB_J_20;
  11000. + break;
  11001. + case SNDRV_PCM_FORMAT_S24_LE:
  11002. + value |= TFA98XX_I2SCTRL_LSB_J_24;
  11003. + break;
  11004. + default:
  11005. + return -EINVAL;
  11006. + }
  11007. + break;
  11008. + case SND_SOC_DAIFMT_LEFT_J:
  11009. + value |= TFA98XX_I2SCTRL_MSB_J;
  11010. + break;
  11011. + default:
  11012. + dev_err(codec->dev, "Invalid dai format = %d\n", tfa98xx->fmt);
  11013. + return -EINVAL;
  11014. + }
  11015. +
  11016. + switch (params_rate(params)) {
  11017. + case 48000:
  11018. + value |= TFA98XX_I2SCTRL_RATE_48000;
  11019. + break;
  11020. + case 44100:
  11021. + value |= TFA98XX_I2SCTRL_RATE_44100;
  11022. + break;
  11023. + case 32000:
  11024. + value |= TFA98XX_I2SCTRL_RATE_32000;
  11025. + break;
  11026. + case 24000:
  11027. + value |= TFA98XX_I2SCTRL_RATE_24000;
  11028. + break;
  11029. + case 22050:
  11030. + value |= TFA98XX_I2SCTRL_RATE_22050;
  11031. + break;
  11032. + case 16000:
  11033. + value |= TFA98XX_I2SCTRL_RATE_16000;
  11034. + break;
  11035. + case 12000:
  11036. + value |= TFA98XX_I2SCTRL_RATE_12000;
  11037. + break;
  11038. + case 11025:
  11039. + value |= TFA98XX_I2SCTRL_RATE_11025;
  11040. + break;
  11041. + case 8000:
  11042. + value |= TFA98XX_I2SCTRL_RATE_08000;
  11043. + break;
  11044. + default:
  11045. + return -EINVAL;
  11046. + }
  11047. +
  11048. + return snd_soc_update_bits_locked(codec, TFA98XX_I2SREG,
  11049. + TFA98XX_I2SREG_I2SSR_MSK | TFA98XX_I2SREG_I2SF_MSK, value);
  11050. +}
  11051. +
  11052. +static const struct snd_soc_dai_ops tfa98xx_dai_ops = {
  11053. + .set_fmt = tfa98xx_set_format,
  11054. + .digital_mute = tfa98xx_digital_mute,
  11055. + .hw_params = tfa98xx_hw_params,
  11056. +};
  11057. +
  11058. +static struct snd_soc_dai_driver tfa98xx_dai = {
  11059. + .name = "tfa98xx-dai",
  11060. + .ops = &tfa98xx_dai_ops,
  11061. + .capture = {
  11062. + .stream_name = "Capture",
  11063. + .formats = TFA98XX_FORMATS,
  11064. + .rates = TFA98XX_RATES,
  11065. + .channels_min = 2,
  11066. + .channels_max = 2,
  11067. + },
  11068. + .playback = {
  11069. + .stream_name = "Playback",
  11070. + .formats = TFA98XX_FORMATS,
  11071. + .rates = TFA98XX_RATES,
  11072. + .channels_min = 2,
  11073. + .channels_max = 2,
  11074. + },
  11075. + .symmetric_rates = 1,
  11076. +};
  11077. +
  11078. +static int tfa98xx_i2c_probe(struct i2c_client *client,
  11079. + const struct i2c_device_id *id)
  11080. +{
  11081. + return snd_soc_register_codec(&client->dev,
  11082. + &tfa98xx_drv, &tfa98xx_dai, 1);
  11083. +}
  11084. +
  11085. +static int tfa98xx_i2c_remove(struct i2c_client *client)
  11086. +{
  11087. + snd_soc_unregister_codec(&client->dev);
  11088. + return 0;
  11089. +}
  11090. +
  11091. +static void tfa98xx_i2c_shutdown(struct i2c_client *client)
  11092. +{
  11093. + struct tfa98xx_priv *tfa98xx = i2c_get_clientdata(client);
  11094. +
  11095. + if (tfa98xx)
  11096. + tfa98xx_power(tfa98xx->codec, false);
  11097. +}
  11098. +
  11099. +static const struct i2c_device_id tfa98xx_i2c_id[] = {
  11100. + { "tfa98xx", 0 },
  11101. + { }
  11102. +};
  11103. +MODULE_DEVICE_TABLE(i2c, tfa98xx_i2c_id);
  11104. +
  11105. +static struct i2c_driver tfa98xx_i2c_driver = {
  11106. + .driver = {
  11107. + .name = "tfa98xx",
  11108. + .owner = THIS_MODULE,
  11109. + },
  11110. + .probe = tfa98xx_i2c_probe,
  11111. + .remove = tfa98xx_i2c_remove,
  11112. + .shutdown = tfa98xx_i2c_shutdown,
  11113. + .id_table = tfa98xx_i2c_id,
  11114. +};
  11115. +module_i2c_driver(tfa98xx_i2c_driver);
  11116. +
  11117. +MODULE_AUTHOR("Xiang Xiao <xiaoxiang@xiaomi.com>");
  11118. +MODULE_DESCRIPTION("ASoC TFA98XX codec driver");
  11119. +MODULE_LICENSE("GPL");
  11120. diff --git a/sound/soc/codecs/tfa98xx.h b/sound/soc/codecs/tfa98xx.h
  11121. new file mode 100644
  11122. index 0000000..2d63f34
  11123. --- /dev/null
  11124. +++ b/sound/soc/codecs/tfa98xx.h
  11125. @@ -0,0 +1,2590 @@
  11126. +/** \file Tfa98xx_genregs.h
  11127. + * This file was automatically generated.
  11128. + */
  11129. +#ifndef TFA98XX_GENREGS_H_
  11130. +#define TFA98XX_GENREGS_H_
  11131. +
  11132. +
  11133. +/** StatusReg Register ($00) ********************************************/
  11134. +
  11135. +/** \addtogroup _0x00_StatusReg
  11136. + * @{
  11137. + */
  11138. +#define TFA98XX_STATUSREG 0x00
  11139. +/** \addtogroup VDDS
  11140. + * @{
  11141. + */
  11142. +/*!
  11143. + Power-on-reset flag
  11144. + * - 1 = Power-on-reset detected
  11145. + * - 0 = Power-on-reset detected and cleared by reading status register
  11146. +*/
  11147. +#define TFA98XX_STATUSREG_VDDS (0x1<<0)
  11148. +#define TFA98XX_STATUSREG_VDDS_POS 0
  11149. +#define TFA98XX_STATUSREG_VDDS_LEN 1
  11150. +#define TFA98XX_STATUSREG_VDDS_MAX 1
  11151. +#define TFA98XX_STATUSREG_VDDS_MSK 0x1
  11152. +/** @} */
  11153. +
  11154. +/** \addtogroup PLLS
  11155. + * @{
  11156. + */
  11157. +/*!
  11158. + PLL lock
  11159. + * - 0 = PLL not in lock
  11160. + * - 1 = PLL in lock
  11161. +*/
  11162. +#define TFA98XX_STATUSREG_PLLS (0x1<<1)
  11163. +#define TFA98XX_STATUSREG_PLLS_POS 1
  11164. +#define TFA98XX_STATUSREG_PLLS_LEN 1
  11165. +#define TFA98XX_STATUSREG_PLLS_MAX 1
  11166. +#define TFA98XX_STATUSREG_PLLS_MSK 0x2
  11167. +/** @} */
  11168. +
  11169. +/** \addtogroup OTDS
  11170. + * @{
  11171. + */
  11172. +/*!
  11173. + Over Temperature Protection alarm
  11174. + * - 0 = Temperature To High
  11175. + * - 1 = Temperature OK
  11176. +*/
  11177. +#define TFA98XX_STATUSREG_OTDS (0x1<<2)
  11178. +#define TFA98XX_STATUSREG_OTDS_POS 2
  11179. +#define TFA98XX_STATUSREG_OTDS_LEN 1
  11180. +#define TFA98XX_STATUSREG_OTDS_MAX 1
  11181. +#define TFA98XX_STATUSREG_OTDS_MSK 0x4
  11182. +/** @} */
  11183. +
  11184. +/** \addtogroup OVDS
  11185. + * @{
  11186. + */
  11187. +/*!
  11188. + Over Voltage Protection alarm
  11189. + * - 0 = VddP is To High
  11190. + * - 1 = VddP is OK
  11191. +*/
  11192. +#define TFA98XX_STATUSREG_OVDS (0x1<<3)
  11193. +#define TFA98XX_STATUSREG_OVDS_POS 3
  11194. +#define TFA98XX_STATUSREG_OVDS_LEN 1
  11195. +#define TFA98XX_STATUSREG_OVDS_MAX 1
  11196. +#define TFA98XX_STATUSREG_OVDS_MSK 0x8
  11197. +/** @} */
  11198. +
  11199. +/** \addtogroup UVDS
  11200. + * @{
  11201. + */
  11202. +/*!
  11203. + Under Voltage Proection alarm
  11204. + * - 0 = VddP is too low
  11205. + * - 1 = VddP is OK
  11206. +*/
  11207. +#define TFA98XX_STATUSREG_UVDS (0x1<<4)
  11208. +#define TFA98XX_STATUSREG_UVDS_POS 4
  11209. +#define TFA98XX_STATUSREG_UVDS_LEN 1
  11210. +#define TFA98XX_STATUSREG_UVDS_MAX 1
  11211. +#define TFA98XX_STATUSREG_UVDS_MSK 0x10
  11212. +/** @} */
  11213. +
  11214. +/** \addtogroup OCDS
  11215. + * @{
  11216. + */
  11217. +/*!
  11218. + Over Current Protection alarm
  11219. + * - 0 = Current is OK
  11220. + * - 1 = Current is to High
  11221. +*/
  11222. +#define TFA98XX_STATUSREG_OCDS (0x1<<5)
  11223. +#define TFA98XX_STATUSREG_OCDS_POS 5
  11224. +#define TFA98XX_STATUSREG_OCDS_LEN 1
  11225. +#define TFA98XX_STATUSREG_OCDS_MAX 1
  11226. +#define TFA98XX_STATUSREG_OCDS_MSK 0x20
  11227. +/** @} */
  11228. +
  11229. +/** \addtogroup CLKS
  11230. + * @{
  11231. + */
  11232. +/*!
  11233. + Clocks stable flag
  11234. + * - 0 = Clock is unstable
  11235. + * - 1 = Clock is Stable
  11236. +*/
  11237. +#define TFA98XX_STATUSREG_CLKS (0x1<<6)
  11238. +#define TFA98XX_STATUSREG_CLKS_POS 6
  11239. +#define TFA98XX_STATUSREG_CLKS_LEN 1
  11240. +#define TFA98XX_STATUSREG_CLKS_MAX 1
  11241. +#define TFA98XX_STATUSREG_CLKS_MSK 0x40
  11242. +/** @} */
  11243. +
  11244. +/** \addtogroup CLIPS
  11245. + * @{
  11246. + */
  11247. +/*!
  11248. + Amplifier clipping
  11249. + * - 0 = Not clipping
  11250. + * - 1 = Clipping
  11251. +*/
  11252. +#define TFA98XX_STATUSREG_CLIPS (0x1<<7)
  11253. +#define TFA98XX_STATUSREG_CLIPS_POS 7
  11254. +#define TFA98XX_STATUSREG_CLIPS_LEN 1
  11255. +#define TFA98XX_STATUSREG_CLIPS_MAX 1
  11256. +#define TFA98XX_STATUSREG_CLIPS_MSK 0x80
  11257. +/** @} */
  11258. +
  11259. +/** \addtogroup MTPB
  11260. + * @{
  11261. + */
  11262. +/*!
  11263. + MTP busy
  11264. + * - 0 = MTP is idle
  11265. + * - 1 = MTP is busy copying data to/from I2C registers
  11266. +*/
  11267. +#define TFA98XX_STATUSREG_MTPB (0x1<<8)
  11268. +#define TFA98XX_STATUSREG_MTPB_POS 8
  11269. +#define TFA98XX_STATUSREG_MTPB_LEN 1
  11270. +#define TFA98XX_STATUSREG_MTPB_MAX 1
  11271. +#define TFA98XX_STATUSREG_MTPB_MSK 0x100
  11272. +/** @} */
  11273. +
  11274. +/** \addtogroup DCCS
  11275. + * @{
  11276. + */
  11277. +/*!
  11278. + * - 0 = Vboost not in window
  11279. + * - 1 = Vboost in window (OK)
  11280. +*/
  11281. +#define TFA9887_STATUSREG_DCCS (0x1<<9)
  11282. +#define TFA9887_STATUSREG_DCCS_POS 9
  11283. +#define TFA9887_STATUSREG_DCCS_MAX 1
  11284. +#define TFA9887_STATUSREG_DCCS_MSK 0x200
  11285. +#define TFA9890_STATUSREG_DCCS (0x1<<9)
  11286. +#define TFA9890_STATUSREG_DCCS_POS 9
  11287. +#define TFA9890_STATUSREG_DCCS_MAX 1
  11288. +#define TFA9890_STATUSREG_DCCS_MSK 0x200
  11289. +#define TFA9895_STATUSREG_DCCS (0x1<<9)
  11290. +#define TFA9895_STATUSREG_DCCS_POS 9
  11291. +#define TFA9895_STATUSREG_DCCS_MAX 1
  11292. +#define TFA9895_STATUSREG_DCCS_MSK 0x200
  11293. +/** @} */
  11294. +
  11295. +
  11296. +/** \addtogroup NOCLK
  11297. + * @{
  11298. + */
  11299. +/*!
  11300. + Flag lost clock from clock generation unit
  11301. + * - 1 = PLL reference clock input disappeared
  11302. + * - 0 = PLL reference clock detected
  11303. +*/
  11304. +#define TFA9897_STATUSREG_NOCLK (0x1<<9)
  11305. +#define TFA9897_STATUSREG_NOCLK_POS 9
  11306. +#define TFA9897_STATUSREG_NOCLK_LEN 1
  11307. +#define TFA9897_STATUSREG_NOCLK_MAX 1
  11308. +#define TFA9897_STATUSREG_NOCLK_MSK 0x200
  11309. +/** @} */
  11310. +
  11311. +/** \addtogroup SPKS
  11312. + * @{
  11313. + */
  11314. +/*!
  11315. + Speaker error flag
  11316. + * - 0 = Speaker is OK
  11317. + * - 1 = Speaker error
  11318. +*/
  11319. +#define TFA98XX_STATUSREG_SPKS (0x1<<10)
  11320. +#define TFA98XX_STATUSREG_SPKS_POS 10
  11321. +#define TFA98XX_STATUSREG_SPKS_LEN 1
  11322. +#define TFA98XX_STATUSREG_SPKS_MAX 1
  11323. +#define TFA98XX_STATUSREG_SPKS_MSK 0x400
  11324. +/** @} */
  11325. +
  11326. +/** \addtogroup ACS
  11327. + * @{
  11328. + */
  11329. +/*!
  11330. + Cold Start flag
  11331. + * - 0 = Not a cold start, already running
  11332. + * - 1 = Cold start (via POR)
  11333. +*/
  11334. +#define TFA98XX_STATUSREG_ACS (0x1<<11)
  11335. +#define TFA98XX_STATUSREG_ACS_POS 11
  11336. +#define TFA98XX_STATUSREG_ACS_LEN 1
  11337. +#define TFA98XX_STATUSREG_ACS_MAX 1
  11338. +#define TFA98XX_STATUSREG_ACS_MSK 0x800
  11339. +/** @} */
  11340. +
  11341. +/** \addtogroup SWS
  11342. + * @{
  11343. + */
  11344. +/*!
  11345. + Flag Engage
  11346. + * - 0 = amplifier is not switching
  11347. + * - 1 = amplifier is switching
  11348. +*/
  11349. +#define TFA98XX_STATUSREG_SWS (0x1<<12)
  11350. +#define TFA98XX_STATUSREG_SWS_POS 12
  11351. +#define TFA98XX_STATUSREG_SWS_LEN 1
  11352. +#define TFA98XX_STATUSREG_SWS_MAX 1
  11353. +#define TFA98XX_STATUSREG_SWS_MSK 0x1000
  11354. +/** @} */
  11355. +
  11356. +/** \addtogroup WDS
  11357. + * @{
  11358. + */
  11359. +/*!
  11360. + Flag watchdog reset
  11361. + * - 0 = no reset due to watchdog
  11362. + * - 1 = reset due to watchdog
  11363. +*/
  11364. +#define TFA98XX_STATUSREG_WDS (0x1<<13)
  11365. +#define TFA98XX_STATUSREG_WDS_POS 13
  11366. +#define TFA98XX_STATUSREG_WDS_LEN 1
  11367. +#define TFA98XX_STATUSREG_WDS_MAX 1
  11368. +#define TFA98XX_STATUSREG_WDS_MSK 0x2000
  11369. +/** @} */
  11370. +
  11371. +/** \addtogroup AMPS
  11372. + * @{
  11373. + */
  11374. +/*!
  11375. + Amplifier is enabled by manager
  11376. + * - 0 = amplifier is not enabled
  11377. + * - 1 = amplifier is enabled
  11378. +*/
  11379. +#define TFA98XX_STATUSREG_AMPS (0x1<<14)
  11380. +#define TFA98XX_STATUSREG_AMPS_POS 14
  11381. +#define TFA98XX_STATUSREG_AMPS_LEN 1
  11382. +#define TFA98XX_STATUSREG_AMPS_MAX 1
  11383. +#define TFA98XX_STATUSREG_AMPS_MSK 0x4000
  11384. +/** @} */
  11385. +
  11386. +/** \addtogroup AREFS
  11387. + * @{
  11388. + */
  11389. +/*!
  11390. + References are enabled by manager
  11391. + * - 0 = references are not enabled
  11392. + * - 1 = references are enabled
  11393. +*/
  11394. +#define TFA98XX_STATUSREG_AREFS (0x1<<15)
  11395. +#define TFA98XX_STATUSREG_AREFS_POS 15
  11396. +#define TFA98XX_STATUSREG_AREFS_LEN 1
  11397. +#define TFA98XX_STATUSREG_AREFS_MAX 1
  11398. +#define TFA98XX_STATUSREG_AREFS_MSK 0x8000
  11399. +/** @} */
  11400. +
  11401. +/** @} */
  11402. +
  11403. +/** BatteryVoltage Register ($01) ********************************************/
  11404. +
  11405. +/** \addtogroup _0x01_BatteryVoltage
  11406. + * @{
  11407. + */
  11408. +#define TFA98XX_BATTERYVOLTAGE 0x01
  11409. +/** \addtogroup BATS
  11410. + * @{
  11411. + */
  11412. +/*!
  11413. + Battery voltage readout; 0[V]..5.5[V]
  11414. +*/
  11415. +#define TFA98XX_BATTERYVOLTAGE_BATS (0x3ff<<0)
  11416. +#define TFA98XX_BATTERYVOLTAGE_BATS_POS 0
  11417. +#define TFA98XX_BATTERYVOLTAGE_BATS_LEN 10
  11418. +#define TFA98XX_BATTERYVOLTAGE_BATS_MAX 1023
  11419. +#define TFA98XX_BATTERYVOLTAGE_BATS_MSK 0x3ff
  11420. +/** @} */
  11421. +
  11422. +/** \addtogroup 10
  11423. + * @{
  11424. + */
  11425. +/*!
  11426. + not used
  11427. +*/
  11428. +#define TFA98XX_BATTERYVOLTAGE_10 (0x3f<<10)
  11429. +#define TFA98XX_BATTERYVOLTAGE_10_POS 10
  11430. +#define TFA98XX_BATTERYVOLTAGE_10_LEN 6
  11431. +#define TFA98XX_BATTERYVOLTAGE_10_MAX 63
  11432. +#define TFA98XX_BATTERYVOLTAGE_10_MSK 0xfc00
  11433. +/** @} */
  11434. +
  11435. +/** @} */
  11436. +
  11437. +/** Temperature Register ($02) ********************************************/
  11438. +
  11439. +/** \addtogroup _0x02_Temperature
  11440. + * @{
  11441. + */
  11442. +#define TFA98XX_TEMPERATURE 0x02
  11443. +/** \addtogroup TEMPS
  11444. + * @{
  11445. + */
  11446. +/*!
  11447. + Temperature readout
  11448. +*/
  11449. +#define TFA98XX_TEMPERATURE_TEMPS (0x1ff<<0)
  11450. +#define TFA98XX_TEMPERATURE_TEMPS_POS 0
  11451. +#define TFA98XX_TEMPERATURE_TEMPS_LEN 9
  11452. +#define TFA98XX_TEMPERATURE_TEMPS_MAX 511
  11453. +#define TFA98XX_TEMPERATURE_TEMPS_MSK 0x1ff
  11454. +/** @} */
  11455. +
  11456. +/** \addtogroup 9
  11457. + * @{
  11458. + */
  11459. +/*!
  11460. + not used
  11461. +*/
  11462. +#define TFA98XX_TEMPERATURE_9 (0x7f<<9)
  11463. +#define TFA98XX_TEMPERATURE_9_POS 9
  11464. +#define TFA98XX_TEMPERATURE_9_LEN 7
  11465. +#define TFA98XX_TEMPERATURE_9_MAX 127
  11466. +#define TFA98XX_TEMPERATURE_9_MSK 0xfe00
  11467. +/** @} */
  11468. +
  11469. +/** @} */
  11470. +
  11471. +/** RevisionNumber Register ($03) ********************************************/
  11472. +
  11473. +/** \addtogroup _0x03_RevisionNumber
  11474. + * @{
  11475. + */
  11476. +#define TFA98XX_REVISIONNUMBER 0x03
  11477. +/** \addtogroup REV
  11478. + * @{
  11479. + */
  11480. +/*!
  11481. + Device type number = 97
  11482. +*/
  11483. +#define TFA98XX_REVISIONNUMBER_REV (0xff<<0)
  11484. +#define TFA98XX_REVISIONNUMBER_REV_POS 0
  11485. +#define TFA98XX_REVISIONNUMBER_REV_LEN 8
  11486. +#define TFA98XX_REVISIONNUMBER_REV_MAX 255
  11487. +#define TFA98XX_REVISIONNUMBER_REV_MSK 0xff
  11488. +/** @} */
  11489. +
  11490. +/** @} */
  11491. +
  11492. +/** AudioReg Register ($04) ********************************************/
  11493. +
  11494. +/** \addtogroup _0x04_AudioReg_TFA9897
  11495. + * @{
  11496. + */
  11497. +#define TFA9897_AUDIOREG 0x04
  11498. +/** \addtogroup 0
  11499. + * @{
  11500. + */
  11501. +/*!
  11502. + reserved
  11503. +*/
  11504. +#define TFA9897_AUDIOREG_0 (0x7<<0)
  11505. +#define TFA9897_AUDIOREG_0_POS 0
  11506. +#define TFA9897_AUDIOREG_0_LEN 3
  11507. +#define TFA9897_AUDIOREG_0_MAX 7
  11508. +#define TFA9897_AUDIOREG_0_MSK 0x7
  11509. +/** @} */
  11510. +
  11511. +/** \addtogroup CHS12
  11512. + * @{
  11513. + */
  11514. +/*!
  11515. + Channel Selection TDM input for Coolflux
  11516. + * - 0 = Stereo
  11517. + * - 1 = Left [default]
  11518. + * - 2 = Right
  11519. + * - 3 = Mono =(L+R)/2
  11520. +*/
  11521. +#define TFA9897_AUDIOREG_CHS12 (0x3<<3)
  11522. +#define TFA9897_AUDIOREG_CHS12_POS 3
  11523. +#define TFA9897_AUDIOREG_CHS12_LEN 2
  11524. +#define TFA9897_AUDIOREG_CHS12_MAX 3
  11525. +#define TFA9897_AUDIOREG_CHS12_MSK 0x18
  11526. +/** @} */
  11527. +
  11528. +/** \addtogroup ILVL
  11529. + * @{
  11530. + */
  11531. +/*!
  11532. + Input level selection control
  11533. + * - 0 = input is -6 dbFS, attenuation is bypassed
  11534. + * - 1 = input is 0 dbFS, attenuated by 6 dBFS
  11535. +*/
  11536. +#define TFA9897_AUDIOREG_ILVL (0x1<<5)
  11537. +#define TFA9897_AUDIOREG_ILVL_POS 5
  11538. +#define TFA9897_AUDIOREG_ILVL_LEN 1
  11539. +#define TFA9897_AUDIOREG_ILVL_MAX 1
  11540. +#define TFA9897_AUDIOREG_ILVL_MSK 0x20
  11541. +/** @} */
  11542. +
  11543. +/** \addtogroup CHSA
  11544. + * @{
  11545. + */
  11546. +/*!
  11547. + Input selection for amplifier
  11548. + * - 0 = TDM data channel1, CoolFlux bypassed
  11549. + * - 1 = TDM data channel2, CoolFlux bypassed
  11550. + * - 2 = Coolflux DSP Output [default]
  11551. + * - 3 = Coolflux DSP Output
  11552. +*/
  11553. +#define TFA9897_AUDIOREG_CHSA (0x3<<6)
  11554. +#define TFA9897_AUDIOREG_CHSA_POS 6
  11555. +#define TFA9897_AUDIOREG_CHSA_LEN 2
  11556. +#define TFA9897_AUDIOREG_CHSA_MAX 3
  11557. +#define TFA9897_AUDIOREG_CHSA_MSK 0xc0
  11558. +/** @} */
  11559. +
  11560. +/** \addtogroup 8
  11561. + * @{
  11562. + */
  11563. +/*!
  11564. +
  11565. +*/
  11566. +#define TFA9897_AUDIOREG_8 (0xf<<8)
  11567. +#define TFA9897_AUDIOREG_8_POS 8
  11568. +#define TFA9897_AUDIOREG_8_LEN 4
  11569. +#define TFA9897_AUDIOREG_8_MAX 15
  11570. +#define TFA9897_AUDIOREG_8_MSK 0xf00
  11571. +/** @} */
  11572. +
  11573. +/** \addtogroup AUDFS
  11574. + * @{
  11575. + */
  11576. +/*!
  11577. + Audio sample rate setting
  11578. + * - 6 = 32 KHz
  11579. + * - 7 = 44.1 kHz
  11580. + * - 8 = 48 KHz [default]
  11581. + * - Others = Reserved
  11582. +*/
  11583. +#define TFA9897_AUDIOREG_AUDFS (0xf<<12)
  11584. +#define TFA9897_AUDIOREG_AUDFS_POS 12
  11585. +#define TFA9897_AUDIOREG_AUDFS_LEN 4
  11586. +#define TFA9897_AUDIOREG_AUDFS_MAX 15
  11587. +#define TFA9897_AUDIOREG_AUDFS_MSK 0xf000
  11588. +/** @} */
  11589. +
  11590. +/** @} */
  11591. +
  11592. +/** I2SReg Register ($04) ********************************************/
  11593. +
  11594. +/** \addtogroup _0x04_I2SReg_TFA9887
  11595. + * @{
  11596. + */
  11597. +#define TFA9887_I2SREG 0x04
  11598. +/** \addtogroup I2SF
  11599. + * @{
  11600. + */
  11601. +/*!
  11602. + I2SFormat data 1, 2 input and output:
  11603. + * - 0=not used
  11604. + * - 1=not used
  11605. + * - 2=MSB justify
  11606. + * - 3=Philips standard I2S (default)
  11607. + * - 4=LSB Justify 16 bits
  11608. + * - 5=LSB Justify 18 bits
  11609. + * - 6=LSB Justify 20 bits
  11610. + * - 7=LSB Justify 24 bits
  11611. +*/
  11612. +#define TFA9887_I2SREG_I2SF (0x7<<0)
  11613. +#define TFA9887_I2SREG_I2SF_POS 0
  11614. +#define TFA9887_I2SREG_I2SF_LEN 3
  11615. +#define TFA9887_I2SREG_I2SF_MAX 7
  11616. +#define TFA9887_I2SREG_I2SF_MSK 0x7
  11617. +/** @} */
  11618. +
  11619. +/** \addtogroup CHS12
  11620. + * @{
  11621. + */
  11622. +/*!
  11623. + ChannelSelection data1 input (In CoolFlux)
  11624. + * - 0=Stereo
  11625. + * - 1=Left
  11626. + * - 2=Right
  11627. + * - 3=Mono =(L+R)/2
  11628. +*/
  11629. +#define TFA9887_I2SREG_CHS12 (0x3<<3)
  11630. +#define TFA9887_I2SREG_CHS12_POS 3
  11631. +#define TFA9887_I2SREG_CHS12_LEN 2
  11632. +#define TFA9887_I2SREG_CHS12_MAX 3
  11633. +#define TFA9887_I2SREG_CHS12_MSK 0x18
  11634. +/** @} */
  11635. +
  11636. +/** \addtogroup CHS3
  11637. + * @{
  11638. + */
  11639. +/*!
  11640. + ChannelSelection data 3 input (coolflux input, the DCDC converter gets the other signal)
  11641. + * - 0=Left
  11642. + * - 1=Right
  11643. +*/
  11644. +#define TFA9887_I2SREG_CHS3 (0x1<<5)
  11645. +#define TFA9887_I2SREG_CHS3_POS 5
  11646. +#define TFA9887_I2SREG_CHS3_LEN 1
  11647. +#define TFA9887_I2SREG_CHS3_MAX 1
  11648. +#define TFA9887_I2SREG_CHS3_MSK 0x20
  11649. +/** @} */
  11650. +
  11651. +/** \addtogroup CHSA
  11652. + * @{
  11653. + */
  11654. +/*!
  11655. + Input selection for amplifier
  11656. + * - 00b I2S input 1 left channel (CoolFlux bypassed)
  11657. + * - 01b I2S input 1 Right channel (CoolFlux bypassed)
  11658. + * - 10b Output Coolflux DSP
  11659. + * - 11b Output Collflux DSP
  11660. +*/
  11661. +#define TFA9887_I2SREG_CHSA (0x3<<6)
  11662. +#define TFA9887_I2SREG_CHSA_POS 6
  11663. +#define TFA9887_I2SREG_CHSA_LEN 2
  11664. +#define TFA9887_I2SREG_CHSA_MAX 3
  11665. +#define TFA9887_I2SREG_CHSA_MSK 0xc0
  11666. +/** @} */
  11667. +
  11668. +/** \addtogroup I2SDOE
  11669. + * @{
  11670. + */
  11671. +/*!
  11672. + data out tristate 0 = tristate
  11673. +*/
  11674. +#define TFA9887_I2SREG_I2SDOE (0x1<<11)
  11675. +#define TFA9887_I2SREG_I2SDOE_POS 11
  11676. +#define TFA9887_I2SREG_I2SDOE_LEN 1
  11677. +#define TFA9887_I2SREG_I2SDOE_MAX 1
  11678. +#define TFA9887_I2SREG_I2SDOE_MSK 0x800
  11679. +/** @} */
  11680. +
  11681. +/** \addtogroup I2SSR
  11682. + * @{
  11683. + */
  11684. +/*!
  11685. + sample rate setting
  11686. + * - 0000b 8 kHz
  11687. + * - 0001b 11.025 kHz
  11688. + * - 0010b 12 kHz
  11689. + * - 0011b 16 kHz
  11690. + * - 0100b 22.05 kHz
  11691. + * - 0101b 24 kHz
  11692. + * - 0110b 32 kHz
  11693. + * - 0111b 44.1 kHz
  11694. + * - 1000b* 48 KHz
  11695. +*/
  11696. +#define TFA9887_I2SREG_I2SSR (0xf<<12)
  11697. +#define TFA9887_I2SREG_I2SSR_POS 12
  11698. +#define TFA9887_I2SREG_I2SSR_LEN 4
  11699. +#define TFA9887_I2SREG_I2SSR_MAX 15
  11700. +#define TFA9887_I2SREG_I2SSR_MSK 0xf000
  11701. +/** @} */
  11702. +
  11703. +/** @} */
  11704. +
  11705. +/** I2SReg Register ($04) ********************************************/
  11706. +
  11707. +/** \addtogroup _0x04_I2SReg
  11708. + * @{
  11709. + */
  11710. +#define TFA98XX_I2SREG 0x04
  11711. +/** \addtogroup I2SF
  11712. + * @{
  11713. + */
  11714. +/*!
  11715. + I2SFormat data 1 input:
  11716. + * - 0 = Philips standard I2S
  11717. + * - 1 = Philips standard I2S
  11718. + * - 2 = MSB justify
  11719. + * - 3 = Philips standard I2S [default]
  11720. + * - 4 = LSB Justify 16 bits
  11721. + * - 5 = LSB Justify 18 bits
  11722. + * - 6 = LSB Justify 20 bits
  11723. + * - 7 = LSB Justify 24 bits
  11724. +*/
  11725. +#define TFA98XX_I2SREG_I2SF (0x7<<0)
  11726. +#define TFA98XX_I2SREG_I2SF_POS 0
  11727. +#define TFA98XX_I2SREG_I2SF_LEN 3
  11728. +#define TFA98XX_I2SREG_I2SF_MAX 7
  11729. +#define TFA98XX_I2SREG_I2SF_MSK 0x7
  11730. +/** @} */
  11731. +
  11732. +/** \addtogroup CHS12
  11733. + * @{
  11734. + */
  11735. +/*!
  11736. + ChannelSelection data1 input (In CoolFlux)
  11737. + * - 0 = Stereo
  11738. + * - 1 = Left [default]
  11739. + * - 2 = Right
  11740. + * - 3 = Mono =(L+R)/2
  11741. +*/
  11742. +#define TFA98XX_I2SREG_CHS12 (0x3<<3)
  11743. +#define TFA98XX_I2SREG_CHS12_POS 3
  11744. +#define TFA98XX_I2SREG_CHS12_LEN 2
  11745. +#define TFA98XX_I2SREG_CHS12_MAX 3
  11746. +#define TFA98XX_I2SREG_CHS12_MSK 0x18
  11747. +/** @} */
  11748. +
  11749. +/** \addtogroup CHS3
  11750. + * @{
  11751. + */
  11752. +/*!
  11753. + ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal)
  11754. + * - 0 = Left channel to CF DSP right channel to other vamp mux [default]
  11755. + * - 1 = Right channel to CF DSP left channel to other vamp mux
  11756. +*/
  11757. +#define TFA98XX_I2SREG_CHS3 (0x1<<5)
  11758. +#define TFA98XX_I2SREG_CHS3_POS 5
  11759. +#define TFA98XX_I2SREG_CHS3_LEN 1
  11760. +#define TFA98XX_I2SREG_CHS3_MAX 1
  11761. +#define TFA98XX_I2SREG_CHS3_MSK 0x20
  11762. +/** @} */
  11763. +
  11764. +/** \addtogroup CHSA
  11765. + * @{
  11766. + */
  11767. +/*!
  11768. + Input selection for amplifier
  11769. + * - 0 = I2S input 1 left channel (CoolFlux bypassed)
  11770. + * - 1 = I2S input 1 Right channel (CoolFlux bypassed)
  11771. + * - 2 = Output Coolflux DSP [default]
  11772. + * - 3 = Output Collflux DSP
  11773. +*/
  11774. +#define TFA98XX_I2SREG_CHSA (0x3<<6)
  11775. +#define TFA98XX_I2SREG_CHSA_POS 6
  11776. +#define TFA98XX_I2SREG_CHSA_LEN 2
  11777. +#define TFA98XX_I2SREG_CHSA_MAX 3
  11778. +#define TFA98XX_I2SREG_CHSA_MSK 0xc0
  11779. +/** @} */
  11780. +
  11781. +/** \addtogroup I2SDOC
  11782. + * @{
  11783. + */
  11784. +/*!
  11785. + selection data out
  11786. + * - 0 = I2S-TX [default]
  11787. + * - 1 = datai1
  11788. + * - 2 = datai2
  11789. + * - 3 = datai3
  11790. +*/
  11791. +#define TFA9890_I2SREG_I2SDOC (0x3<<8)
  11792. +#define TFA9890_I2SREG_I2SDOC_POS 8
  11793. +#define TFA9890_I2SREG_I2SDOC_LEN 2
  11794. +#define TFA9890_I2SREG_I2SDOC_MAX 3
  11795. +#define TFA9890_I2SREG_I2SDOC_MSK 0x300
  11796. +/** @} */
  11797. +
  11798. +/** \addtogroup DISP
  11799. + * @{
  11800. + */
  11801. +/*!
  11802. + idp protection
  11803. + * - 0 = on
  11804. + * - 1 = off
  11805. +*/
  11806. +#define TFA9890_I2SREG_DISP (0x1<<10)
  11807. +#define TFA9890_I2SREG_DISP_POS 10
  11808. +#define TFA9890_I2SREG_DISP_LEN 1
  11809. +#define TFA9890_I2SREG_DISP_MAX 1
  11810. +#define TFA9890_I2SREG_DISP_MSK 0x400
  11811. +/** @} */
  11812. +
  11813. +/** \addtogroup I2SDOE
  11814. + * @{
  11815. + */
  11816. +/*!
  11817. + Enable data output
  11818. + * - 0 = data output in tristate
  11819. + * - 1 = normal mode [default]
  11820. +*/
  11821. +#define TFA98XX_I2SREG_I2SDOE (0x1<<11)
  11822. +#define TFA98XX_I2SREG_I2SDOE_POS 11
  11823. +#define TFA98XX_I2SREG_I2SDOE_LEN 1
  11824. +#define TFA98XX_I2SREG_I2SDOE_MAX 1
  11825. +#define TFA98XX_I2SREG_I2SDOE_MSK 0x800
  11826. +/** @} */
  11827. +
  11828. +/** \addtogroup I2SSR
  11829. + * @{
  11830. + */
  11831. +/*!
  11832. + sample rate setting
  11833. + * - 0 = 8kHk
  11834. + * - 1 =11.025kHz
  11835. + * - 2 = 12kHz
  11836. + * - 3 = 16kHz
  11837. + * - 4 = 22.05kHz
  11838. + * - 5 = 24kHz
  11839. + * - 6 = 32kHz
  11840. + * - 7 = 44.1kHz
  11841. + * - 8 = 48kHz [default]
  11842. +*/
  11843. +#define TFA98XX_I2SREG_I2SSR (0xf<<12)
  11844. +#define TFA98XX_I2SREG_I2SSR_POS 12
  11845. +#define TFA98XX_I2SREG_I2SSR_LEN 4
  11846. +#define TFA98XX_I2SREG_I2SSR_MAX 15
  11847. +#define TFA98XX_I2SREG_I2SSR_MSK 0xf000
  11848. +/** @} */
  11849. +
  11850. +/** @} */
  11851. +
  11852. +/** bat_prot Register ($05) ********************************************/
  11853. +
  11854. +/** \addtogroup _0x05_bat_prot
  11855. + * @{
  11856. + */
  11857. +#define TFA98XX_BAT_PROT 0x05
  11858. +/** \addtogroup BSSCR
  11859. + * @{
  11860. + */
  11861. +/*!
  11862. + Protection Attack Time
  11863. + * - 0 = 0.56 dB/Sample
  11864. + * - 1 = 1.12 dB/sample
  11865. + * - 2 = 2.32 dB/Sample [default]
  11866. + * - 3 = infinite dB/Sample
  11867. +*/
  11868. +#define TFA989X_BAT_PROT_BSSCR (0x3<<0)
  11869. +#define TFA989X_BAT_PROT_BSSCR_POS 0
  11870. +#define TFA989X_BAT_PROT_BSSCR_LEN 2
  11871. +#define TFA989X_BAT_PROT_BSSCR_MAX 3
  11872. +#define TFA989X_BAT_PROT_BSSCR_MSK 0x3
  11873. +/** @} */
  11874. +
  11875. +/** \addtogroup BSST
  11876. + * @{
  11877. + */
  11878. +/*!
  11879. + ProtectionThreshold
  11880. + * - normal steep
  11881. + * - 0 = 2.73V 2.99V
  11882. + * - 1 = 2.83V 3.09V
  11883. + * - 2 = 2.93V 3.19V
  11884. + * - 3 = 3.03V 3.29V
  11885. + * - 4 = 3.13V 3.39V (default)
  11886. + * - 5 = 3.23V 3.49V
  11887. + * - 6 = 3.33V 3.59V
  11888. + * - 7 = 3.43V 3.69V
  11889. + * - 8 = 3.53V 3.79V
  11890. + * - 9 = 3.63V 3.89V
  11891. + * - 10 = 3.73V 3.99V
  11892. + * - 11 = 3.83V 4.09V
  11893. + * - 12 = 3.93V 4.19V
  11894. + * - 13 = 4.03V 4.29V
  11895. + * - 14 = 4.13V 4.39V
  11896. + * - 15 = 4.23V 4.49V
  11897. +*/
  11898. +#define TFA989X_BAT_PROT_BSST (0xf<<2)
  11899. +#define TFA989X_BAT_PROT_BSST_POS 2
  11900. +#define TFA989X_BAT_PROT_BSST_LEN 4
  11901. +#define TFA989X_BAT_PROT_BSST_MAX 15
  11902. +#define TFA989X_BAT_PROT_BSST_MSK 0x3c
  11903. +/** @} */
  11904. +
  11905. +/** \addtogroup BSSRL
  11906. + * @{
  11907. + */
  11908. +/*!
  11909. + Protection Maximum Reduction
  11910. + * - 0 = 3V
  11911. + * - 1 = 4V
  11912. + * - 2 = 5V [default]
  11913. + * - 3 = not permitted
  11914. +*/
  11915. +#define TFA98XX_BAT_PROT_BSSRL (0x3<<6)
  11916. +#define TFA98XX_BAT_PROT_BSSRL_POS 6
  11917. +#define TFA98XX_BAT_PROT_BSSRL_LEN 2
  11918. +#define TFA98XX_BAT_PROT_BSSRL_MAX 3
  11919. +#define TFA98XX_BAT_PROT_BSSRL_MSK 0xc0
  11920. +/** @} */
  11921. +
  11922. +/** \addtogroup BSSRR
  11923. + * @{
  11924. + */
  11925. +/*!
  11926. + Battery Protection Release Time
  11927. + * - 0 = 0.4 sec
  11928. + * - 1 = 0.8 sec
  11929. + * - 2 = 1.2 sec
  11930. + * - 3 = 1.6 sec [default]
  11931. + * - 4 = 2 sec
  11932. + * - 5 = 2,4 sec
  11933. + * - 6 = 2.8 sec
  11934. + * - 7 = 3.2 sec
  11935. +*/
  11936. +#define TFA98XX_BAT_PROT_BSSRR (0x7<<8)
  11937. +#define TFA98XX_BAT_PROT_BSSRR_POS 8
  11938. +#define TFA98XX_BAT_PROT_BSSRR_LEN 3
  11939. +#define TFA98XX_BAT_PROT_BSSRR_MAX 7
  11940. +#define TFA98XX_BAT_PROT_BSSRR_MSK 0x700
  11941. +/** @} */
  11942. +
  11943. +/** \addtogroup BSSHY
  11944. + * @{
  11945. + */
  11946. +/*!
  11947. + Battery Protection Hysterese
  11948. + * - 0 = No hysterese
  11949. + * - 1 = 0.05V
  11950. + * - 2 = 0.1V [default]
  11951. + * - 3 = 0.2V
  11952. +*/
  11953. +#define TFA98XX_BAT_PROT_BSSHY (0x3<<11)
  11954. +#define TFA98XX_BAT_PROT_BSSHY_POS 11
  11955. +#define TFA98XX_BAT_PROT_BSSHY_LEN 2
  11956. +#define TFA98XX_BAT_PROT_BSSHY_MAX 3
  11957. +#define TFA98XX_BAT_PROT_BSSHY_MSK 0x1800
  11958. +/** @} */
  11959. +
  11960. +/** \addtogroup 13
  11961. + * @{
  11962. + */
  11963. +/*!
  11964. + reset clipper
  11965. + * - 0 = clipper is not reset if CF is bypassed [default]
  11966. + * - 1 = reset the clipper via I2C in case the CF is bypassed
  11967. +*/
  11968. +#define TFA98XX_BAT_PROT_13 (0x1<<13)
  11969. +#define TFA98XX_BAT_PROT_13_POS 13
  11970. +#define TFA98XX_BAT_PROT_13_LEN 1
  11971. +#define TFA98XX_BAT_PROT_13_MAX 1
  11972. +#define TFA98XX_BAT_PROT_13_MSK 0x2000
  11973. +/** @} */
  11974. +
  11975. +/** \addtogroup BSSR
  11976. + * @{
  11977. + */
  11978. +/*!
  11979. + battery voltage for I2C read out only
  11980. + * - 0 = minimum battery value [reset]
  11981. + * - 1 = avarage battery value
  11982. +*/
  11983. +#define TFA98XX_BAT_PROT_BSSR (0x1<<14)
  11984. +#define TFA98XX_BAT_PROT_BSSR_POS 14
  11985. +#define TFA98XX_BAT_PROT_BSSR_LEN 1
  11986. +#define TFA98XX_BAT_PROT_BSSR_MAX 1
  11987. +#define TFA98XX_BAT_PROT_BSSR_MSK 0x4000
  11988. +/** @} */
  11989. +
  11990. +/** \addtogroup BSSBY
  11991. + * @{
  11992. + */
  11993. +/*!
  11994. + bypass clipper battery protection
  11995. + * - 0 = clipper active [device default]
  11996. + * - 1 = clipper bypassed [new default]
  11997. +*/
  11998. +#define TFA989X_BAT_PROT_BSSBY (0x1<<15)
  11999. +#define TFA989X_BAT_PROT_BSSBY_POS 15
  12000. +#define TFA989X_BAT_PROT_BSSBY_LEN 1
  12001. +#define TFA989X_BAT_PROT_BSSBY_MAX 1
  12002. +#define TFA989X_BAT_PROT_BSSBY_MSK 0x8000
  12003. +/** @} */
  12004. +
  12005. +/** @} */
  12006. +
  12007. +/** bat_prot Register ($05) ********************************************/
  12008. +
  12009. +/** \addtogroup _0x05_bat_prot_TFA9887
  12010. + * @{
  12011. + */
  12012. +#define TFA9887_BAT_PROT 0x05
  12013. +/** \addtogroup BSSBY
  12014. + * @{
  12015. + */
  12016. +/*!
  12017. +
  12018. +*/
  12019. +#define TFA9887_BAT_PROT_BSSBY (0x1<<0)
  12020. +#define TFA9887_BAT_PROT_BSSBY_POS 0
  12021. +#define TFA9887_BAT_PROT_BSSBY_LEN 1
  12022. +#define TFA9887_BAT_PROT_BSSBY_MAX 1
  12023. +#define TFA9887_BAT_PROT_BSSBY_MSK 0x1
  12024. +/** @} */
  12025. +
  12026. +/** \addtogroup BSSCR
  12027. + * @{
  12028. + */
  12029. +/*!
  12030. + 00 = 0.56 dB/Sample
  12031. + * - 01 = 1.12 dB/sample
  12032. + * - 10 = 2.32 dB/Sample (default)
  12033. + * - 11 = infinite dB/Sample
  12034. +*/
  12035. +#define TFA9887_BAT_PROT_BSSCR (0x3<<1)
  12036. +#define TFA9887_BAT_PROT_BSSCR_POS 1
  12037. +#define TFA9887_BAT_PROT_BSSCR_LEN 2
  12038. +#define TFA9887_BAT_PROT_BSSCR_MAX 3
  12039. +#define TFA9887_BAT_PROT_BSSCR_MSK 0x6
  12040. +/** @} */
  12041. +
  12042. +/** \addtogroup BSST
  12043. + * @{
  12044. + */
  12045. +/*!
  12046. + 000 = 2.92V
  12047. + * - 001 = 3.05 V
  12048. + * - 010 = 3.17
  12049. + * - 011 = 3.3 V
  12050. + * - 100 = 3.42 V
  12051. + * - 101 - 3.55 V (default)
  12052. + * - 110 = 3.67 V
  12053. + * - 111 = 3.8 V
  12054. +*/
  12055. +#define TFA9887_BAT_PROT_BSST (0x7<<3)
  12056. +#define TFA9887_BAT_PROT_BSST_POS 3
  12057. +#define TFA9887_BAT_PROT_BSST_LEN 3
  12058. +#define TFA9887_BAT_PROT_BSST_MAX 7
  12059. +#define TFA9887_BAT_PROT_BSST_MSK 0x38
  12060. +/** @} */
  12061. +
  12062. +/** \addtogroup 13
  12063. + * @{
  12064. + */
  12065. +/*!
  12066. + to reset the clipper via I2C in case the CF is bypassed
  12067. +*/
  12068. +#define TFA9887_BAT_PROT_13 (0x1<<13)
  12069. +#define TFA9887_BAT_PROT_13_POS 13
  12070. +#define TFA9887_BAT_PROT_13_LEN 1
  12071. +#define TFA9887_BAT_PROT_13_MAX 1
  12072. +#define TFA9887_BAT_PROT_13_MSK 0x2000
  12073. +/** @} */
  12074. +
  12075. +/** \addtogroup I2SDOC
  12076. + * @{
  12077. + */
  12078. +/*!
  12079. + selection data out
  12080. + * - 0 = I2S-TX; 1 = datai3
  12081. +*/
  12082. +#define TFA9887_BAT_PROT_I2SDOC (0x1<<15)
  12083. +#define TFA9887_BAT_PROT_I2SDOC_POS 15
  12084. +#define TFA9887_BAT_PROT_I2SDOC_LEN 1
  12085. +#define TFA9887_BAT_PROT_I2SDOC_MAX 1
  12086. +#define TFA9887_BAT_PROT_I2SDOC_MSK 0x8000
  12087. +/** @} */
  12088. +
  12089. +/** @} */
  12090. +
  12091. +/** audio_ctr Register ($06) ********************************************/
  12092. +
  12093. +/** \addtogroup _0x06_audio_ctr
  12094. + * @{
  12095. + */
  12096. +#define TFA98XX_AUDIO_CTR 0x06
  12097. +/** \addtogroup DPSA
  12098. + * @{
  12099. + */
  12100. +/*!
  12101. + Enable dynamic powerstage activation
  12102. + * - 0 = dpsa off
  12103. + * - 1 = dpsa on [default]
  12104. +*/
  12105. +#define TFA98XX_AUDIO_CTR_DPSA (0x1<<0)
  12106. +#define TFA98XX_AUDIO_CTR_DPSA_POS 0
  12107. +#define TFA98XX_AUDIO_CTR_DPSA_LEN 1
  12108. +#define TFA98XX_AUDIO_CTR_DPSA_MAX 1
  12109. +#define TFA98XX_AUDIO_CTR_DPSA_MSK 0x1
  12110. +/** @} */
  12111. +
  12112. +/** \addtogroup control slope
  12113. + * @{
  12114. + */
  12115. +/*!
  12116. + 0 = slope 1
  12117. + 1 = slope 1
  12118. + 2 = slope 1
  12119. + 3 = slope 2
  12120. + 4 = slope 1
  12121. + 5 = slope 2
  12122. + 6 = slope 2
  12123. + 7 = slope 3 [default]
  12124. + 8 = slope 1
  12125. + 9 = slope 2
  12126. + 10 = slope 2
  12127. + 11 = slope 3
  12128. + 12 = slope 2
  12129. + 13 = slope 3
  12130. + 14 = slope 3
  12131. + 15 = maximal
  12132. +*/
  12133. +#define TFA98XX_AUDIO_CTR_AMPSL (0xf<<1)
  12134. +#define TFA98XX_AUDIO_CTR_AMPSL_POS 1
  12135. +#define TFA98XX_AUDIO_CTR_AMPSL_LEN 4
  12136. +#define TFA98XX_AUDIO_CTR_AMPSL_MAX 15
  12137. +#define TFA98XX_AUDIO_CTR_AMPSL_MSK 0x1e
  12138. +/** @} */
  12139. +
  12140. +/** \addtogroup CFSM
  12141. + * @{
  12142. + */
  12143. +/*!
  12144. + Soft mute in CoolFlux
  12145. + * - 0= no mute [default]
  12146. + * - 1= muted
  12147. +*/
  12148. +#define TFA98XX_AUDIO_CTR_CFSM (0x1<<5)
  12149. +#define TFA98XX_AUDIO_CTR_CFSM_POS 5
  12150. +#define TFA98XX_AUDIO_CTR_CFSM_LEN 1
  12151. +#define TFA98XX_AUDIO_CTR_CFSM_MAX 1
  12152. +#define TFA98XX_AUDIO_CTR_CFSM_MSK 0x20
  12153. +/** @} */
  12154. +
  12155. +/** \addtogroup 6
  12156. + * @{
  12157. + */
  12158. +/*!
  12159. +
  12160. +*/
  12161. +#define TFA98XX_AUDIO_CTR_6 (0x1<<6)
  12162. +#define TFA98XX_AUDIO_CTR_6_POS 6
  12163. +#define TFA98XX_AUDIO_CTR_6_LEN 1
  12164. +#define TFA98XX_AUDIO_CTR_6_MAX 1
  12165. +#define TFA98XX_AUDIO_CTR_6_MSK 0x40
  12166. +/** @} */
  12167. +
  12168. +/** \addtogroup BSSS
  12169. + * @{
  12170. + */
  12171. +/*!
  12172. + batsensesteepness
  12173. + * - 0 = 5.4V/V if ctr_supplysense = 1
  12174. + * - 1 = 10.8V/V if ctrl_supplysense = 1
  12175. + * - 0 = 3.13V/V if ctrl_supplysense = 0
  12176. + * - 1 = 6.25V/V if ctrl_supplysense = 0
  12177. +*/
  12178. +#define TFA989X_AUDIO_CTR_BSSS (0x1<<7)
  12179. +#define TFA989X_AUDIO_CTR_BSSS_POS 7
  12180. +#define TFA989X_AUDIO_CTR_BSSS_LEN 1
  12181. +#define TFA989X_AUDIO_CTR_BSSS_MAX 1
  12182. +#define TFA989X_AUDIO_CTR_BSSS_MSK 0x80
  12183. +/** @} */
  12184. +
  12185. +/** \addtogroup VOL
  12186. + * @{
  12187. + */
  12188. +/*!
  12189. + volume control (in CoolFlux)
  12190. +*/
  12191. +#define TFA98XX_AUDIO_CTR_VOL (0xff<<8)
  12192. +#define TFA98XX_AUDIO_CTR_VOL_POS 8
  12193. +#define TFA98XX_AUDIO_CTR_VOL_LEN 8
  12194. +#define TFA98XX_AUDIO_CTR_VOL_MAX 255
  12195. +#define TFA98XX_AUDIO_CTR_VOL_MSK 0xff00
  12196. +/** @} */
  12197. +
  12198. +/** @} */
  12199. +
  12200. +/** DCDCboost Register ($07) ********************************************/
  12201. +
  12202. +/** \addtogroup _0x07_DCDCboost
  12203. + * @{
  12204. + */
  12205. +#define TFA98XX_DCDCBOOST 0x07
  12206. +/** \addtogroup DCVO
  12207. + * @{
  12208. + */
  12209. +/*!
  12210. + Boost Voltage
  12211. + * - 0 = 4.0 V
  12212. + * - 1 = 4.2 V
  12213. + * - 2 = 4.4 V
  12214. + * - 3 = 4.6 V
  12215. + * - 4 = 4.8 V
  12216. + * - 5 = 5.0 V
  12217. + * - 6 = 5.2 V (default)
  12218. + * - 7 = 5.4 V
  12219. +*/
  12220. +#define TFA98XX_DCDCBOOST_DCVO (0x7<<0)
  12221. +#define TFA98XX_DCDCBOOST_DCVO_POS 0
  12222. +#define TFA98XX_DCDCBOOST_DCVO_LEN 3
  12223. +#define TFA98XX_DCDCBOOST_DCVO_MAX 7
  12224. +#define TFA98XX_DCDCBOOST_DCVO_MSK 0x7
  12225. +/** @} */
  12226. +
  12227. +/** \addtogroup DCMCC
  12228. + * @{
  12229. + */
  12230. +/*!
  12231. + for 87,90,95
  12232. + * - 0 = 0.48 A
  12233. + * - 1 = 0.96 A
  12234. + * - 2 = 1.44 A
  12235. + * - 3 = 1.92 A
  12236. + * - 4 = 2.4 A [87/95 default]
  12237. + * - 5 = 2.88 A
  12238. + * - 6 = 3.56 A
  12239. + * - 7 = 3.8 A [90 default]
  12240. +*/
  12241. +#define TFA98XX_DCDCBOOST_DCMCC (0x7<<3)
  12242. +#define TFA98XX_DCDCBOOST_DCMCC_POS 3
  12243. +#define TFA98XX_DCDCBOOST_DCMCC_LEN 3
  12244. +#define TFA98XX_DCDCBOOST_DCMCC_MAX 7
  12245. +#define TFA98XX_DCDCBOOST_DCMCC_MSK 0x38
  12246. +#define TFA9897_DCDCBOOST_DCMCC (0xf<<3)
  12247. +#define TFA9897_DCDCBOOST_DCMCC_POS 3
  12248. +#define TFA9897_DCDCBOOST_DCMCC_LEN 4
  12249. +#define TFA9897_DCDCBOOST_DCMCC_MAX 15
  12250. +#define TFA9897_DCDCBOOST_DCMCC_MSK 0x78
  12251. +
  12252. +/** \addtogroup DCIE
  12253. + * @{
  12254. + */
  12255. +/*!
  12256. + Adaptive / Intelligent boost mode
  12257. + * - 0 = Off
  12258. + * - 1 = On [default]
  12259. +*/
  12260. +#define TFA98XX_DCDCBOOST_DCIE (0x1<<10)
  12261. +#define TFA98XX_DCDCBOOST_DCIE_POS 10
  12262. +#define TFA98XX_DCDCBOOST_DCIE_LEN 1
  12263. +#define TFA98XX_DCDCBOOST_DCIE_MAX 1
  12264. +#define TFA98XX_DCDCBOOST_DCIE_MSK 0x400
  12265. +/** @} */
  12266. +
  12267. +/** \addtogroup DCSR
  12268. + * @{
  12269. + */
  12270. +/*!
  12271. + Soft RampUp/Down mode for DCDC controller
  12272. + * - 0 = Immediate : 0 Cycle
  12273. + * - 1 = Fast (Default) : 32 Cycles/step at 2MHz, 16 cycles/step at 1MHz and 0.5MHz
  12274. +*/
  12275. +#define TFA98XX_DCDCBOOST_DCSR (0x1<<11)
  12276. +#define TFA98XX_DCDCBOOST_DCSR_POS 11
  12277. +#define TFA98XX_DCDCBOOST_DCSR_LEN 1
  12278. +#define TFA98XX_DCDCBOOST_DCSR_MAX 1
  12279. +#define TFA98XX_DCDCBOOST_DCSR_MSK 0x800
  12280. +/** @} */
  12281. +
  12282. +
  12283. +/** @} */
  12284. +
  12285. +/** spkr_calibration Register ($08) ********************************************/
  12286. +
  12287. +/** \addtogroup _0x08_spkr_calibration
  12288. + * @{
  12289. + */
  12290. +#define TFA98XX_SPKR_CALIBRATION 0x08
  12291. +/** \addtogroup TROS
  12292. + * @{
  12293. + */
  12294. +/*!
  12295. + Select external temperature also the ext_temp will be put on the temp read out
  12296. + * - 0 = internal temperature
  12297. + * - 1 = external temperature
  12298. +*/
  12299. +#define TFA98XX_SPKR_CALIBRATION_TROS (0x1<<0)
  12300. +#define TFA98XX_SPKR_CALIBRATION_TROS_POS 0
  12301. +#define TFA98XX_SPKR_CALIBRATION_TROS_LEN 1
  12302. +#define TFA98XX_SPKR_CALIBRATION_TROS_MAX 1
  12303. +#define TFA98XX_SPKR_CALIBRATION_TROS_MSK 0x1
  12304. +/** @} */
  12305. +
  12306. +/** \addtogroup EXTTS
  12307. + * @{
  12308. + */
  12309. +/*!
  12310. + external temperature setting to be given by host
  12311. +*/
  12312. +#define TFA98XX_SPKR_CALIBRATION_EXTTS (0x1ff<<1)
  12313. +#define TFA98XX_SPKR_CALIBRATION_EXTTS_POS 1
  12314. +#define TFA98XX_SPKR_CALIBRATION_EXTTS_LEN 9
  12315. +#define TFA98XX_SPKR_CALIBRATION_EXTTS_MAX 511
  12316. +#define TFA98XX_SPKR_CALIBRATION_EXTTS_MSK 0x3fe
  12317. +/** @} */
  12318. +
  12319. +/** \addtogroup 10
  12320. + * @{
  12321. + */
  12322. +/*!
  12323. +
  12324. +*/
  12325. +#define TFA98XX_SPKR_CALIBRATION_10 (0x1<<10)
  12326. +#define TFA98XX_SPKR_CALIBRATION_10_POS 10
  12327. +#define TFA98XX_SPKR_CALIBRATION_10_LEN 1
  12328. +#define TFA98XX_SPKR_CALIBRATION_10_MAX 1
  12329. +#define TFA98XX_SPKR_CALIBRATION_10_MSK 0x400
  12330. +/** @} */
  12331. +
  12332. +/** \addtogroup DCSYN
  12333. + * @{
  12334. + */
  12335. +/*!
  12336. + DCDC synchronisation off + 7 positions
  12337. + * - 0 = off + 7 positions
  12338. + * - 1 = off
  12339. + * - 2 = on min
  12340. + * - 3 = on, 3
  12341. + * - 4 = on, 4
  12342. + * - 5 = on, 5
  12343. + * - 6 = on, 6
  12344. + * - 7 = on, max
  12345. +*/
  12346. +#define TFA98XX_SPKR_CALIBRATION_DCSYN (0x7<<11)
  12347. +#define TFA98XX_SPKR_CALIBRATION_DCSYN_POS 11
  12348. +#define TFA98XX_SPKR_CALIBRATION_DCSYN_LEN 3
  12349. +#define TFA98XX_SPKR_CALIBRATION_DCSYN_MAX 7
  12350. +#define TFA98XX_SPKR_CALIBRATION_DCSYN_MSK 0x3800
  12351. +/** @} */
  12352. +
  12353. +
  12354. +/** sys_ctrl Register ($09) ********************************************/
  12355. +
  12356. +/** \addtogroup _0x09_sys_ctrl
  12357. + * @{
  12358. + */
  12359. +#define TFA98XX_SYS_CTRL 0x09
  12360. +/** \addtogroup PWDN
  12361. + * @{
  12362. + */
  12363. +/*!
  12364. + Device Mode
  12365. + * - 0 = Device is set in operating mode
  12366. + * - 1 = Device is set in Powerdown mode [default]
  12367. +*/
  12368. +#define TFA98XX_SYS_CTRL_PWDN (0x1<<0)
  12369. +#define TFA98XX_SYS_CTRL_PWDN_POS 0
  12370. +#define TFA98XX_SYS_CTRL_PWDN_LEN 1
  12371. +#define TFA98XX_SYS_CTRL_PWDN_MAX 1
  12372. +#define TFA98XX_SYS_CTRL_PWDN_MSK 0x1
  12373. +/** @} */
  12374. +
  12375. +/** \addtogroup I2CR
  12376. + * @{
  12377. + */
  12378. +/*!
  12379. + I2C Reset
  12380. + * - 0 = Normal operation [default]
  12381. + * - 1 = Reset all register to default
  12382. +*/
  12383. +#define TFA98XX_SYS_CTRL_I2CR (0x1<<1)
  12384. +#define TFA98XX_SYS_CTRL_I2CR_POS 1
  12385. +#define TFA98XX_SYS_CTRL_I2CR_LEN 1
  12386. +#define TFA98XX_SYS_CTRL_I2CR_MAX 1
  12387. +#define TFA98XX_SYS_CTRL_I2CR_MSK 0x2
  12388. +/** @} */
  12389. +
  12390. +/** \addtogroup CFE
  12391. + * @{
  12392. + */
  12393. +/*!
  12394. + Enable CoolFlux
  12395. + * - 0 = Coolflux OFF
  12396. + * - 1 = Coolflux ON [default]
  12397. +*/
  12398. +#define TFA98XX_SYS_CTRL_CFE (0x1<<2)
  12399. +#define TFA98XX_SYS_CTRL_CFE_POS 2
  12400. +#define TFA98XX_SYS_CTRL_CFE_LEN 1
  12401. +#define TFA98XX_SYS_CTRL_CFE_MAX 1
  12402. +#define TFA98XX_SYS_CTRL_CFE_MSK 0x4
  12403. +/** @} */
  12404. +
  12405. +/** \addtogroup AMPE
  12406. + * @{
  12407. + */
  12408. +/*!
  12409. + Enable Amplifier
  12410. + * - 0 = Amplifier OFF
  12411. + * - 1 = Amplifier ON [default]
  12412. +*/
  12413. +#define TFA98XX_SYS_CTRL_AMPE (0x1<<3)
  12414. +#define TFA98XX_SYS_CTRL_AMPE_POS 3
  12415. +#define TFA98XX_SYS_CTRL_AMPE_LEN 1
  12416. +#define TFA98XX_SYS_CTRL_AMPE_MAX 1
  12417. +#define TFA98XX_SYS_CTRL_AMPE_MSK 0x8
  12418. +/** @} */
  12419. +
  12420. +/** \addtogroup DCA
  12421. + * @{
  12422. + */
  12423. +/*!
  12424. + EnableBoost
  12425. + * - 0 = Boost OFF (Follower mode) [default]
  12426. + * - 1 = Boost ON
  12427. +*/
  12428. +#define TFA98XX_SYS_CTRL_DCA (0x1<<4)
  12429. +#define TFA98XX_SYS_CTRL_DCA_POS 4
  12430. +#define TFA98XX_SYS_CTRL_DCA_LEN 1
  12431. +#define TFA98XX_SYS_CTRL_DCA_MAX 1
  12432. +#define TFA98XX_SYS_CTRL_DCA_MSK 0x10
  12433. +/** @} */
  12434. +
  12435. +/** \addtogroup SBSL
  12436. + * @{
  12437. + */
  12438. +/*!
  12439. + Coolflux configured
  12440. + * - 0 = coolflux not configured [default]
  12441. + * - 1 = coolflux configured
  12442. +*/
  12443. +#define TFA98XX_SYS_CTRL_SBSL (0x1<<5)
  12444. +#define TFA98XX_SYS_CTRL_SBSL_POS 5
  12445. +#define TFA98XX_SYS_CTRL_SBSL_LEN 1
  12446. +#define TFA98XX_SYS_CTRL_SBSL_MAX 1
  12447. +#define TFA98XX_SYS_CTRL_SBSL_MSK 0x20
  12448. +/** @} */
  12449. +
  12450. +/** \addtogroup AMPC
  12451. + * @{
  12452. + */
  12453. +/*!
  12454. + Selection on how Amplifier is enabled
  12455. + * - 0 = Enable amplifier independent of CoolFlux [default]
  12456. + * - 1 = CoolFlux enables amplifier (SW_Bit: cf_enbl_amplifier)
  12457. +*/
  12458. +#define TFA98XX_SYS_CTRL_AMPC (0x1<<6)
  12459. +#define TFA98XX_SYS_CTRL_AMPC_POS 6
  12460. +#define TFA98XX_SYS_CTRL_AMPC_LEN 1
  12461. +#define TFA98XX_SYS_CTRL_AMPC_MAX 1
  12462. +#define TFA98XX_SYS_CTRL_AMPC_MSK 0x40
  12463. +/** @} */
  12464. +
  12465. +/** \addtogroup DCDIS
  12466. + * @{
  12467. + */
  12468. +/*!
  12469. + DCDC not connected
  12470. + * - 0 = normal DCDC functionality [default]
  12471. + * - 1 = DCDC switched off
  12472. +*/
  12473. +#define TFA98XX_SYS_CTRL_DCDIS (0x1<<7)
  12474. +#define TFA98XX_SYS_CTRL_DCDIS_POS 7
  12475. +#define TFA98XX_SYS_CTRL_DCDIS_LEN 1
  12476. +#define TFA98XX_SYS_CTRL_DCDIS_MAX 1
  12477. +#define TFA98XX_SYS_CTRL_DCDIS_MSK 0x80
  12478. +/** @} */
  12479. +
  12480. +/** \addtogroup PSDR
  12481. + * @{
  12482. + */
  12483. +/*!
  12484. + IDDQ test amplifier
  12485. + * - 0 = amplifier is normal mode [default]
  12486. + * - 1 = amplifier is in the test mode
  12487. +*/
  12488. +#define TFA98XX_SYS_CTRL_PSDR (0x1<<8)
  12489. +#define TFA98XX_SYS_CTRL_PSDR_POS 8
  12490. +#define TFA98XX_SYS_CTRL_PSDR_LEN 1
  12491. +#define TFA98XX_SYS_CTRL_PSDR_MAX 1
  12492. +#define TFA98XX_SYS_CTRL_PSDR_MSK 0x100
  12493. +/** @} */
  12494. +
  12495. +/** \addtogroup DCCV
  12496. + * @{
  12497. + */
  12498. +/*!
  12499. + Coil Value
  12500. + * - 0 = 0.7 uH
  12501. + * - 1 = 1.0 uH [new default]
  12502. + * - 2 = 1.5 uH [device default]
  12503. + * - 3 = 2.2 uH
  12504. +*/
  12505. +#define TFA98XX_SYS_CTRL_DCCV (0x3<<9)
  12506. +#define TFA98XX_SYS_CTRL_DCCV_POS 9
  12507. +#define TFA98XX_SYS_CTRL_DCCV_LEN 2
  12508. +#define TFA98XX_SYS_CTRL_DCCV_MAX 3
  12509. +#define TFA98XX_SYS_CTRL_DCCV_MSK 0x600
  12510. +/** @} */
  12511. +
  12512. +/** \addtogroup ISEL
  12513. + * @{
  12514. + */
  12515. +/*!
  12516. + selection input 1 or 2
  12517. + * 0 = input 1 [default]
  12518. + * 1 = input 2
  12519. +*/
  12520. +#define TFA98XX_SYS_CTRL_ISEL (0x1<<13)
  12521. +#define TFA98XX_SYS_CTRL_ISEL_POS 13
  12522. +#define TFA98XX_SYS_CTRL_ISEL_LEN 1
  12523. +#define TFA98XX_SYS_CTRL_ISEL_MAX 1
  12524. +#define TFA98XX_SYS_CTRL_ISEL_MSK 0x2000
  12525. +/** @} */
  12526. +
  12527. +/** \addtogroup INTPAD
  12528. + * @{
  12529. + */
  12530. +/*!
  12531. + INT pad configuration control
  12532. + * - 00 = INT is active low driven all the time
  12533. + * - 01 = INT is active high driven all the time
  12534. + * - 10 = INT pad in pull up mode, driven 0 only when interrupt is raised
  12535. + * - 11 = INT pad in pull down mode, driven 1 only when interrupt is raised
  12536. +*/
  12537. +#define TFA9897_SYS_CTRL_INTPAD (0x3<<12)
  12538. +#define TFA9897_SYS_CTRL_INTPAD_POS 12
  12539. +#define TFA9897_SYS_CTRL_INTPAD_LEN 2
  12540. +#define TFA9897_SYS_CTRL_INTPAD_MAX 3
  12541. +#define TFA9897_SYS_CTRL_INTPAD_MSK 0x3000
  12542. +/** @} */
  12543. +
  12544. +/** \addtogroup IPLL
  12545. + * @{
  12546. + */
  12547. +/*!
  12548. + PLL input refrence clock selection
  12549. + * - 0 = Bit clock BCK [default]
  12550. + * - 1 = Frame Sync FS
  12551. +*/
  12552. +#define TFA98XX_SYS_CTRL_IPLL (0x1<<14)
  12553. +#define TFA98XX_SYS_CTRL_IPLL_POS 14
  12554. +#define TFA98XX_SYS_CTRL_IPLL_LEN 1
  12555. +#define TFA98XX_SYS_CTRL_IPLL_MAX 1
  12556. +#define TFA98XX_SYS_CTRL_IPLL_MSK 0x4000
  12557. +/** @} */
  12558. +
  12559. +/** \addtogroup CFCLK
  12560. + * @{
  12561. + */
  12562. +/*!
  12563. + Coolflux sub-system clock
  12564. + * - 0 = clk_e selected for CF sub-system
  12565. + * - 1 = I2C clock SCL selected for CF sub-system
  12566. +*/
  12567. +#define TFA98XX_SYS_CTRL_CFCLK (0x1<<15)
  12568. +#define TFA98XX_SYS_CTRL_CFCLK_POS 15
  12569. +#define TFA98XX_SYS_CTRL_CFCLK_LEN 1
  12570. +#define TFA98XX_SYS_CTRL_CFCLK_MAX 1
  12571. +#define TFA98XX_SYS_CTRL_CFCLK_MSK 0x8000
  12572. +/** @} */
  12573. +
  12574. +/** @} */
  12575. +
  12576. +/** sys_ctrl Register ($09) ********************************************/
  12577. +
  12578. +/** \addtogroup _0x09_sys_ctrl
  12579. + * @{
  12580. + */
  12581. +#define TFA98XX_SYS_CTRL 0x09
  12582. +/** \addtogroup ISEL
  12583. + * @{
  12584. + */
  12585. +/*!
  12586. + selection input 1 or 2
  12587. + * - 0 = input 1 [default]
  12588. + * - 1 = input 2
  12589. +*/
  12590. +#define TFA9890_SYS_CTRL_ISEL (0x1<<13)
  12591. +#define TFA9890_SYS_CTRL_ISEL_POS 13
  12592. +#define TFA9890_SYS_CTRL_ISEL_LEN 1
  12593. +#define TFA9890_SYS_CTRL_ISEL_MAX 1
  12594. +#define TFA9890_SYS_CTRL_ISEL_MSK 0x2000
  12595. +/** @} */
  12596. +
  12597. +/** @} */
  12598. +
  12599. +/** I2S_sel_reg Register ($0a) ********************************************/
  12600. +
  12601. +/** \addtogroup _0x0a_I2S_sel_reg
  12602. + * @{
  12603. + */
  12604. +#define TFA98XX_I2S_SEL_REG 0x0a
  12605. +#define TFA9890_I2S_SEL_REG_POR 0x3ec3
  12606. +/** \addtogroup DOLS
  12607. + * @{
  12608. + */
  12609. +/*!
  12610. + Output selection dataout left channel
  12611. + * - 0=CurrentSense signal
  12612. + * - 1=Coolflux output 3 (e.g. gain)
  12613. + * - 2=Coolflux output 2 (second channel)
  12614. + * - 3=Coolflux output 1 (main channel) [default]
  12615. + * - 4=datai3 left
  12616. + * - 5=datai3 right
  12617. + * - 6= dcdc feedforward audio current
  12618. +*/
  12619. +#define TFA98XX_I2S_SEL_REG_DOLS (0x7<<0)
  12620. +#define TFA98XX_I2S_SEL_REG_DOLS_POS 0
  12621. +#define TFA98XX_I2S_SEL_REG_DOLS_LEN 3
  12622. +#define TFA98XX_I2S_SEL_REG_DOLS_MAX 7
  12623. +#define TFA98XX_I2S_SEL_REG_DOLS_MSK 0x7
  12624. +/** @} */
  12625. +
  12626. +/** \addtogroup DORS
  12627. + * @{
  12628. + */
  12629. +/*!
  12630. + Output selection dataout right channel
  12631. + * - 0=CurrentSense signal [default]
  12632. + * - 1=Coolflux output 3 (e.g. gain)
  12633. + * - 2=Coolflux output 2 (second channel)
  12634. + * - 3=Coolflux output 1 (main channel)
  12635. + * - 4=datai3 left
  12636. + * - 5=datai3 right
  12637. + * - 6= dcdc feedforward audio current
  12638. +*/
  12639. +#define TFA98XX_I2S_SEL_REG_DORS (0x7<<3)
  12640. +#define TFA98XX_I2S_SEL_REG_DORS_POS 3
  12641. +#define TFA98XX_I2S_SEL_REG_DORS_LEN 3
  12642. +#define TFA98XX_I2S_SEL_REG_DORS_MAX 7
  12643. +#define TFA98XX_I2S_SEL_REG_DORS_MSK 0x38
  12644. +/** @} */
  12645. +
  12646. +/** \addtogroup SPKL
  12647. + * @{
  12648. + */
  12649. +/*!
  12650. + Selection speaker induction
  12651. + * - 0 = 22 uH
  12652. + * - 1 = 27 uH
  12653. + * - 2 = 33 uH
  12654. + * - 3 = 39 uH [default]
  12655. + * - 4 = 47 uH
  12656. + * - 5 = 56 uH
  12657. + * - 6 = 68 uH
  12658. + * - 7 = 82 uH
  12659. +*/
  12660. +#define TFA98XX_I2S_SEL_REG_SPKL (0x7<<6)
  12661. +#define TFA98XX_I2S_SEL_REG_SPKL_POS 6
  12662. +#define TFA98XX_I2S_SEL_REG_SPKL_LEN 3
  12663. +#define TFA98XX_I2S_SEL_REG_SPKL_MAX 7
  12664. +#define TFA98XX_I2S_SEL_REG_SPKL_MSK 0x1c0
  12665. +/** @} */
  12666. +
  12667. +/** \addtogroup SPKR
  12668. + * @{
  12669. + */
  12670. +/*!
  12671. + Selection speaker impedance
  12672. + * - 0 = defined by DSP
  12673. + * - 1 = 4 ohm
  12674. + * - 2 = 6 ohm
  12675. + * - 3 = 8 ohm [default]
  12676. +*/
  12677. +#define TFA98XX_I2S_SEL_REG_SPKR (0x3<<9)
  12678. +#define TFA98XX_I2S_SEL_REG_SPKR_POS 9
  12679. +#define TFA98XX_I2S_SEL_REG_SPKR_LEN 2
  12680. +#define TFA98XX_I2S_SEL_REG_SPKR_MAX 3
  12681. +#define TFA98XX_I2S_SEL_REG_SPKR_MSK 0x600
  12682. +/** @} */
  12683. +
  12684. +/** \addtogroup DCFG
  12685. + * @{
  12686. + */
  12687. +/*!
  12688. + DCDC speaker current compensation gain
  12689. + * - 0 = Off [new default]
  12690. + * - 1 = 70%
  12691. + * - 2 = 75%
  12692. + * - 3 = 80%
  12693. + * - 4 = 85%
  12694. + * - 5 = 90%
  12695. + * - 6 = 95%
  12696. + * - 7 = 100% [device default]
  12697. + * - 8 = 105%
  12698. + * - 9 = 110%
  12699. + * - 10 = 115%
  12700. + * - 11 = 120%
  12701. + * - 12 = 125%
  12702. + * - 13 = 130%
  12703. + * - 14 = 135%
  12704. + * - 15 = 140%
  12705. +*/
  12706. +#define TFA98XX_I2S_SEL_REG_DCFG (0xf<<11)
  12707. +#define TFA98XX_I2S_SEL_REG_DCFG_POS 11
  12708. +#define TFA98XX_I2S_SEL_REG_DCFG_LEN 4
  12709. +#define TFA98XX_I2S_SEL_REG_DCFG_MAX 15
  12710. +#define TFA98XX_I2S_SEL_REG_DCFG_MSK 0x7800
  12711. +/** @} */
  12712. +
  12713. +/** \addtogroup 15
  12714. + * @{
  12715. + */
  12716. +/*!
  12717. + DCDC speaker current compensation sign
  12718. + * - 0 = positive [default]
  12719. + * - 1 = negative
  12720. +*/
  12721. +#define TFA98XX_I2S_SEL_REG_15 (0x1<<15)
  12722. +#define TFA98XX_I2S_SEL_REG_15_POS 15
  12723. +#define TFA98XX_I2S_SEL_REG_15_LEN 1
  12724. +#define TFA98XX_I2S_SEL_REG_15_MAX 1
  12725. +#define TFA98XX_I2S_SEL_REG_15_MSK 0x8000
  12726. +/** @} */
  12727. +
  12728. +/** @} */
  12729. +
  12730. +/** mtpkey2_reg Register ($0b) ********************************************/
  12731. +
  12732. +/** \addtogroup _0x0b_mtpkey2_reg
  12733. + * @{
  12734. + */
  12735. +#define TFA98XX_MTPKEY2_REG 0x0b
  12736. +/** \addtogroup MTPK
  12737. + * @{
  12738. + */
  12739. +/*!
  12740. + 5Ah, 90d To access KEY1_Protected registers (=Default for engineering)
  12741. +*/
  12742. +#define TFA98XX_MTPKEY2_REG_MTPK (0xff<<0)
  12743. +#define TFA98XX_MTPKEY2_REG_MTPK_POS 0
  12744. +#define TFA98XX_MTPKEY2_REG_MTPK_LEN 8
  12745. +#define TFA98XX_MTPKEY2_REG_MTPK_MAX 255
  12746. +#define TFA98XX_MTPKEY2_REG_MTPK_MSK 0xff
  12747. +/** @} */
  12748. +
  12749. +/** \addtogroup 8
  12750. + * @{
  12751. + */
  12752. +/*!
  12753. + not used
  12754. +*/
  12755. +#define TFA98XX_MTPKEY2_REG_8 (0xff<<8)
  12756. +#define TFA98XX_MTPKEY2_REG_8_POS 8
  12757. +#define TFA98XX_MTPKEY2_REG_8_LEN 8
  12758. +#define TFA98XX_MTPKEY2_REG_8_MAX 255
  12759. +#define TFA98XX_MTPKEY2_REG_8_MSK 0xff00
  12760. +/** @} */
  12761. +
  12762. +/** @} */
  12763. +
  12764. +/** voltage_sense_config Register ($0c) ********************************************/
  12765. +
  12766. +/** \addtogroup _0x0c_voltage_sense_config
  12767. + * @{
  12768. + */
  12769. +#define TFA98XX_VOLTAGE_SENSE_CONFIG 0x0c
  12770. +/** \addtogroup VSENA
  12771. + * @{
  12772. + */
  12773. +/*!
  12774. + Voltage sense enabling control bit
  12775. + * - 0 = disables the voltage sense measurment
  12776. + * - 1 = enables the voltage sense measurment
  12777. +*/
  12778. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSENA (0x1<<0)
  12779. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSENA_POS 0
  12780. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSENA_LEN 1
  12781. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSENA_MAX 1
  12782. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSENA_MSK 0x1
  12783. +/** @} */
  12784. +
  12785. +/** \addtogroup VSPWM
  12786. + * @{
  12787. + */
  12788. +/*!
  12789. + Voltage sense PWM source selection control
  12790. + * - 0 = PWM signal from coolflux output
  12791. + * - 1 = PWM signal from analog clipper module
  12792. +*/
  12793. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSPWM (0x1<<1)
  12794. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSPWM_POS 1
  12795. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSPWM_LEN 1
  12796. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSPWM_MAX 1
  12797. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_VSPWM_MSK 0x2
  12798. +/** @} */
  12799. +
  12800. +/** \addtogroup 2
  12801. + * @{
  12802. + */
  12803. +/*!
  12804. +
  12805. +*/
  12806. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_2 (0x3fff<<2)
  12807. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_2_POS 2
  12808. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_2_LEN 14
  12809. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_2_MAX 16383
  12810. +#define TFA98XX_VOLTAGE_SENSE_CONFIG_2_MSK 0xfffc
  12811. +/** @} */
  12812. +
  12813. +/** cgu_clock_sync_reg Register ($0c) **/
  12814. +#define TFA98XX_CGU_CLOCK_SYNC_REG 0x0c
  12815. +#define TFA9890_CGU_CLOCK_SYNC_REG_POR 0x8000
  12816. +/* Delay count for clock synchronisation */
  12817. +#define TFA98XX_CGU_CLOCK_SYNC_REG_0 (0x1fff<<0)
  12818. +#define TFA98XX_CGU_CLOCK_SYNC_REG_0_POS 0
  12819. +#define TFA98XX_CGU_CLOCK_SYNC_REG_0_MAX 8191
  12820. +#define TFA98XX_CGU_CLOCK_SYNC_REG_0_MSK 0x1fff
  12821. +/* not used */
  12822. +#define TFA98XX_CGU_CLOCK_SYNC_REG_13 (0x3<<13)
  12823. +#define TFA98XX_CGU_CLOCK_SYNC_REG_13_POS 13
  12824. +#define TFA98XX_CGU_CLOCK_SYNC_REG_13_MAX 3
  12825. +#define TFA98XX_CGU_CLOCK_SYNC_REG_13_MSK 0x6000
  12826. +/* Enable CGU clock synchronisation */
  12827. +#define TFA98XX_CGU_CLOCK_SYNC_REG_15 (0x1<<15)
  12828. +#define TFA98XX_CGU_CLOCK_SYNC_REG_15_POS 15
  12829. +#define TFA98XX_CGU_CLOCK_SYNC_REG_15_MAX 1
  12830. +#define TFA98XX_CGU_CLOCK_SYNC_REG_15_MSK 0x8000
  12831. +
  12832. +/** adc_sync_reg Register ($0d) **/
  12833. +#define TFA98XX_ADC_SYNC_REG 0x0d
  12834. +#define TFA9890_ADC_SYNC_REG_POR 0x8000
  12835. +/* Delay count for ADC synchronisation */
  12836. +#define TFA98XX_ADC_SYNC_REG_0 (0x1fff<<0)
  12837. +#define TFA98XX_ADC_SYNC_REG_0_POS 0
  12838. +#define TFA98XX_ADC_SYNC_REG_0_MAX 8191
  12839. +#define TFA98XX_ADC_SYNC_REG_0_MSK 0x1fff
  12840. +/* not used */
  12841. +#define TFA98XX_ADC_SYNC_REG_13 (0x3<<13)
  12842. +#define TFA98XX_ADC_SYNC_REG_13_POS 13
  12843. +#define TFA98XX_ADC_SYNC_REG_13_MAX 3
  12844. +#define TFA98XX_ADC_SYNC_REG_13_MSK 0x6000
  12845. +/* Enable ADC synchronisation */
  12846. +#define TFA98XX_ADC_SYNC_REG_15 (0x1<<15)
  12847. +#define TFA98XX_ADC_SYNC_REG_15_POS 15
  12848. +#define TFA98XX_ADC_SYNC_REG_15_MAX 1
  12849. +#define TFA98XX_ADC_SYNC_REG_15_MSK 0x8000
  12850. +
  12851. +/** reserved_1 Register ($0e) **/
  12852. +#define TFA98XX_RESERVED_1 0x0e
  12853. +#define TFA9890_RESERVED_1_POR 0x0f01
  12854. +/* to switch off dcdc reduction with bat prot */
  12855. +#define TFA98XX_RESERVED_1_0 (0x1<<0)
  12856. +#define TFA98XX_RESERVED_1_0_POS 0
  12857. +#define TFA98XX_RESERVED_1_0_MAX 1
  12858. +#define TFA98XX_RESERVED_1_0_MSK 0x1
  12859. +/* test option for frinch caps */
  12860. +#define TFA98XX_RESERVED_1_1 (0x1<<1)
  12861. +#define TFA98XX_RESERVED_1_1_POS 1
  12862. +#define TFA98XX_RESERVED_1_1_MAX 1
  12863. +#define TFA98XX_RESERVED_1_1_MSK 0x2
  12864. +/* for extra connections digital to analog */
  12865. +#define TFA98XX_RESERVED_1_2 (0x1f<<2)
  12866. +#define TFA98XX_RESERVED_1_2_POS 2
  12867. +#define TFA98XX_RESERVED_1_2_MAX 31
  12868. +#define TFA98XX_RESERVED_1_2_MSK 0x7c
  12869. +/* icomp dem switch */
  12870. +#define TFA98XX_RESERVED_1_7 (0x1<<7)
  12871. +#define TFA98XX_RESERVED_1_7_POS 7
  12872. +#define TFA98XX_RESERVED_1_7_MAX 1
  12873. +#define TFA98XX_RESERVED_1_7_MSK 0x80
  12874. +/* */
  12875. +#define TFA98XX_RESERVED_1_8 (0xff<<8)
  12876. +#define TFA98XX_RESERVED_1_8_POS 8
  12877. +#define TFA98XX_RESERVED_1_8_MAX 255
  12878. +#define TFA98XX_RESERVED_1_8_MSK 0xff00
  12879. +
  12880. +
  12881. +/** @} */
  12882. +
  12883. +/** interrupt_reg Register ($0f) ********************************************/
  12884. +
  12885. +/** \addtogroup _0x0f_interrupt_reg
  12886. + * @{
  12887. + */
  12888. +#define TFA98XX_INTERRUPT_REG 0x0f
  12889. +/** \addtogroup VDDD
  12890. + * @{
  12891. + */
  12892. +/*!
  12893. + mask flag_por for interupt generation
  12894. + * - 0 = enable interrupt
  12895. + * - 1 = mask interrupt
  12896. +*/
  12897. +#define TFA98XX_INTERRUPT_REG_VDDD (0x1<<0)
  12898. +#define TFA98XX_INTERRUPT_REG_VDDD_POS 0
  12899. +#define TFA98XX_INTERRUPT_REG_VDDD_LEN 1
  12900. +#define TFA98XX_INTERRUPT_REG_VDDD_MAX 1
  12901. +#define TFA98XX_INTERRUPT_REG_VDDD_MSK 0x1
  12902. +/** @} */
  12903. +
  12904. +/** \addtogroup OTDD
  12905. + * @{
  12906. + */
  12907. +/*!
  12908. + mask flag_otpok for interupt generation
  12909. + * - 0 = enable interrupt
  12910. + * - 1 = mask interrupt
  12911. +*/
  12912. +#define TFA98XX_INTERRUPT_REG_OTDD (0x1<<1)
  12913. +#define TFA98XX_INTERRUPT_REG_OTDD_POS 1
  12914. +#define TFA98XX_INTERRUPT_REG_OTDD_LEN 1
  12915. +#define TFA98XX_INTERRUPT_REG_OTDD_MAX 1
  12916. +#define TFA98XX_INTERRUPT_REG_OTDD_MSK 0x2
  12917. +/** @} */
  12918. +
  12919. +/** \addtogroup OVDD
  12920. + * @{
  12921. + */
  12922. +/*!
  12923. + mask flag_ovpok for interupt generation
  12924. + * - 0 = enable interrupt
  12925. + * - 1 = mask interrupt
  12926. +*/
  12927. +#define TFA9890_INTERRUPT_REG_OVDD (0x1<<2)
  12928. +#define TFA9890_INTERRUPT_REG_OVDD_POS 2
  12929. +#define TFA9890_INTERRUPT_REG_OVDD_LEN 1
  12930. +#define TFA9890_INTERRUPT_REG_OVDD_MAX 1
  12931. +#define TFA9890_INTERRUPT_REG_OVDD_MSK 0x4
  12932. +/** @} */
  12933. +
  12934. +/** \addtogroup UVDD
  12935. + * @{
  12936. + */
  12937. +/*!
  12938. + mask flag_uvpok for interupt generation
  12939. + * - 0 = enable interrupt
  12940. + * - 1 = mask interrupt
  12941. +*/
  12942. +#define TFA9890_INTERRUPT_REG_UVDD (0x1<<3)
  12943. +#define TFA9890_INTERRUPT_REG_UVDD_POS 3
  12944. +#define TFA9890_INTERRUPT_REG_UVDD_LEN 1
  12945. +#define TFA9890_INTERRUPT_REG_UVDD_MAX 1
  12946. +#define TFA9890_INTERRUPT_REG_UVDD_MSK 0x8
  12947. +/** @} */
  12948. +
  12949. +/** \addtogroup OCDD
  12950. + * @{
  12951. + */
  12952. +/*!
  12953. + mask flag_ocp_alarm for interupt generation
  12954. + * - 0 = enable interrupt
  12955. + * - 1 = mask interrupt
  12956. +*/
  12957. +#define TFA9890_INTERRUPT_REG_OCDD (0x1<<4)
  12958. +#define TFA9890_INTERRUPT_REG_OCDD_POS 4
  12959. +#define TFA9890_INTERRUPT_REG_OCDD_LEN 1
  12960. +#define TFA9890_INTERRUPT_REG_OCDD_MAX 1
  12961. +#define TFA9890_INTERRUPT_REG_OCDD_MSK 0x10
  12962. +/** @} */
  12963. +
  12964. +/** \addtogroup CLKD
  12965. + * @{
  12966. + */
  12967. +/*!
  12968. + mask flag_clocks_stable for interupt generation
  12969. + * - 0 = enable interrupt
  12970. + * - 1 = mask interrupt
  12971. +*/
  12972. +#define TFA9890_INTERRUPT_REG_CLKD (0x1<<5)
  12973. +#define TFA9890_INTERRUPT_REG_CLKD_POS 5
  12974. +#define TFA9890_INTERRUPT_REG_CLKD_LEN 1
  12975. +#define TFA9890_INTERRUPT_REG_CLKD_MAX 1
  12976. +#define TFA9890_INTERRUPT_REG_CLKD_MSK 0x20
  12977. +/** @} */
  12978. +
  12979. +/** \addtogroup DCCD
  12980. + * @{
  12981. + */
  12982. +/*!
  12983. + mask flag_pwrokbst for interupt generation
  12984. + * - 0 = enable interrupt
  12985. + * - 1 = mask interrupt
  12986. +*/
  12987. +#define TFA9890_INTERRUPT_REG_DCCD (0x1<<6)
  12988. +#define TFA9890_INTERRUPT_REG_DCCD_POS 6
  12989. +#define TFA9890_INTERRUPT_REG_DCCD_LEN 1
  12990. +#define TFA9890_INTERRUPT_REG_DCCD_MAX 1
  12991. +#define TFA9890_INTERRUPT_REG_DCCD_MSK 0x40
  12992. +/** @} */
  12993. +
  12994. +/** \addtogroup SPKD
  12995. + * @{
  12996. + */
  12997. +/*!
  12998. + mask flag_cf_speakererror for interupt generation
  12999. + * - 0 = enable interrupt
  13000. + * - 1 = mask interrupt
  13001. +*/
  13002. +#define TFA9890_INTERRUPT_REG_SPKD (0x1<<7)
  13003. +#define TFA9890_INTERRUPT_REG_SPKD_POS 7
  13004. +#define TFA9890_INTERRUPT_REG_SPKD_LEN 1
  13005. +#define TFA9890_INTERRUPT_REG_SPKD_MAX 1
  13006. +#define TFA9890_INTERRUPT_REG_SPKD_MSK 0x80
  13007. +/** @} */
  13008. +
  13009. +/** \addtogroup WDD
  13010. + * @{
  13011. + */
  13012. +/*!
  13013. + mask flag_watchdog_reset for interupt generation
  13014. + * - 0 = enable interrupt
  13015. + * - 1 = mask interrupt
  13016. +*/
  13017. +#define TFA9890_INTERRUPT_REG_WDD (0x1<<8)
  13018. +#define TFA9890_INTERRUPT_REG_WDD_POS 8
  13019. +#define TFA9890_INTERRUPT_REG_WDD_LEN 1
  13020. +#define TFA9890_INTERRUPT_REG_WDD_MAX 1
  13021. +#define TFA9890_INTERRUPT_REG_WDD_MSK 0x100
  13022. +/** @} */
  13023. +
  13024. +/** \addtogroup LCLK
  13025. + * @{
  13026. + */
  13027. +/*!
  13028. + mask flag_lost_clk for interupt generation
  13029. + * - 0 = enable interrupt
  13030. + * - 1 = mask interrupt
  13031. +*/
  13032. +#define TFA9890_INTERRUPT_REG_LCLK (0x1<<9)
  13033. +#define TFA9890_INTERRUPT_REG_LCLK_POS 9
  13034. +#define TFA9890_INTERRUPT_REG_LCLK_LEN 1
  13035. +#define TFA9890_INTERRUPT_REG_LCLK_MAX 1
  13036. +#define TFA9890_INTERRUPT_REG_LCLK_MSK 0x200
  13037. +/** @} */
  13038. +
  13039. +/** \addtogroup 10
  13040. + * @{
  13041. + */
  13042. +/*!
  13043. + Reserved
  13044. +*/
  13045. +#define TFA9890_INTERRUPT_REG_10 (0xf<<10)
  13046. +#define TFA9890_INTERRUPT_REG_10_POS 10
  13047. +#define TFA9890_INTERRUPT_REG_10_LEN 4
  13048. +#define TFA9890_INTERRUPT_REG_10_MAX 15
  13049. +#define TFA9890_INTERRUPT_REG_10_MSK 0x3c00
  13050. +/** @} */
  13051. +
  13052. +/** \addtogroup INT
  13053. + * @{
  13054. + */
  13055. +/*!
  13056. + enabling interrupt
  13057. + * - 0 = interrupt disabled
  13058. + * - 1 = interrupt enabled
  13059. +*/
  13060. +#define TFA9890_INTERRUPT_REG_INT (0x1<<14)
  13061. +#define TFA9890_INTERRUPT_REG_INT_POS 14
  13062. +#define TFA9890_INTERRUPT_REG_INT_LEN 1
  13063. +#define TFA9890_INTERRUPT_REG_INT_MAX 1
  13064. +#define TFA9890_INTERRUPT_REG_INT_MSK 0x4000
  13065. +/** @} */
  13066. +
  13067. +/** \addtogroup INTP
  13068. + * @{
  13069. + */
  13070. +/*!
  13071. + Setting polarity interupt
  13072. + * - 0 = interrupt active low
  13073. + * - 1 = interrupt active high
  13074. +*/
  13075. +#define TFA9890_INTERRUPT_REG_INTP (0x1<<15)
  13076. +#define TFA9890_INTERRUPT_REG_INTP_POS 15
  13077. +#define TFA9890_INTERRUPT_REG_INTP_LEN 1
  13078. +#define TFA9890_INTERRUPT_REG_INTP_MAX 1
  13079. +#define TFA9890_INTERRUPT_REG_INTP_MSK 0x8000
  13080. +/** @} */
  13081. +
  13082. +/** @} */
  13083. +
  13084. +/** pwm_mute_set Register ($41) ********************************************/
  13085. +
  13086. +/** \addtogroup _0x41_pwm_mute_set_TFA9887
  13087. + * @{
  13088. + */
  13089. +#define TFA9887_PWM_MUTE_SET 0x41
  13090. +/** \addtogroup 0
  13091. + * @{
  13092. + */
  13093. +/*!
  13094. + bypass_hp, to bypass the hp filter byhind the CoolFlux
  13095. +*/
  13096. +#define TFA9887_PWM_MUTE_SET_0 (0x1<<0)
  13097. +#define TFA9887_PWM_MUTE_SET_0_POS 0
  13098. +#define TFA9887_PWM_MUTE_SET_0_LEN 1
  13099. +#define TFA9887_PWM_MUTE_SET_0_MAX 1
  13100. +#define TFA9887_PWM_MUTE_SET_0_MSK 0x1
  13101. +/** @} */
  13102. +
  13103. +/** \addtogroup 1
  13104. + * @{
  13105. + */
  13106. +/*!
  13107. + hard mute setting in HW
  13108. + * - 0=no mute
  13109. + * - 1=hard-muted
  13110. +*/
  13111. +#define TFA9887_PWM_MUTE_SET_1 (0x1<<1)
  13112. +#define TFA9887_PWM_MUTE_SET_1_POS 1
  13113. +#define TFA9887_PWM_MUTE_SET_1_LEN 1
  13114. +#define TFA9887_PWM_MUTE_SET_1_MAX 1
  13115. +#define TFA9887_PWM_MUTE_SET_1_MSK 0x2
  13116. +/** @} */
  13117. +
  13118. +/** \addtogroup 2
  13119. + * @{
  13120. + */
  13121. +/*!
  13122. + Soft mute setting in HW
  13123. + * - 0=no mute
  13124. + * - 1=soft-muted
  13125. +*/
  13126. +#define TFA9887_PWM_MUTE_SET_2 (0x1<<2)
  13127. +#define TFA9887_PWM_MUTE_SET_2_POS 2
  13128. +#define TFA9887_PWM_MUTE_SET_2_LEN 1
  13129. +#define TFA9887_PWM_MUTE_SET_2_MAX 1
  13130. +#define TFA9887_PWM_MUTE_SET_2_MSK 0x4
  13131. +/** @} */
  13132. +
  13133. +/** \addtogroup PWMDEL
  13134. + * @{
  13135. + */
  13136. +/*!
  13137. + PWM DelayBits to set the delay
  13138. +*/
  13139. +#define TFA9887_PWM_MUTE_SET_PWMDEL (0x1f<<3)
  13140. +#define TFA9887_PWM_MUTE_SET_PWMDEL_POS 3
  13141. +#define TFA9887_PWM_MUTE_SET_PWMDEL_LEN 5
  13142. +#define TFA9887_PWM_MUTE_SET_PWMDEL_MAX 31
  13143. +#define TFA9887_PWM_MUTE_SET_PWMDEL_MSK 0xf8
  13144. +/** @} */
  13145. +
  13146. +/** \addtogroup PWMSH
  13147. + * @{
  13148. + */
  13149. +/*!
  13150. + PWM Shape
  13151. + * - 0=Single sided
  13152. + * - 1=Double sided
  13153. +*/
  13154. +#define TFA9887_PWM_MUTE_SET_PWMSH (0x1<<8)
  13155. +#define TFA9887_PWM_MUTE_SET_PWMSH_POS 8
  13156. +#define TFA9887_PWM_MUTE_SET_PWMSH_LEN 1
  13157. +#define TFA9887_PWM_MUTE_SET_PWMSH_MAX 1
  13158. +#define TFA9887_PWM_MUTE_SET_PWMSH_MSK 0x100
  13159. +/** @} */
  13160. +
  13161. +/** \addtogroup PWMRE
  13162. + * @{
  13163. + */
  13164. +/*!
  13165. + PWM Bitlength in noise shaper
  13166. + * - 0=7 bits
  13167. + * - 1=8 bits
  13168. +*/
  13169. +#define TFA9887_PWM_MUTE_SET_PWMRE (0x1<<9)
  13170. +#define TFA9887_PWM_MUTE_SET_PWMRE_POS 9
  13171. +#define TFA9887_PWM_MUTE_SET_PWMRE_LEN 1
  13172. +#define TFA9887_PWM_MUTE_SET_PWMRE_MAX 1
  13173. +#define TFA9887_PWM_MUTE_SET_PWMRE_MSK 0x200
  13174. +/** @} */
  13175. +
  13176. +/** @} */
  13177. +
  13178. +/** currentsense3 Register ($48) ********************************************/
  13179. +
  13180. +/** \addtogroup _0x48_currentsense3_TFA9887
  13181. + * @{
  13182. + */
  13183. +#define TFA9887_CURRENTSENSE3 0x48
  13184. +/** \addtogroup 0
  13185. + * @{
  13186. + */
  13187. +/*!
  13188. +
  13189. +*/
  13190. +#define TFA9887_CURRENTSENSE3_0 (0x1<<0)
  13191. +#define TFA9887_CURRENTSENSE3_0_POS 0
  13192. +#define TFA9887_CURRENTSENSE3_0_LEN 1
  13193. +#define TFA9887_CURRENTSENSE3_0_MAX 1
  13194. +#define TFA9887_CURRENTSENSE3_0_MSK 0x1
  13195. +/** @} */
  13196. +
  13197. +/** \addtogroup 1
  13198. + * @{
  13199. + */
  13200. +/*!
  13201. +
  13202. +*/
  13203. +#define TFA9887_CURRENTSENSE3_1 (0x1<<1)
  13204. +#define TFA9887_CURRENTSENSE3_1_POS 1
  13205. +#define TFA9887_CURRENTSENSE3_1_LEN 1
  13206. +#define TFA9887_CURRENTSENSE3_1_MAX 1
  13207. +#define TFA9887_CURRENTSENSE3_1_MSK 0x2
  13208. +/** @} */
  13209. +
  13210. +/** \addtogroup 2
  13211. + * @{
  13212. + */
  13213. +/*!
  13214. + HIGH => Prevent dcdc switching during clk_cs_clksh
  13215. + * - LOW => Allow switch of dcdc during clk_cs_clksh
  13216. +*/
  13217. +#define TFA9887_CURRENTSENSE3_2 (0x1<<2)
  13218. +#define TFA9887_CURRENTSENSE3_2_POS 2
  13219. +#define TFA9887_CURRENTSENSE3_2_LEN 1
  13220. +#define TFA9887_CURRENTSENSE3_2_MAX 1
  13221. +#define TFA9887_CURRENTSENSE3_2_MSK 0x4
  13222. +/** @} */
  13223. +
  13224. +/** \addtogroup 7
  13225. + * @{
  13226. + */
  13227. +/*!
  13228. + delayshiftse2
  13229. +*/
  13230. +#define TFA9887_CURRENTSENSE3_7 (0x7f<<7)
  13231. +#define TFA9887_CURRENTSENSE3_7_POS 7
  13232. +#define TFA9887_CURRENTSENSE3_7_LEN 7
  13233. +#define TFA9887_CURRENTSENSE3_7_MAX 127
  13234. +#define TFA9887_CURRENTSENSE3_7_MSK 0x3f80
  13235. +/** @} */
  13236. +
  13237. +/** \addtogroup TCC
  13238. + * @{
  13239. + */
  13240. +/*!
  13241. + sample & hold track time:
  13242. + * - 00 = 2 clock cycles
  13243. + * - 01 = 4 clock cycles
  13244. + * - 10 = 8 clock cycles
  13245. + * - 11 = is no fixed time, but as N1B
  13246. +*/
  13247. +#define TFA9887_CURRENTSENSE3_TCC (0x1f<<1)
  13248. +#define TFA9887_CURRENTSENSE3_TCC_POS 1
  13249. +#define TFA9887_CURRENTSENSE3_TCC_LEN 5
  13250. +#define TFA9887_CURRENTSENSE3_TCC_MAX 31
  13251. +#define TFA9887_CURRENTSENSE3_TCC_MSK 0x3e
  13252. +/** @} */
  13253. +
  13254. +/** @} */
  13255. +
  13256. +/** CurrentSense4 Register ($49) ********************************************/
  13257. +
  13258. +/** \addtogroup _0x49_CurrentSense4
  13259. + * @{
  13260. + */
  13261. +#define TFA98XX_CURRENTSENSE4 0x49
  13262. +/** \addtogroup CLIP
  13263. + * @{
  13264. + */
  13265. +/*!
  13266. + Bypass clip control
  13267. + * - 0 = clip control enabled
  13268. + * - 1 = clip control bypassed
  13269. +*/
  13270. +#define TFA989X_CURRENTSENSE4_CLIP (0x1<<0)
  13271. +#define TFA989X_CURRENTSENSE4_CLIP_POS 0
  13272. +#define TFA989X_CURRENTSENSE4_CLIP_LEN 1
  13273. +#define TFA989X_CURRENTSENSE4_CLIP_MAX 1
  13274. +#define TFA989X_CURRENTSENSE4_CLIP_MSK 0x1
  13275. +/** @} */
  13276. +
  13277. +/** \addtogroup 1
  13278. + * @{
  13279. + */
  13280. +/*!
  13281. +
  13282. +*/
  13283. +#define TFA98XX_CURRENTSENSE4_1 (0x1<<1)
  13284. +#define TFA98XX_CURRENTSENSE4_1_POS 1
  13285. +#define TFA98XX_CURRENTSENSE4_1_LEN 1
  13286. +#define TFA98XX_CURRENTSENSE4_1_MAX 1
  13287. +#define TFA98XX_CURRENTSENSE4_1_MSK 0x2
  13288. +/** @} */
  13289. +
  13290. +/** \addtogroup 2
  13291. + * @{
  13292. + */
  13293. +/*!
  13294. + to disable clock gating in the coolflux
  13295. +*/
  13296. +#define TFA9897_CURRENTSENSE4_2 (0x1<<2)
  13297. +#define TFA9897_CURRENTSENSE4_2_POS 2
  13298. +#define TFA9897_CURRENTSENSE4_2_LEN 1
  13299. +#define TFA9897_CURRENTSENSE4_2_MAX 1
  13300. +#define TFA9897_CURRENTSENSE4_2_MSK 0x4
  13301. +/** @} */
  13302. +
  13303. +/** \addtogroup 3
  13304. + * @{
  13305. + */
  13306. +/*!
  13307. +
  13308. +*/
  13309. +#define TFA98XX_CURRENTSENSE4_3 (0x1<<3)
  13310. +#define TFA98XX_CURRENTSENSE4_3_POS 3
  13311. +#define TFA98XX_CURRENTSENSE4_3_LEN 1
  13312. +#define TFA98XX_CURRENTSENSE4_3_MAX 1
  13313. +#define TFA98XX_CURRENTSENSE4_3_MSK 0x8
  13314. +/** @} */
  13315. +
  13316. +/** \addtogroup 4
  13317. + * @{
  13318. + */
  13319. +/*!
  13320. + clock switch for battery protection clipper, it switches back to old frequency
  13321. +*/
  13322. +#define TFA9897_CURRENTSENSE4_4 (0x1<<4)
  13323. +#define TFA9897_CURRENTSENSE4_4_POS 4
  13324. +#define TFA9897_CURRENTSENSE4_4_LEN 1
  13325. +#define TFA9897_CURRENTSENSE4_4_MAX 1
  13326. +#define TFA9897_CURRENTSENSE4_4_MSK 0x10
  13327. +/** @} */
  13328. +
  13329. +/** \addtogroup 5
  13330. + * @{
  13331. + */
  13332. +/*!
  13333. + 8 ohm mode for current sense (gain mode)
  13334. + * - 0 = 4 ohm (default)
  13335. + * - 1 = 8 ohm
  13336. +*/
  13337. +#define TFA9897_CURRENTSENSE4_5 (0x1<<5)
  13338. +#define TFA9897_CURRENTSENSE4_5_POS 5
  13339. +#define TFA9897_CURRENTSENSE4_5_LEN 1
  13340. +#define TFA9897_CURRENTSENSE4_5_MAX 1
  13341. +#define TFA9897_CURRENTSENSE4_5_MSK 0x20
  13342. +/** @} */
  13343. +
  13344. +/** \addtogroup 6
  13345. + * @{
  13346. + */
  13347. +/*!
  13348. +
  13349. +*/
  13350. +#define TFA98XX_CURRENTSENSE4_6 (0x1<<6)
  13351. +#define TFA98XX_CURRENTSENSE4_6_POS 6
  13352. +#define TFA98XX_CURRENTSENSE4_6_LEN 1
  13353. +#define TFA98XX_CURRENTSENSE4_6_MAX 1
  13354. +#define TFA98XX_CURRENTSENSE4_6_MSK 0x40
  13355. +/** @} */
  13356. +
  13357. +/** \addtogroup 7
  13358. + * @{
  13359. + */
  13360. +/*!
  13361. + delay_sh, tunes S7H delay
  13362. +*/
  13363. +#define TFA9897_CURRENTSENSE4_7 (0x1f<<7)
  13364. +#define TFA9897_CURRENTSENSE4_7_POS 7
  13365. +#define TFA9897_CURRENTSENSE4_7_LEN 5
  13366. +#define TFA9897_CURRENTSENSE4_7_MAX 31
  13367. +#define TFA9897_CURRENTSENSE4_7_MSK 0xf80
  13368. +/** @} */
  13369. +
  13370. +/** \addtogroup 12
  13371. + * @{
  13372. + */
  13373. +/*!
  13374. + Invert the sample/hold clock for current sense ADC
  13375. +*/
  13376. +#define TFA9897_CURRENTSENSE4_12 (0x1<<12)
  13377. +#define TFA9897_CURRENTSENSE4_12_POS 12
  13378. +#define TFA9897_CURRENTSENSE4_12_LEN 1
  13379. +#define TFA9897_CURRENTSENSE4_12_MAX 1
  13380. +#define TFA9897_CURRENTSENSE4_12_MSK 0x1000
  13381. +/** @} */
  13382. +
  13383. +/** \addtogroup 13
  13384. + * @{
  13385. + */
  13386. +/*!
  13387. + Invert neg signal
  13388. +*/
  13389. +#define TFA9897_CURRENTSENSE4_13 (0x1<<13)
  13390. +#define TFA9897_CURRENTSENSE4_13_POS 13
  13391. +#define TFA9897_CURRENTSENSE4_13_LEN 1
  13392. +#define TFA9897_CURRENTSENSE4_13_MAX 1
  13393. +#define TFA9897_CURRENTSENSE4_13_MSK 0x2000
  13394. +/** @} */
  13395. +
  13396. +/** \addtogroup 14
  13397. + * @{
  13398. + */
  13399. +/*!
  13400. + Invert se signal
  13401. +*/
  13402. +#define TFA9897_CURRENTSENSE4_14 (0x1<<14)
  13403. +#define TFA9897_CURRENTSENSE4_14_POS 14
  13404. +#define TFA9897_CURRENTSENSE4_14_LEN 1
  13405. +#define TFA9897_CURRENTSENSE4_14_MAX 1
  13406. +#define TFA9897_CURRENTSENSE4_14_MSK 0x4000
  13407. +/** @} */
  13408. +
  13409. +/** \addtogroup 15
  13410. + * @{
  13411. + */
  13412. +/*!
  13413. + switches between Single Ende and differentail mode; 1 = single ended
  13414. +*/
  13415. +#define TFA9897_CURRENTSENSE4_15 (0x1<<15)
  13416. +#define TFA9897_CURRENTSENSE4_15_POS 15
  13417. +#define TFA9897_CURRENTSENSE4_15_LEN 1
  13418. +#define TFA9897_CURRENTSENSE4_15_MAX 1
  13419. +#define TFA9897_CURRENTSENSE4_15_MSK 0x8000
  13420. +/** @} */
  13421. +
  13422. +/** @} */
  13423. +
  13424. +/** mtp_ctrl_reg3 Register ($62) ********************************************/
  13425. +
  13426. +/** \addtogroup _0x62_mtp_ctrl_reg3
  13427. + * @{
  13428. + */
  13429. +#define TFA98XX_MTP_CTRL_REG3 0x62
  13430. +/** \addtogroup 4
  13431. + * @{
  13432. + */
  13433. +/*!
  13434. + not used
  13435. +*/
  13436. +#define TFA98XX_MTP_CTRL_REG3_4 (0x3<<4)
  13437. +#define TFA98XX_MTP_CTRL_REG3_4_POS 4
  13438. +#define TFA98XX_MTP_CTRL_REG3_4_LEN 2
  13439. +#define TFA98XX_MTP_CTRL_REG3_4_MAX 3
  13440. +#define TFA98XX_MTP_CTRL_REG3_4_MSK 0x30
  13441. +/** @} */
  13442. +
  13443. +/** \addtogroup CIMTP
  13444. + * @{
  13445. + */
  13446. +/*!
  13447. + start copying all the data from i2cregs_mtp to mtp [Key 2 protected]
  13448. +*/
  13449. +#define TFA98XX_MTP_CTRL_REG3_CIMTP (0x1<<11)
  13450. +#define TFA98XX_MTP_CTRL_REG3_CIMTP_POS 11
  13451. +#define TFA98XX_MTP_CTRL_REG3_CIMTP_LEN 1
  13452. +#define TFA98XX_MTP_CTRL_REG3_CIMTP_MAX 1
  13453. +#define TFA98XX_MTP_CTRL_REG3_CIMTP_MSK 0x800
  13454. +/** @} */
  13455. +
  13456. +/** \addtogroup 12
  13457. + * @{
  13458. + */
  13459. +/*!
  13460. + not used
  13461. +*/
  13462. +#define TFA98XX_MTP_CTRL_REG3_12 (0x1<<12)
  13463. +#define TFA98XX_MTP_CTRL_REG3_12_POS 12
  13464. +#define TFA98XX_MTP_CTRL_REG3_12_LEN 1
  13465. +#define TFA98XX_MTP_CTRL_REG3_12_MAX 1
  13466. +#define TFA98XX_MTP_CTRL_REG3_12_MSK 0x1000
  13467. +/** @} */
  13468. +
  13469. +/** @} */
  13470. +
  13471. +/** cf_controls Register ($70) ********************************************/
  13472. +
  13473. +/** \addtogroup _0x70_cf_controls
  13474. + * @{
  13475. + */
  13476. +#define TFA98XX_CF_CONTROLS 0x70
  13477. +/** \addtogroup RST
  13478. + * @{
  13479. + */
  13480. +/*!
  13481. + Reset CoolFlux DSP
  13482. + * - 0 = Reset not active [default]
  13483. + * - 1 = Reset active
  13484. +*/
  13485. +#define TFA98XX_CF_CONTROLS_RST (0x1<<0)
  13486. +#define TFA98XX_CF_CONTROLS_RST_POS 0
  13487. +#define TFA98XX_CF_CONTROLS_RST_LEN 1
  13488. +#define TFA98XX_CF_CONTROLS_RST_MAX 1
  13489. +#define TFA98XX_CF_CONTROLS_RST_MSK 0x1
  13490. +/** @} */
  13491. +
  13492. +/** \addtogroup DMEM
  13493. + * @{
  13494. + */
  13495. +/*!
  13496. + Target memory for access
  13497. + * - 0 = pmem [default]
  13498. + * - 1 = xmem
  13499. + * - 2 = ymem
  13500. + * - 3 = iomem
  13501. +*/
  13502. +#define TFA98XX_CF_CONTROLS_DMEM (0x3<<1)
  13503. +#define TFA98XX_CF_CONTROLS_DMEM_POS 1
  13504. +#define TFA98XX_CF_CONTROLS_DMEM_LEN 2
  13505. +#define TFA98XX_CF_CONTROLS_DMEM_MAX 3
  13506. +#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6
  13507. +/** @} */
  13508. +
  13509. +/** \addtogroup AIF
  13510. + * @{
  13511. + */
  13512. +/*!
  13513. + Autoincrement-flag for memory-address
  13514. + * - 0 = Autoincrement ON [default]
  13515. + * - 1 = Autoincrement OFF
  13516. +*/
  13517. +#define TFA98XX_CF_CONTROLS_AIF (0x1<<3)
  13518. +#define TFA98XX_CF_CONTROLS_AIF_POS 3
  13519. +#define TFA98XX_CF_CONTROLS_AIF_LEN 1
  13520. +#define TFA98XX_CF_CONTROLS_AIF_MAX 1
  13521. +#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8
  13522. +/** @} */
  13523. +
  13524. +/** \addtogroup CFINT
  13525. + * @{
  13526. + */
  13527. +/*!
  13528. + Interrupt CoolFlux DSP
  13529. +*/
  13530. +#define TFA98XX_CF_CONTROLS_CFINT (0x1<<4)
  13531. +#define TFA98XX_CF_CONTROLS_CFINT_POS 4
  13532. +#define TFA98XX_CF_CONTROLS_CFINT_LEN 1
  13533. +#define TFA98XX_CF_CONTROLS_CFINT_MAX 1
  13534. +#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10
  13535. +/** @} */
  13536. +
  13537. +/** \addtogroup 5
  13538. + * @{
  13539. + */
  13540. +/*!
  13541. + not used
  13542. +*/
  13543. +#define TFA98XX_CF_CONTROLS_5 (0x7<<5)
  13544. +#define TFA98XX_CF_CONTROLS_5_POS 5
  13545. +#define TFA98XX_CF_CONTROLS_5_LEN 3
  13546. +#define TFA98XX_CF_CONTROLS_5_MAX 7
  13547. +#define TFA98XX_CF_CONTROLS_5_MSK 0xe0
  13548. +/** @} */
  13549. +
  13550. +/** \addtogroup REQ
  13551. + * @{
  13552. + */
  13553. +/*!
  13554. + request for access (8 channels)
  13555. +*/
  13556. +#define TFA98XX_CF_CONTROLS_REQ (0xff<<8)
  13557. +#define TFA98XX_CF_CONTROLS_REQ_POS 8
  13558. +#define TFA98XX_CF_CONTROLS_REQ_LEN 8
  13559. +#define TFA98XX_CF_CONTROLS_REQ_MAX 255
  13560. +#define TFA98XX_CF_CONTROLS_REQ_MSK 0xff00
  13561. +/** @} */
  13562. +
  13563. +/** @} */
  13564. +
  13565. +/** cf_mad Register ($71) ********************************************/
  13566. +
  13567. +/** \addtogroup _0x71_cf_mad
  13568. + * @{
  13569. + */
  13570. +#define TFA98XX_CF_MAD 0x71
  13571. +/** \addtogroup MADD
  13572. + * @{
  13573. + */
  13574. +/*!
  13575. + memory-address to be accessed
  13576. +*/
  13577. +#define TFA98XX_CF_MAD_MADD (0xffff<<0)
  13578. +#define TFA98XX_CF_MAD_MADD_POS 0
  13579. +#define TFA98XX_CF_MAD_MADD_LEN 16
  13580. +#define TFA98XX_CF_MAD_MADD_MAX 65535
  13581. +#define TFA98XX_CF_MAD_MADD_MSK 0xffff
  13582. +/** @} */
  13583. +
  13584. +/** @} */
  13585. +
  13586. +/** cf_mem Register ($72) ********************************************/
  13587. +
  13588. +/** \addtogroup _0x72_cf_mem
  13589. + * @{
  13590. + */
  13591. +#define TFA98XX_CF_MEM 0x72
  13592. +/** \addtogroup MEMA
  13593. + * @{
  13594. + */
  13595. +/*!
  13596. + activate memory access (24- or 32-bits data is written/read to/from memory
  13597. +*/
  13598. +#define TFA98XX_CF_MEM_MEMA (0xffff<<0)
  13599. +#define TFA98XX_CF_MEM_MEMA_POS 0
  13600. +#define TFA98XX_CF_MEM_MEMA_LEN 16
  13601. +#define TFA98XX_CF_MEM_MEMA_MAX 65535
  13602. +#define TFA98XX_CF_MEM_MEMA_MSK 0xffff
  13603. +/** @} */
  13604. +
  13605. +/** @} */
  13606. +
  13607. +/** cf_status Register ($73) ********************************************/
  13608. +
  13609. +/** \addtogroup _0x73_cf_status
  13610. + * @{
  13611. + */
  13612. +#define TFA98XX_CF_STATUS 0x73
  13613. +/** \addtogroup ERR
  13614. + * @{
  13615. + */
  13616. +/*!
  13617. + Coolflux error flags
  13618. +*/
  13619. +#define TFA98XX_CF_STATUS_ERR (0xff<<0)
  13620. +#define TFA98XX_CF_STATUS_ERR_POS 0
  13621. +#define TFA98XX_CF_STATUS_ERR_LEN 8
  13622. +#define TFA98XX_CF_STATUS_ERR_MAX 255
  13623. +#define TFA98XX_CF_STATUS_ERR_MSK 0xff
  13624. +/** @} */
  13625. +
  13626. +/** \addtogroup ACK
  13627. + * @{
  13628. + */
  13629. +/*!
  13630. + acknowledge of requests (8 channels)
  13631. +*/
  13632. +#define TFA98XX_CF_STATUS_ACK (0xff<<8)
  13633. +#define TFA98XX_CF_STATUS_ACK_POS 8
  13634. +#define TFA98XX_CF_STATUS_ACK_LEN 8
  13635. +#define TFA98XX_CF_STATUS_ACK_MAX 255
  13636. +#define TFA98XX_CF_STATUS_ACK_MSK 0xff00
  13637. +/** @} */
  13638. +
  13639. +/** @} */
  13640. +
  13641. +/** mtp_spkr_cal Register ($80) ********************************************/
  13642. +
  13643. +/** \addtogroup _0x80_mtp_spkr_cal
  13644. + * @{
  13645. + */
  13646. +#define TFA98XX_MTP_SPKR_CAL 0x80
  13647. +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP 0x80
  13648. +#define TFA9890_KEY2PROTECTED_SPKR_CAL_MTP_POR 0x0000
  13649. +
  13650. +/** \addtogroup MTPOTC
  13651. + * @{
  13652. + */
  13653. +/*!
  13654. + Calibration schedule (key2 protected)
  13655. + * - 0 = Calibrate after each POR [default]
  13656. + * - 1 = One time calibration
  13657. +*/
  13658. +#define TFA98XX_MTP_SPKR_CAL_MTPOTC (0x1<<0)
  13659. +#define TFA98XX_MTP_SPKR_CAL_MTPOTC_POS 0
  13660. +#define TFA98XX_MTP_SPKR_CAL_MTPOTC_LEN 1
  13661. +#define TFA98XX_MTP_SPKR_CAL_MTPOTC_MAX 1
  13662. +#define TFA98XX_MTP_SPKR_CAL_MTPOTC_MSK 0x1
  13663. +/** @} */
  13664. +
  13665. +/** \addtogroup MTPEX
  13666. + * @{
  13667. + */
  13668. +/*!
  13669. + (key2 protected)
  13670. + * - calibration of Ron has been executed.
  13671. +*/
  13672. +#define TFA98XX_MTP_SPKR_CAL_MTPEX (0x1<<1)
  13673. +#define TFA98XX_MTP_SPKR_CAL_MTPEX_POS 1
  13674. +#define TFA98XX_MTP_SPKR_CAL_MTPEX_LEN 1
  13675. +#define TFA98XX_MTP_SPKR_CAL_MTPEX_MAX 1
  13676. +#define TFA98XX_MTP_SPKR_CAL_MTPEX_MSK 0x2
  13677. +/** @} */
  13678. +
  13679. +/** \addtogroup 2
  13680. + * @{
  13681. + */
  13682. +/*!
  13683. +
  13684. +*/
  13685. +#define TFA98XX_MTP_SPKR_CAL_2 (0x3fff<<2)
  13686. +#define TFA98XX_MTP_SPKR_CAL_2_POS 2
  13687. +#define TFA98XX_MTP_SPKR_CAL_2_LEN 14
  13688. +#define TFA98XX_MTP_SPKR_CAL_2_MAX 16383
  13689. +#define TFA98XX_MTP_SPKR_CAL_2_MSK 0xfffc
  13690. +/** @} */
  13691. +
  13692. +/** @} */
  13693. +
  13694. +/** MTPF Register ($8f) ********************************************/
  13695. +
  13696. +/** \addtogroup _0x8f_MTPF_TFA9890
  13697. + * @{
  13698. + */
  13699. +#define TFA9890_MTPF 0x8f
  13700. +/** \addtogroup VERSION
  13701. + * @{
  13702. + */
  13703. +/*!
  13704. + (key1 protected)
  13705. +*/
  13706. +#define TFA9890_MTPF_VERSION (0xffff<<0)
  13707. +#define TFA9890_MTPF_VERSION_POS 0
  13708. +#define TFA9890_MTPF_VERSION_LEN 16
  13709. +#define TFA9890_MTPF_VERSION_MAX 65535
  13710. +#define TFA9890_MTPF_VERSION_MSK 0xffff
  13711. +/** @} */
  13712. +
  13713. +/** @} */
  13714. +
  13715. +#endif /* TFA98XX_GENREGS_H_ */
  13716. diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c
  13717. index e72f554..50bedd5 100644
  13718. --- a/sound/soc/soc-cache.c
  13719. +++ b/sound/soc/soc-cache.c
  13720. @@ -280,7 +280,7 @@ static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
  13721. unsigned int reg)
  13722. {
  13723. const struct snd_soc_codec_driver *codec_drv;
  13724. - unsigned int min, max, index;
  13725. + int min, max, index;
  13726.  
  13727. codec_drv = codec->driver;
  13728. min = 0;
  13729. @@ -292,7 +292,7 @@ static int snd_soc_get_reg_access_index(struct snd_soc_codec *codec,
  13730. if (codec_drv->reg_access_default[index].reg < reg)
  13731. min = index + 1;
  13732. else
  13733. - max = index;
  13734. + max = index - 1;
  13735. } while (min <= max);
  13736. return -1;
  13737. }
  13738. diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
  13739. index 7672e72..279540f 100644
  13740. --- a/sound/soc/soc-core.c
  13741. +++ b/sound/soc/soc-core.c
  13742. @@ -1339,7 +1339,6 @@ static int soc_probe_link_dais(struct snd_soc_card *card, int num, int order)
  13743. struct snd_soc_platform *platform = rtd->platform;
  13744. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  13745. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  13746. - struct snd_soc_dapm_widget *play_w, *capture_w;
  13747. int ret;
  13748.  
  13749. dev_dbg(card->dev, "ASoC: probe %s dai link %d late %d\n",
  13750. @@ -1420,39 +1419,12 @@ static int soc_probe_link_dais(struct snd_soc_card *card, int num, int order)
  13751. }
  13752. } else {
  13753.  
  13754. - if (!dai_link->params) {
  13755. - /* create the pcm */
  13756. - ret = soc_new_pcm(rtd, num);
  13757. - if (ret < 0) {
  13758. - dev_err(card->dev, "ASoC: can't create pcm %s :%d\n",
  13759. - dai_link->stream_name, ret);
  13760. - return ret;
  13761. - }
  13762. - } else {
  13763. - /* link the DAI widgets */
  13764. - play_w = codec_dai->playback_widget;
  13765. - capture_w = cpu_dai->capture_widget;
  13766. - if (play_w && capture_w) {
  13767. - ret = snd_soc_dapm_new_pcm(card, dai_link->params,
  13768. - capture_w, play_w);
  13769. - if (ret != 0) {
  13770. - dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n",
  13771. - play_w->name, capture_w->name, ret);
  13772. - return ret;
  13773. - }
  13774. - }
  13775. -
  13776. - play_w = cpu_dai->playback_widget;
  13777. - capture_w = codec_dai->capture_widget;
  13778. - if (play_w && capture_w) {
  13779. - ret = snd_soc_dapm_new_pcm(card, dai_link->params,
  13780. - capture_w, play_w);
  13781. - if (ret != 0) {
  13782. - dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n",
  13783. - play_w->name, capture_w->name, ret);
  13784. - return ret;
  13785. - }
  13786. - }
  13787. + /* create the pcm */
  13788. + ret = soc_new_pcm(rtd, num);
  13789. + if (ret < 0) {
  13790. + dev_err(card->dev, "ASoC: can't create pcm %s :%d\n",
  13791. + dai_link->stream_name, ret);
  13792. + return ret;
  13793. }
  13794. }
  13795.  
  13796. diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
  13797. index 7025d68..880ad9e 100644
  13798. --- a/sound/soc/soc-dapm.c
  13799. +++ b/sound/soc/soc-dapm.c
  13800. @@ -1730,10 +1730,14 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
  13801.  
  13802. trace_snd_soc_dapm_walk_done(card);
  13803.  
  13804. - /* Run all the bias changes in parallel */
  13805. - list_for_each_entry(d, &dapm->card->dapm_list, list)
  13806. - async_schedule_domain(dapm_pre_sequence_async, d,
  13807. - &async_domain);
  13808. + /* Run card bias changes at first */
  13809. + dapm_pre_sequence_async(&card->dapm, 0);
  13810. + /* Run other bias changes in parallel */
  13811. + list_for_each_entry(d, &dapm->card->dapm_list, list) {
  13812. + if (d != &card->dapm)
  13813. + async_schedule_domain(dapm_pre_sequence_async, d,
  13814. + &async_domain);
  13815. + }
  13816. async_synchronize_full_domain(&async_domain);
  13817.  
  13818. /* Power down widgets first; try to avoid amplifying pops. */
  13819. @@ -1744,11 +1748,15 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event)
  13820. /* Now power up. */
  13821. dapm_seq_run(dapm, &up_list, event, true);
  13822.  
  13823. - /* Run all the bias changes in parallel */
  13824. - list_for_each_entry(d, &dapm->card->dapm_list, list)
  13825. - async_schedule_domain(dapm_post_sequence_async, d,
  13826. - &async_domain);
  13827. + /* Run other bias changes in parallel */
  13828. + list_for_each_entry(d, &dapm->card->dapm_list, list) {
  13829. + if (d != &card->dapm)
  13830. + async_schedule_domain(dapm_post_sequence_async, d,
  13831. + &async_domain);
  13832. + }
  13833. async_synchronize_full_domain(&async_domain);
  13834. + /* Run card bias changes at last */
  13835. + dapm_post_sequence_async(&card->dapm, 0);
  13836.  
  13837. /* do we need to notify any clients that DAPM event is complete */
  13838. list_for_each_entry(d, &card->dapm_list, list) {
  13839. @@ -3014,7 +3022,7 @@ EXPORT_SYMBOL_GPL(snd_soc_dapm_info_pin_switch);
  13840. * @kcontrol: mixer control
  13841. * @ucontrol: Value
  13842. */
  13843. -int snd_soc_dapm_get_pin_switch(struct snd_kcontrol *kcontrol,
  13844. +int snd_soc_dapm_get_pin_switch (struct snd_kcontrol *kcontrol,
  13845. struct snd_ctl_elem_value *ucontrol)
  13846. {
  13847. struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
  13848. @@ -3212,38 +3220,25 @@ EXPORT_SYMBOL_GPL(snd_soc_dapm_new_controls);
  13849. static int snd_soc_dai_link_event(struct snd_soc_dapm_widget *w,
  13850. struct snd_kcontrol *kcontrol, int event)
  13851. {
  13852. - struct snd_soc_dapm_path *source_p, *sink_p;
  13853. - struct snd_soc_dai *source, *sink;
  13854. - const struct snd_soc_pcm_stream *config = w->params;
  13855. - struct snd_pcm_substream substream;
  13856. + struct snd_soc_dapm_path *source_p;
  13857. + struct snd_soc_dai *source;
  13858. + struct snd_soc_pcm_runtime *rtd = w->rtd;
  13859. + const struct snd_soc_pcm_stream *config = rtd->dai_link->params;
  13860. + struct snd_pcm_substream *substream = w->priv;
  13861. struct snd_pcm_hw_params *params = NULL;
  13862. - u64 fmt;
  13863. - int ret;
  13864. + int ret = 0;
  13865.  
  13866. BUG_ON(!config);
  13867. - BUG_ON(list_empty(&w->sources) || list_empty(&w->sinks));
  13868. + BUG_ON(list_empty(&w->sources));
  13869.  
  13870. - /* We only support a single source and sink, pick the first */
  13871. + /* We only support a single source, pick the first */
  13872. source_p = list_first_entry(&w->sources, struct snd_soc_dapm_path,
  13873. list_sink);
  13874. - sink_p = list_first_entry(&w->sinks, struct snd_soc_dapm_path,
  13875. - list_source);
  13876. -
  13877. - BUG_ON(!source_p || !sink_p);
  13878. - BUG_ON(!sink_p->source || !source_p->sink);
  13879. - BUG_ON(!source_p->source || !sink_p->sink);
  13880. + BUG_ON(!source_p);
  13881. + BUG_ON(!source_p->sink);
  13882. + BUG_ON(!source_p->source);
  13883.  
  13884. source = source_p->source->priv;
  13885. - sink = sink_p->sink->priv;
  13886. -
  13887. - /* Be a little careful as we don't want to overflow the mask array */
  13888. - if (config->formats) {
  13889. - fmt = ffs(config->formats) - 1;
  13890. - } else {
  13891. - dev_warn(w->dapm->dev, "ASoC: Invalid format %llx specified\n",
  13892. - config->formats);
  13893. - fmt = 0;
  13894. - }
  13895.  
  13896. /* Currently very limited parameter selection */
  13897. params = kzalloc(sizeof(*params), GFP_KERNEL);
  13898. @@ -3251,7 +3246,12 @@ static int snd_soc_dai_link_event(struct snd_soc_dapm_widget *w,
  13899. ret = -ENOMEM;
  13900. goto out;
  13901. }
  13902. - snd_mask_set(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), fmt);
  13903. + _snd_pcm_hw_params_any(params);
  13904. +
  13905. + hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT)->bits[0] =
  13906. + config->formats;
  13907. + hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT)->bits[1] =
  13908. + config->formats >> 32;
  13909.  
  13910. hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->min =
  13911. config->rate_min;
  13912. @@ -3263,47 +3263,38 @@ static int snd_soc_dai_link_event(struct snd_soc_dapm_widget *w,
  13913. hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS)->max
  13914. = config->channels_max;
  13915.  
  13916. - memset(&substream, 0, sizeof(substream));
  13917. -
  13918. switch (event) {
  13919. case SND_SOC_DAPM_PRE_PMU:
  13920. - if (source->driver->ops && source->driver->ops->hw_params) {
  13921. - substream.stream = SNDRV_PCM_STREAM_CAPTURE;
  13922. - ret = source->driver->ops->hw_params(&substream,
  13923. - params, source);
  13924. - if (ret != 0) {
  13925. - dev_err(source->dev,
  13926. - "ASoC: hw_params() failed: %d\n", ret);
  13927. - goto out;
  13928. - }
  13929. + ret = snd_pcm_open_substream(rtd->pcm,
  13930. + source == rtd->codec_dai, NULL, &substream);
  13931. + if (ret < 0) {
  13932. + dev_err(w->dapm->dev, "ASoC: open() failed: %d\n", ret);
  13933. + goto out;
  13934. }
  13935. + w->priv = substream;
  13936.  
  13937. - if (sink->driver->ops && sink->driver->ops->hw_params) {
  13938. - substream.stream = SNDRV_PCM_STREAM_PLAYBACK;
  13939. - ret = sink->driver->ops->hw_params(&substream, params,
  13940. - sink);
  13941. - if (ret != 0) {
  13942. - dev_err(sink->dev,
  13943. - "ASoC: hw_params() failed: %d\n", ret);
  13944. - goto out;
  13945. - }
  13946. + ret = rtd->ops.hw_params(substream, params);
  13947. + if (ret < 0) {
  13948. + dev_err(w->dapm->dev, "ASoC: hw_params() failed: %d\n", ret);
  13949. + goto out;
  13950. + }
  13951. + ret = rtd->ops.prepare(substream);
  13952. + if (ret < 0) {
  13953. + dev_err(w->dapm->dev, "ASoC: prepare() failed: %d\n", ret);
  13954. + goto out;
  13955. + }
  13956. + ret = rtd->ops.trigger(substream, SNDRV_PCM_TRIGGER_START);
  13957. + if (ret < 0) {
  13958. + dev_err(w->dapm->dev, "ASoC: trigger() failed: %d\n", ret);
  13959. + goto out;
  13960. }
  13961. - break;
  13962. -
  13963. - case SND_SOC_DAPM_POST_PMU:
  13964. - ret = snd_soc_dai_digital_mute(sink, 0,
  13965. - SNDRV_PCM_STREAM_PLAYBACK);
  13966. - if (ret != 0 && ret != -ENOTSUPP)
  13967. - dev_warn(sink->dev, "ASoC: Failed to unmute: %d\n", ret);
  13968. - ret = 0;
  13969. break;
  13970.  
  13971. case SND_SOC_DAPM_PRE_PMD:
  13972. - ret = snd_soc_dai_digital_mute(sink, 1,
  13973. - SNDRV_PCM_STREAM_PLAYBACK);
  13974. - if (ret != 0 && ret != -ENOTSUPP)
  13975. - dev_warn(sink->dev, "ASoC: Failed to mute: %d\n", ret);
  13976. - ret = 0;
  13977. + if (substream) {
  13978. + snd_pcm_release_substream(substream);
  13979. + w->priv = NULL;
  13980. + }
  13981. break;
  13982.  
  13983. default:
  13984. @@ -3316,51 +3307,67 @@ out:
  13985. return ret;
  13986. }
  13987.  
  13988. -int snd_soc_dapm_new_pcm(struct snd_soc_card *card,
  13989. - const struct snd_soc_pcm_stream *params,
  13990. - struct snd_soc_dapm_widget *source,
  13991. - struct snd_soc_dapm_widget *sink)
  13992. +int snd_soc_dapm_new_dai_link_widgets(struct snd_soc_dapm_context *dapm,
  13993. + struct snd_soc_pcm_runtime *rtd)
  13994. {
  13995. struct snd_soc_dapm_route routes[2];
  13996. struct snd_soc_dapm_widget template;
  13997. + struct snd_soc_dapm_widget *source;
  13998. + struct snd_soc_dapm_widget *sink;
  13999. struct snd_soc_dapm_widget *w;
  14000. size_t len;
  14001. char *link_name;
  14002. + int i, ret = 0;
  14003.  
  14004. - len = strlen(source->name) + strlen(sink->name) + 2;
  14005. - link_name = devm_kzalloc(card->dev, len, GFP_KERNEL);
  14006. - if (!link_name)
  14007. - return -ENOMEM;
  14008. - snprintf(link_name, len, "%s-%s", source->name, sink->name);
  14009. + for (i = 0; i < 2; i++) {
  14010. + if (i == 0) {
  14011. + source = rtd->cpu_dai->capture_widget;
  14012. + sink = rtd->codec_dai->playback_widget;
  14013. + } else {
  14014. + source = rtd->codec_dai->capture_widget;
  14015. + sink = rtd->cpu_dai->playback_widget;
  14016. + }
  14017.  
  14018. - memset(&template, 0, sizeof(template));
  14019. - template.reg = SND_SOC_NOPM;
  14020. - template.id = snd_soc_dapm_dai_link;
  14021. - template.name = link_name;
  14022. - template.event = snd_soc_dai_link_event;
  14023. - template.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  14024. - SND_SOC_DAPM_PRE_PMD;
  14025. +len = strlen(source->name) + strlen(sink->name) + 2;
  14026. + link_name = devm_kzalloc(dapm->dev, len, GFP_KERNEL);
  14027. + if (!link_name)
  14028. + return -ENOMEM;
  14029. + snprintf(link_name, len, "%s-%s", source->name, sink->name);
  14030.  
  14031. - dev_dbg(card->dev, "ASoC: adding %s widget\n", link_name);
  14032. + memset(&template, 0, sizeof(template));
  14033. + template.reg = SND_SOC_NOPM;
  14034. + template.id = snd_soc_dapm_dai_link;
  14035. + template.name = link_name;
  14036. + template.event = snd_soc_dai_link_event;
  14037. + template.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD;
  14038.  
  14039. - w = snd_soc_dapm_new_control(&card->dapm, &template);
  14040. - if (!w) {
  14041. - dev_err(card->dev, "ASoC: Failed to create %s widget\n",
  14042. - link_name);
  14043. - return -ENOMEM;
  14044. - }
  14045. + dev_dbg(dapm->dev, "ASoC: adding %s widget\n", link_name);
  14046.  
  14047. - w->params = params;
  14048. + w = snd_soc_dapm_new_control(dapm, &template);
  14049. + if (!w) {
  14050. + dev_err(dapm->dev, "ASoC: Failed to create %s widget\n",
  14051. + link_name);
  14052. + return -ENOMEM;
  14053. + }
  14054. +
  14055. + w->rtd = rtd;
  14056.  
  14057. - memset(&routes, 0, sizeof(routes));
  14058. + memset(&routes, 0, sizeof(routes));
  14059.  
  14060. - routes[0].source = source->name;
  14061. - routes[0].sink = link_name;
  14062. - routes[1].source = link_name;
  14063. - routes[1].sink = sink->name;
  14064. + routes[0].source = source->name;
  14065. + routes[0].sink = link_name;
  14066. + routes[1].source = link_name;
  14067. + routes[1].sink = sink->name;
  14068.  
  14069. - return snd_soc_dapm_add_routes(&card->dapm, routes,
  14070. - ARRAY_SIZE(routes));
  14071. + ret = snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
  14072. + if (ret < 0) {
  14073. + dev_err(dapm->dev, "ASoC: Failed to add %s route\n",
  14074. + link_name);
  14075. + return ret;
  14076. + }
  14077. + }
  14078. +
  14079. + return ret;
  14080. }
  14081.  
  14082. int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
  14083. @@ -3451,7 +3458,7 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card)
  14084. break;
  14085. }
  14086.  
  14087. - if (!w->sname)
  14088. + if (!w->sname || !strstr(w->sname, dai_w->name))
  14089. continue;
  14090.  
  14091. if (dai->driver->playback.stream_name &&
  14092. @@ -3778,7 +3785,7 @@ void snd_soc_dapm_free(struct snd_soc_dapm_context *dapm)
  14093. }
  14094. EXPORT_SYMBOL_GPL(snd_soc_dapm_free);
  14095.  
  14096. -static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm)
  14097. +static void soc_dapm_shutdown_dapm(struct snd_soc_dapm_context *dapm)
  14098. {
  14099. struct snd_soc_card *card = dapm->card;
  14100. struct snd_soc_dapm_widget *w;
  14101. @@ -3818,14 +3825,21 @@ static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm)
  14102. */
  14103. void snd_soc_dapm_shutdown(struct snd_soc_card *card)
  14104. {
  14105. - struct snd_soc_codec *codec;
  14106. + struct snd_soc_dapm_context *dapm;
  14107.  
  14108. - list_for_each_entry(codec, &card->codec_dev_list, card_list) {
  14109. - soc_dapm_shutdown_codec(&codec->dapm);
  14110. - if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
  14111. - snd_soc_dapm_set_bias_level(&codec->dapm,
  14112. - SND_SOC_BIAS_OFF);
  14113. + list_for_each_entry(dapm, &card->dapm_list, list) {
  14114. + if (dapm != &card->dapm) {
  14115. + soc_dapm_shutdown_dapm(dapm);
  14116. + if (dapm->bias_level == SND_SOC_BIAS_STANDBY)
  14117. + snd_soc_dapm_set_bias_level(dapm,
  14118. + SND_SOC_BIAS_OFF);
  14119. + }
  14120. }
  14121. +
  14122. + soc_dapm_shutdown_dapm(&card->dapm);
  14123. + if (card->dapm.bias_level == SND_SOC_BIAS_STANDBY)
  14124. + snd_soc_dapm_set_bias_level(&card->dapm,
  14125. + SND_SOC_BIAS_OFF);
  14126. }
  14127.  
  14128. /* Module information */
  14129. diff --git a/sound/soc/soc-jack.c b/sound/soc/soc-jack.c
  14130. index 0bb5ccc..8e4a579 100644
  14131. --- a/sound/soc/soc-jack.c
  14132. +++ b/sound/soc/soc-jack.c
  14133. @@ -247,7 +247,7 @@ static void snd_soc_jack_gpio_detect(struct snd_soc_jack_gpio *gpio)
  14134. report = 0;
  14135.  
  14136. if (gpio->jack_status_check)
  14137. - report = gpio->jack_status_check();
  14138. + report = gpio->jack_status_check(gpio);
  14139.  
  14140. snd_soc_jack_report(jack, report, gpio->report);
  14141. }
  14142. @@ -339,7 +339,8 @@ int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count,
  14143. gpio_export(gpios[i].gpio, false);
  14144.  
  14145. /* Update initial jack status */
  14146. - snd_soc_jack_gpio_detect(&gpios[i]);
  14147. + schedule_delayed_work(&gpios[i].work,
  14148. + msecs_to_jiffies(gpios[i].debounce_time));
  14149. }
  14150.  
  14151. return 0;
  14152. diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
  14153. index 9a93bef..4d75a06 100644
  14154. --- a/sound/soc/soc-pcm.c
  14155. +++ b/sound/soc/soc-pcm.c
  14156. @@ -124,6 +124,21 @@ static void soc_pcm_apply_msb(struct snd_pcm_substream *substream,
  14157. }
  14158. }
  14159.  
  14160. +static void soc_pcm_reverse_direction_for_cpu_dai(struct snd_pcm_substream *substream)
  14161. +{
  14162. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  14163. +
  14164. + /* reverse the stream direction if the link has
  14165. + params since cpu dai actually come from codec */
  14166. + if (rtd->dai_link->params) {
  14167. + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  14168. + substream->stream = SNDRV_PCM_STREAM_CAPTURE;
  14169. + else
  14170. + substream->stream = SNDRV_PCM_STREAM_PLAYBACK;
  14171. + }
  14172. +}
  14173. +
  14174. +
  14175. /*
  14176. * Called by ALSA when a PCM substream is opened, the runtime->hw record is
  14177. * then initialized and any private data can be allocated. This also calls
  14178. @@ -148,7 +163,9 @@ static int soc_pcm_open(struct snd_pcm_substream *substream)
  14179.  
  14180. /* startup the audio subsystem */
  14181. if (cpu_dai->driver->ops->startup) {
  14182. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14183. ret = cpu_dai->driver->ops->startup(substream, cpu_dai);
  14184. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14185. if (ret < 0) {
  14186. dev_err(cpu_dai->dev, "ASoC: can't open interface"
  14187. " %s: %d\n", cpu_dai->name, ret);
  14188. @@ -306,8 +323,11 @@ codec_dai_err:
  14189. platform->driver->ops->close(substream);
  14190.  
  14191. platform_err:
  14192. - if (cpu_dai->driver->ops->shutdown)
  14193. + if (cpu_dai->driver->ops->shutdown) {
  14194. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14195. cpu_dai->driver->ops->shutdown(substream, cpu_dai);
  14196. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14197. + }
  14198. out:
  14199. mutex_unlock(&rtd->pcm_mutex);
  14200.  
  14201. @@ -384,9 +404,15 @@ static int soc_pcm_close(struct snd_pcm_substream *substream)
  14202. * shutdown, for example from stopping clocks.
  14203. */
  14204. snd_soc_dai_digital_mute(codec_dai, 1, substream->stream);
  14205. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14206. + snd_soc_dai_digital_mute(cpu_dai, 1, substream->stream);
  14207. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14208.  
  14209. - if (cpu_dai->driver->ops->shutdown)
  14210. + if (cpu_dai->driver->ops->shutdown) {
  14211. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14212. cpu_dai->driver->ops->shutdown(substream, cpu_dai);
  14213. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14214. + }
  14215.  
  14216. if (codec_dai->driver->ops->shutdown)
  14217. codec_dai->driver->ops->shutdown(substream, codec_dai);
  14218. @@ -398,23 +424,26 @@ static int soc_pcm_close(struct snd_pcm_substream *substream)
  14219. platform->driver->ops->close(substream);
  14220. cpu_dai->runtime = NULL;
  14221.  
  14222. - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  14223. - if (!rtd->pmdown_time || codec->ignore_pmdown_time ||
  14224. - rtd->dai_link->ignore_pmdown_time) {
  14225. - /* powered down playback stream now */
  14226. - snd_soc_dapm_stream_event(rtd,
  14227. - SNDRV_PCM_STREAM_PLAYBACK,
  14228. + /* dai with params is skipped to avoid the recursive */
  14229. + if (!rtd->dai_link->params) {
  14230. + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  14231. + if (!rtd->pmdown_time || codec->ignore_pmdown_time ||
  14232. + rtd->dai_link->ignore_pmdown_time) {
  14233. + /* powered down playback stream now */
  14234. + snd_soc_dapm_stream_event(rtd,
  14235. + SNDRV_PCM_STREAM_PLAYBACK,
  14236. + SND_SOC_DAPM_STREAM_STOP);
  14237. + } else {
  14238. + /* capture streams can be powered down now */
  14239. + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE,
  14240. SND_SOC_DAPM_STREAM_STOP);
  14241. + }
  14242. } else {
  14243. /* start delayed pop wq here for playback streams */
  14244. rtd->pop_wait = 1;
  14245. schedule_delayed_work(&rtd->delayed_work,
  14246. msecs_to_jiffies(rtd->pmdown_time));
  14247. }
  14248. - } else {
  14249. - /* capture streams can be powered down now */
  14250. - snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE,
  14251. - SND_SOC_DAPM_STREAM_STOP);
  14252. }
  14253.  
  14254. mutex_unlock(&rtd->pcm_mutex);
  14255. @@ -469,7 +498,9 @@ static int soc_pcm_prepare(struct snd_pcm_substream *substream)
  14256. }
  14257.  
  14258. if (cpu_dai->driver->ops->prepare) {
  14259. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14260. ret = cpu_dai->driver->ops->prepare(substream, cpu_dai);
  14261. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14262. if (ret < 0) {
  14263. dev_err(cpu_dai->dev, "ASoC: DAI prepare error: %d\n",
  14264. ret);
  14265. @@ -477,16 +508,22 @@ static int soc_pcm_prepare(struct snd_pcm_substream *substream)
  14266. }
  14267. }
  14268.  
  14269. - /* cancel any delayed stream shutdown that is pending */
  14270. - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  14271. - rtd->pop_wait) {
  14272. - rtd->pop_wait = 0;
  14273. - cancel_delayed_work(&rtd->delayed_work);
  14274. - }
  14275. + /* dai with params is skipped to avoid the recursive */
  14276. + if (!rtd->dai_link->params) {
  14277. + /* cancel any delayed stream shutdown that is pending */
  14278. + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
  14279. + rtd->pop_wait) {
  14280. + rtd->pop_wait = 0;
  14281. + cancel_delayed_work(&rtd->delayed_work);
  14282. + }
  14283.  
  14284. - snd_soc_dapm_stream_event(rtd, substream->stream,
  14285. - SND_SOC_DAPM_STREAM_START);
  14286. + snd_soc_dapm_stream_event(rtd, substream->stream,
  14287. + SND_SOC_DAPM_STREAM_START);
  14288. + }
  14289.  
  14290. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14291. + snd_soc_dai_digital_mute(cpu_dai, 0, substream->stream);
  14292. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14293. snd_soc_dai_digital_mute(codec_dai, 0, substream->stream);
  14294.  
  14295. out:
  14296. @@ -497,7 +534,7 @@ out:
  14297. /*
  14298. * Called by ALSA when the hardware params are set by application. This
  14299. * function can also be called multiple times and can allocate buffers
  14300. - * (using snd_pcm_lib_* ). It's non-atomic.
  14301. + * (using snd_pcm_lib_*). It's non-atomic.
  14302. */
  14303. static int soc_pcm_hw_params(struct snd_pcm_substream *substream,
  14304. struct snd_pcm_hw_params *params)
  14305. @@ -529,7 +566,9 @@ static int soc_pcm_hw_params(struct snd_pcm_substream *substream,
  14306. }
  14307.  
  14308. if (cpu_dai->driver->ops->hw_params) {
  14309. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14310. ret = cpu_dai->driver->ops->hw_params(substream, params, cpu_dai);
  14311. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14312. if (ret < 0) {
  14313. dev_err(cpu_dai->dev, "ASoC: %s hw params failed: %d\n",
  14314. cpu_dai->name, ret);
  14315. @@ -555,8 +594,11 @@ out:
  14316. return ret;
  14317.  
  14318. platform_err:
  14319. - if (cpu_dai->driver->ops->hw_free)
  14320. + if (cpu_dai->driver->ops->hw_free) {
  14321. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14322. cpu_dai->driver->ops->hw_free(substream, cpu_dai);
  14323. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14324. + }
  14325.  
  14326. interface_err:
  14327. if (codec_dai->driver->ops->hw_free)
  14328. @@ -584,8 +626,12 @@ static int soc_pcm_hw_free(struct snd_pcm_substream *substream)
  14329. mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass);
  14330.  
  14331. /* apply codec digital mute */
  14332. - if (!codec->active)
  14333. + if (!codec->active) {
  14334. snd_soc_dai_digital_mute(codec_dai, 1, substream->stream);
  14335. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14336. + snd_soc_dai_digital_mute(cpu_dai, 1, substream->stream);
  14337. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14338. + }
  14339.  
  14340. /* free any machine hw params */
  14341. if (rtd->dai_link->ops && rtd->dai_link->ops->hw_free)
  14342. @@ -599,8 +645,11 @@ static int soc_pcm_hw_free(struct snd_pcm_substream *substream)
  14343. if (codec_dai->driver->ops->hw_free)
  14344. codec_dai->driver->ops->hw_free(substream, codec_dai);
  14345.  
  14346. - if (cpu_dai->driver->ops->hw_free)
  14347. + if (cpu_dai->driver->ops->hw_free) {
  14348. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14349. cpu_dai->driver->ops->hw_free(substream, cpu_dai);
  14350. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14351. + }
  14352.  
  14353. mutex_unlock(&rtd->pcm_mutex);
  14354. return 0;
  14355. @@ -627,7 +676,9 @@ static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  14356. }
  14357.  
  14358. if (cpu_dai->driver->ops->trigger) {
  14359. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14360. ret = cpu_dai->driver->ops->trigger(substream, cmd, cpu_dai);
  14361. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14362. if (ret < 0)
  14363. return ret;
  14364. }
  14365. @@ -656,7 +707,9 @@ static int soc_pcm_bespoke_trigger(struct snd_pcm_substream *substream,
  14366. }
  14367.  
  14368. if (cpu_dai->driver->ops->bespoke_trigger) {
  14369. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14370. ret = cpu_dai->driver->ops->bespoke_trigger(substream, cmd, cpu_dai);
  14371. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14372. if (ret < 0)
  14373. return ret;
  14374. }
  14375. @@ -680,8 +733,11 @@ static snd_pcm_uframes_t soc_pcm_pointer(struct snd_pcm_substream *substream)
  14376. if (platform->driver->ops && platform->driver->ops->pointer)
  14377. offset = platform->driver->ops->pointer(substream);
  14378.  
  14379. - if (cpu_dai->driver->ops->delay)
  14380. + if (cpu_dai->driver->ops->delay) {
  14381. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14382. delay += cpu_dai->driver->ops->delay(substream, cpu_dai);
  14383. + soc_pcm_reverse_direction_for_cpu_dai(substream);
  14384. + }
  14385.  
  14386. if (codec_dai->driver->ops->delay)
  14387. delay += codec_dai->driver->ops->delay(substream, codec_dai);
  14388. @@ -2037,8 +2093,13 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num)
  14389. snprintf(new_name, sizeof(new_name), "%s %s-%d",
  14390. rtd->dai_link->stream_name, codec_dai->name, num);
  14391.  
  14392. - ret = snd_pcm_new(rtd->card->snd_card, new_name, num, playback,
  14393. - capture, &pcm);
  14394. + /* dai with params can only be used by kernel */
  14395. + if (rtd->dai_link->params)
  14396. + ret = snd_pcm_new_internal(rtd->card->snd_card, new_name, num,
  14397. + playback, capture, &pcm);
  14398. + else
  14399. + ret = snd_pcm_new(rtd->card->snd_card, new_name, num, playback,
  14400. + capture, &pcm);
  14401. }
  14402. if (ret < 0) {
  14403. dev_err(rtd->card->dev, "ASoC: can't create pcm for %s\n",
  14404. @@ -2107,6 +2168,16 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num)
  14405. }
  14406.  
  14407. pcm->private_free = platform->driver->pcm_free;
  14408. +
  14409. + if (rtd->dai_link->params) {
  14410. + ret = snd_soc_dapm_new_dai_link_widgets(&rtd->card->dapm, rtd);
  14411. + if (ret < 0) {
  14412. + dev_err(rtd->card->dev, "ASoC: Can't link %s: %d\n",
  14413. + rtd->dai_link->name, ret);
  14414. + return ret;
  14415. + }
  14416. + }
  14417. +
  14418. out:
  14419. dev_info(rtd->card->dev, " %s <-> %s mapping ok\n", codec_dai->name,
  14420. cpu_dai->name);
  14421. diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
  14422. index 6484c80..d0bc81d 100644
  14423. --- a/sound/soc/tegra/Kconfig
  14424. +++ b/sound/soc/tegra/Kconfig
  14425. @@ -319,6 +319,19 @@ config SND_SOC_TEGRA_RT5645
  14426. Say Y or M here if you want to add support for SoC audio on Tegra
  14427. boards using the ALC5645 codec. Currently, the supported boards
  14428. are Ardbeg.
  14429. +
  14430. +config SND_SOC_TEGRA_RT5671
  14431. + tristate "SoC Audio support for Tegra boards using a ALC5671 codec"
  14432. + depends on SND_SOC_TEGRA && I2C && TEGRA_DC
  14433. + select SND_SOC_TEGRA30_I2S if !ARCH_TEGRA_2x_SOC
  14434. + select SND_SOC_TEGRA30_SPDIF if !ARCH_TEGRA_2x_SOC
  14435. + select SND_SOC_TFA98XX
  14436. + select SND_SOC_RT5671
  14437. + select SND_SOC_SPDIF
  14438. + select SND_SOC_TEGRA30_DAM if !ARCH_TEGRA_2x_SOC
  14439. + help
  14440. + Say Y or M here if you want to add support for SoC audio on Tegra
  14441. + boards using the ALC5671 codec.
  14442.  
  14443. config SND_SOC_TEGRA_MAX98095
  14444. tristate "SoC Audio support for Tegra boards using a MAX98095 codec"
  14445. diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile
  14446. index 0434fa1..7aac85f 100644
  14447. --- a/sound/soc/tegra/Makefile
  14448. +++ b/sound/soc/tegra/Makefile
  14449. @@ -40,6 +40,7 @@ snd-soc-tegra-aic325x-objs := tegra_aic325x.o
  14450. snd-soc-tegra-rt5640-objs := tegra_rt5640.o
  14451. snd-soc-tegra-rt5645-objs := tegra_rt5645.o
  14452. snd-soc-tegra-rt5639-objs := tegra_rt5639.o
  14453. +snd-soc-tegra-rt5671-objs := tegra_rt5671.o
  14454. snd-soc-tegra-max98095-objs := tegra_max98095.o
  14455. snd-soc-tegra-vcm-objs := tegra_vcm.o
  14456. snd-soc-tegra-cs42l73-objs := tegra_cs42l73.o
  14457. @@ -57,6 +58,7 @@ obj-$(CONFIG_SND_SOC_TEGRA_TLV320AIC325X) += snd-soc-tegra-aic325x.o
  14458. obj-$(CONFIG_SND_SOC_TEGRA_RT5640) += snd-soc-tegra-rt5640.o
  14459. obj-$(CONFIG_SND_SOC_TEGRA_RT5645) += snd-soc-tegra-rt5645.o
  14460. obj-$(CONFIG_SND_SOC_TEGRA_RT5639) += snd-soc-tegra-rt5639.o
  14461. +obj-$(CONFIG_SND_SOC_TEGRA_RT5671) += snd-soc-tegra-rt5671.o
  14462. obj-$(CONFIG_SND_SOC_TEGRA_MAX98095) += snd-soc-tegra-max98095.o
  14463. obj-$(CONFIG_SND_SOC_TEGRA_P1852) += snd-soc-tegra-vcm.o
  14464. obj-$(CONFIG_SND_SOC_TEGRA_E1853) += snd-soc-tegra-vcm.o
  14465. diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
  14466. index a9f3370..813d472 100644
  14467. --- a/sound/soc/tegra/tegra_asoc_utils.c
  14468. +++ b/sound/soc/tegra/tegra_asoc_utils.c
  14469. @@ -467,12 +467,27 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_lock_clk_rate);
  14470. int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data)
  14471. {
  14472. int err;
  14473. -
  14474. +
  14475. + err = clk_prepare_enable(data->clk_audio_emc);
  14476. + if (err) {
  14477. + dev_err(data->dev, "Can't enable emc: %d\n", err);
  14478. + return err;
  14479. + }
  14480. err = clk_prepare_enable(data->clk_cdev1);
  14481. if (err) {
  14482. dev_err(data->dev, "Can't enable cdev1: %d\n", err);
  14483. + clk_disable_unprepare(data->clk_audio_emc);
  14484. return err;
  14485. }
  14486. + if (!IS_ERR(data->clk_out1)) {
  14487. + err = clk_prepare_enable(data->clk_out1);
  14488. + if (err) {
  14489. + dev_err(data->dev, "Can't enable clk out1: %d\n", err);
  14490. + clk_disable_unprepare(data->clk_cdev1);
  14491. + clk_disable_unprepare(data->clk_audio_emc);
  14492. + return err;
  14493. + }
  14494. + }
  14495.  
  14496. return 0;
  14497. }
  14498. @@ -480,7 +495,10 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_enable);
  14499.  
  14500. int tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data)
  14501. {
  14502. + if (!IS_ERR(data->clk_out1))
  14503. + clk_disable_unprepare(data->clk_out1);
  14504. clk_disable_unprepare(data->clk_cdev1);
  14505. + clk_disable_unprepare(data->clk_audio_emc);
  14506. return 0;
  14507. }
  14508. EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_disable);
  14509. @@ -526,12 +544,19 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
  14510.  
  14511. data->dev = dev;
  14512. data->card = card;
  14513. +
  14514. + data->clk_audio_emc = clk_get_sys("audio", "emc");
  14515. + if (IS_ERR(data->clk_audio_emc)) {
  14516. + dev_err(data->dev, "Can't retrieve clk emc\n");
  14517. + ret = PTR_ERR(data->clk_audio_emc);
  14518. + goto err;
  14519. + }
  14520.  
  14521. data->clk_pll_p_out1 = clk_get_sys(NULL, "pll_p_out1");
  14522. if (IS_ERR(data->clk_pll_p_out1)) {
  14523. dev_err(data->dev, "Can't retrieve clk pll_p_out1\n");
  14524. ret = PTR_ERR(data->clk_pll_p_out1);
  14525. - goto err;
  14526. + goto err_put_audio_emc;
  14527. }
  14528.  
  14529. if (of_machine_is_compatible("nvidia,tegra20"))
  14530. @@ -603,6 +628,12 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
  14531. goto err_put_cdev1;
  14532. }
  14533. }
  14534. +
  14535. + ret = clk_prepare_enable(data->clk_audio_emc);
  14536. + if (ret) {
  14537. + dev_err(data->dev, "Can't enable clk emc");
  14538. + goto err_put_out1;
  14539. + }
  14540.  
  14541. ret = clk_prepare_enable(data->clk_cdev1);
  14542. if (ret) {
  14543. @@ -635,6 +666,8 @@ err_put_pll_a:
  14544. clk_put(data->clk_pll_a);
  14545. err_put_pll_p_out1:
  14546. clk_put(data->clk_pll_p_out1);
  14547. +err_put_audio_emc:
  14548. + clk_put(data->clk_audio_emc);
  14549. err:
  14550. return ret;
  14551. }
  14552. @@ -688,6 +721,9 @@ void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
  14553.  
  14554. if (!IS_ERR(data->clk_pll_p_out1))
  14555. clk_put(data->clk_pll_p_out1);
  14556. +
  14557. + if (!IS_ERR(data->clk_audio_emc))
  14558. + clk_put(data->clk_audio_emc);
  14559. }
  14560. EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
  14561.  
  14562. diff --git a/sound/soc/tegra/tegra_asoc_utils.h b/sound/soc/tegra/tegra_asoc_utils.h
  14563. index 346b01a..cf4ee26 100644
  14564. --- a/sound/soc/tegra/tegra_asoc_utils.h
  14565. +++ b/sound/soc/tegra/tegra_asoc_utils.h
  14566. @@ -45,6 +45,7 @@ struct tegra_asoc_utils_data {
  14567. struct device *dev;
  14568. struct snd_soc_card *card;
  14569. enum tegra_asoc_utils_soc soc;
  14570. + struct clk *clk_audio_emc;
  14571. struct clk *clk_pll_a;
  14572. struct clk *clk_pll_a_out0;
  14573. struct clk *clk_cdev1;
  14574. diff --git a/sound/soc/tegra/tegra_rt5671.c b/sound/soc/tegra/tegra_rt5671.c
  14575. new file mode 100644
  14576. index 0000000..d73b2c0
  14577. --- /dev/null
  14578. +++ b/sound/soc/tegra/tegra_rt5671.c
  14579. @@ -0,0 +1,951 @@
  14580. +/*
  14581. + * tegra_rt5671.c - Tegra machine ASoC driver for boards using ALC5671 codec.
  14582. + *
  14583. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
  14584. + * Copyright (C) 2016 XiaoMi, Inc.
  14585. + * This program is free software; you can redistribute it and/or
  14586. + * modify it under the terms of the GNU General Public License
  14587. + * version 2 as published by the Free Software Foundation.
  14588. + *
  14589. + * This program is distributed in the hope that it will be useful, but
  14590. + * WITHOUT ANY WARRANTY; without even the implied warranty of
  14591. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14592. + * General Public License for more details.
  14593. + *
  14594. + * You should have received a copy of the GNU General Public License
  14595. + * along with this program; if not, write to the Free Software
  14596. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  14597. + * 02110-1301 USA
  14598. + *
  14599. + */
  14600. +
  14601. +#include <asm/mach-types.h>
  14602. +#include <linux/of.h>
  14603. +#include <linux/clk.h>
  14604. +#include <linux/module.h>
  14605. +#include <linux/platform_device.h>
  14606. +#include <linux/slab.h>
  14607. +#include <linux/gpio.h>
  14608. +#include <linux/of_gpio.h>
  14609. +#include <linux/regulator/consumer.h>
  14610. +#include <linux/delay.h>
  14611. +#include <linux/pm_runtime.h>
  14612. +#include <mach/tegra_asoc_pdata.h>
  14613. +#include <mach/gpio-tegra.h>
  14614. +#include <mach/tegra_rt5640_pdata.h>
  14615. +
  14616. +#include <sound/core.h>
  14617. +#include <sound/jack.h>
  14618. +#include <sound/pcm.h>
  14619. +#include <sound/pcm_params.h>
  14620. +#include <sound/soc.h>
  14621. +#include "../codecs/rt5671.h"
  14622. +
  14623. +#include "tegra_pcm.h"
  14624. +#include "tegra_asoc_utils.h"
  14625. +#include <linux/tfa9887.h>
  14626. +#include "tegra30_ahub.h"
  14627. +#include "tegra30_i2s.h"
  14628. +
  14629. +#define DRV_NAME "tegra-snd-rt5671"
  14630. +
  14631. +#define DAI_LINK_HIFI 0
  14632. +#define DAI_LINK_LEFT_SPK 1
  14633. +#define DAI_LINK_RIGHT_SPK 2
  14634. +#define DAI_LINK_BTSCO 3
  14635. +#define DAI_LINK_FM 4
  14636. +#define NUM_DAI_LINKS 5
  14637. +
  14638. +const char *tegra_rt5671_i2s_dai_name[TEGRA30_NR_I2S_IFC] = {
  14639. + "tegra30-i2s.0",
  14640. + "tegra30-i2s.1",
  14641. + "tegra30-i2s.2",
  14642. + "tegra30-i2s.3",
  14643. + "tegra30-i2s.4",
  14644. +};
  14645. +
  14646. +#define GPIO_SPKR_EN BIT(0)
  14647. +#define GPIO_HP_MUTE BIT(1)
  14648. +#define GPIO_INT_MIC_EN BIT(2)
  14649. +#define GPIO_EXT_MIC_EN BIT(3)
  14650. +#define GPIO_HP_DET BIT(4)
  14651. +
  14652. +struct tegra_rt5671 {
  14653. + struct tegra_asoc_utils_data util_data;
  14654. + struct tegra_asoc_platform_data *pdata;
  14655. + int gpio_requested;
  14656. + int clock_enabled;
  14657. + struct regulator *codec_reg;
  14658. + struct regulator *digital_reg;
  14659. + struct regulator *analog_reg;
  14660. + struct regulator *spk_reg;
  14661. + struct regulator *mic_reg;
  14662. + struct regulator *dmic_reg;
  14663. + struct snd_soc_card *pcard;
  14664. +};
  14665. +
  14666. +static int tegra_rt5671_set_clock(struct snd_soc_pcm_runtime *rtd,
  14667. + int sample_size, int channel, int srate)
  14668. +{
  14669. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  14670. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  14671. + struct snd_soc_codec *codec = rtd->codec;
  14672. + struct snd_soc_card *card = codec->card;
  14673. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14674. + int err, mclk, rate;
  14675. + unsigned int i2sclock;
  14676. +
  14677. + mclk = 256 * srate;
  14678. + err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
  14679. + if (err < 0) {
  14680. + if (!(machine->util_data.set_mclk % mclk)) {
  14681. + mclk = machine->util_data.set_mclk;
  14682. + } else {
  14683. + dev_err(card->dev, "Can't configure clocks\n");
  14684. + return err;
  14685. + }
  14686. + }
  14687. +
  14688. + rate = clk_get_rate(machine->util_data.clk_cdev1);
  14689. + err = snd_soc_dai_set_pll(codec_dai, 0, RT5671_PLL1_S_MCLK,
  14690. + rate, 512*srate);
  14691. + if (err < 0) {
  14692. + dev_err(card->dev, "codec_dai pll not set\n");
  14693. + return err;
  14694. + }
  14695. + err = snd_soc_dai_set_sysclk(codec_dai, RT5671_SCLK_S_PLL1,
  14696. + 512*srate, SND_SOC_CLOCK_IN);
  14697. + if (err < 0) {
  14698. + dev_err(card->dev, "codec_dai clock not set\n");
  14699. + return err;
  14700. + }
  14701. +
  14702. + /*for 24 bit audio we support only S24_LE (S24_3LE is not supported)
  14703. + which is rendered on bus in 32 bits packet so consider as 32 bit
  14704. + depth in clock calculations, extra 4 is required by codec,
  14705. + God knows why ?*/
  14706. + if (sample_size == 24)
  14707. + i2sclock = srate * channel * 32 * 4;
  14708. + else
  14709. + i2sclock = 0;
  14710. +
  14711. + err = snd_soc_dai_set_sysclk(cpu_dai, 0,
  14712. + i2sclock, SND_SOC_CLOCK_OUT);
  14713. + if (err < 0) {
  14714. + dev_err(card->dev, "cpu_dai clock not set\n");
  14715. + return err;
  14716. + }
  14717. +
  14718. + return 0;
  14719. +}
  14720. +
  14721. +static int tegra_rt5671_startup(struct snd_pcm_substream *substream)
  14722. +{
  14723. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  14724. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  14725. + struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  14726. +
  14727. + tegra_asoc_utils_tristate_dap(i2s->id, false);
  14728. +
  14729. + return 0;
  14730. +}
  14731. +
  14732. +static void tegra_rt5671_shutdown(struct snd_pcm_substream *substream)
  14733. +{
  14734. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  14735. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  14736. + struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  14737. +
  14738. + tegra_asoc_utils_tristate_dap(i2s->id, true);
  14739. +}
  14740. +
  14741. +static int tegra_rt5671_hw_params(struct snd_pcm_substream *substream,
  14742. + struct snd_pcm_hw_params *params)
  14743. +{
  14744. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  14745. + struct snd_soc_dai *codec_dai = rtd->codec_dai;
  14746. + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  14747. + struct snd_soc_codec *codec = rtd->codec;
  14748. + struct snd_soc_card *card = codec->card;
  14749. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14750. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14751. + int srate, i2s_daifmt, codec_daifmt;
  14752. + int err, sample_size;
  14753. +
  14754. + srate = params_rate(params);
  14755. +
  14756. + i2s_daifmt = SND_SOC_DAIFMT_NB_NF;
  14757. + i2s_daifmt |= pdata->i2s_param[HIFI_CODEC].is_i2s_master ?
  14758. + SND_SOC_DAIFMT_CBS_CFS : SND_SOC_DAIFMT_CBM_CFM;
  14759. +
  14760. + switch (params_format(params)) {
  14761. + case SNDRV_PCM_FORMAT_S8:
  14762. + sample_size = 8;
  14763. + break;
  14764. + case SNDRV_PCM_FORMAT_S16_LE:
  14765. + sample_size = 16;
  14766. + break;
  14767. + case SNDRV_PCM_FORMAT_S24_LE:
  14768. + sample_size = 24;
  14769. + break;
  14770. + case SNDRV_PCM_FORMAT_S32_LE:
  14771. + sample_size = 32;
  14772. + break;
  14773. + default:
  14774. + return -EINVAL;
  14775. + }
  14776. +
  14777. + switch (pdata->i2s_param[HIFI_CODEC].i2s_mode) {
  14778. + case TEGRA_DAIFMT_I2S:
  14779. + i2s_daifmt |= SND_SOC_DAIFMT_I2S;
  14780. + break;
  14781. + case TEGRA_DAIFMT_DSP_A:
  14782. + i2s_daifmt |= SND_SOC_DAIFMT_DSP_A;
  14783. + break;
  14784. + case TEGRA_DAIFMT_DSP_B:
  14785. + i2s_daifmt |= SND_SOC_DAIFMT_DSP_B;
  14786. + break;
  14787. + case TEGRA_DAIFMT_LEFT_J:
  14788. + i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J;
  14789. + break;
  14790. + case TEGRA_DAIFMT_RIGHT_J:
  14791. + i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J;
  14792. + break;
  14793. + default:
  14794. + dev_err(card->dev, "Can't configure i2s format\n");
  14795. + return -EINVAL;
  14796. + }
  14797. +
  14798. + err = tegra_rt5671_set_clock(rtd, sample_size, params_channels(params), srate);
  14799. + if (err < 0) {
  14800. + dev_err(card->dev, "Can't configure clocks\n");
  14801. + return err;
  14802. + }
  14803. +
  14804. + tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
  14805. +
  14806. + codec_daifmt = i2s_daifmt;
  14807. +
  14808. + /*invert the codec bclk polarity when codec is master
  14809. + in DSP mode this is done to match with the negative
  14810. + edge settings of tegra i2s*/
  14811. + if (((i2s_daifmt & SND_SOC_DAIFMT_FORMAT_MASK)
  14812. + == SND_SOC_DAIFMT_DSP_A) &&
  14813. + ((i2s_daifmt & SND_SOC_DAIFMT_MASTER_MASK)
  14814. + == SND_SOC_DAIFMT_CBM_CFM)) {
  14815. + codec_daifmt &= ~(SND_SOC_DAIFMT_INV_MASK);
  14816. + codec_daifmt |= SND_SOC_DAIFMT_IB_NF;
  14817. + }
  14818. +
  14819. + err = snd_soc_dai_set_fmt(codec_dai, codec_daifmt);
  14820. + if (err < 0) {
  14821. + dev_err(card->dev, "codec_dai fmt not set\n");
  14822. + return err;
  14823. + }
  14824. +
  14825. + err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt);
  14826. + if (err < 0) {
  14827. + dev_err(card->dev, "cpu_dai fmt not set\n");
  14828. + return err;
  14829. + }
  14830. +
  14831. + return 0;
  14832. +}
  14833. +
  14834. +static int tegra_hw_free(struct snd_pcm_substream *substream)
  14835. +{
  14836. + struct snd_soc_pcm_runtime *rtd = substream->private_data;
  14837. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(rtd->card);
  14838. +
  14839. + tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
  14840. +
  14841. + return 0;
  14842. +}
  14843. +
  14844. +static struct snd_soc_ops tegra_rt5671_ops = {
  14845. + .hw_params = tegra_rt5671_hw_params,
  14846. + .hw_free = tegra_hw_free,
  14847. + .startup = tegra_rt5671_startup,
  14848. + .shutdown = tegra_rt5671_shutdown,
  14849. +};
  14850. +
  14851. +static int tegra_rt5671_event_int_spk(struct snd_soc_dapm_widget *w,
  14852. + struct snd_kcontrol *k, int event)
  14853. +{
  14854. + struct snd_soc_dapm_context *dapm = w->dapm;
  14855. + struct snd_soc_card *card = dapm->card;
  14856. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14857. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14858. + int ret;
  14859. +
  14860. + if (machine->spk_reg) {
  14861. + if (SND_SOC_DAPM_EVENT_ON(event))
  14862. + ret = regulator_enable(machine->spk_reg);
  14863. + else
  14864. + regulator_disable(machine->spk_reg);
  14865. + }
  14866. +
  14867. + if (!(machine->gpio_requested & GPIO_SPKR_EN))
  14868. + return 0;
  14869. +
  14870. + gpio_set_value_cansleep(pdata->gpio_spkr_en,
  14871. + !!SND_SOC_DAPM_EVENT_ON(event));
  14872. +
  14873. + return 0;
  14874. +}
  14875. +
  14876. +static int tegra_rt5671_event_hp(struct snd_soc_dapm_widget *w,
  14877. + struct snd_kcontrol *k, int event)
  14878. +{
  14879. + struct snd_soc_dapm_context *dapm = w->dapm;
  14880. + struct snd_soc_card *card = dapm->card;
  14881. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14882. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14883. +
  14884. + if (!(machine->gpio_requested & GPIO_HP_MUTE))
  14885. + return 0;
  14886. +
  14887. + gpio_set_value_cansleep(pdata->gpio_hp_mute,
  14888. + SND_SOC_DAPM_EVENT_ON(event));
  14889. +
  14890. + return 0;
  14891. +}
  14892. +
  14893. +static int tegra_rt5671_event_int_mic(struct snd_soc_dapm_widget *w,
  14894. + struct snd_kcontrol *k, int event)
  14895. +{
  14896. + struct snd_soc_dapm_context *dapm = w->dapm;
  14897. + struct snd_soc_card *card = dapm->card;
  14898. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14899. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14900. + int ret;
  14901. +
  14902. + if (machine->dmic_reg) {
  14903. + if (SND_SOC_DAPM_EVENT_ON(event))
  14904. + ret = regulator_enable(machine->dmic_reg);
  14905. + else
  14906. + regulator_disable(machine->dmic_reg);
  14907. + }
  14908. +
  14909. + if (!(machine->gpio_requested & GPIO_INT_MIC_EN))
  14910. + return 0;
  14911. +
  14912. + gpio_set_value_cansleep(pdata->gpio_int_mic_en,
  14913. + !!SND_SOC_DAPM_EVENT_ON(event));
  14914. +
  14915. + return 0;
  14916. +}
  14917. +
  14918. +static int tegra_rt5671_event_ext_mic(struct snd_soc_dapm_widget *w,
  14919. + struct snd_kcontrol *k, int event)
  14920. +{
  14921. + struct snd_soc_dapm_context *dapm = w->dapm;
  14922. + struct snd_soc_card *card = dapm->card;
  14923. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14924. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14925. +
  14926. + if (!(machine->gpio_requested & GPIO_EXT_MIC_EN))
  14927. + return 0;
  14928. +
  14929. + gpio_set_value_cansleep(pdata->gpio_ext_mic_en,
  14930. + !SND_SOC_DAPM_EVENT_ON(event));
  14931. +
  14932. + return 0;
  14933. +}
  14934. +
  14935. +static const struct snd_soc_dapm_widget ardbeg_dapm_widgets[] = {
  14936. + SND_SOC_DAPM_SPK("Int Left Spk", tegra_rt5671_event_int_spk),
  14937. + SND_SOC_DAPM_SPK("Int Right Spk", tegra_rt5671_event_int_spk),
  14938. + SND_SOC_DAPM_HP("Headphone Jack", tegra_rt5671_event_hp),
  14939. + SND_SOC_DAPM_MIC("Mic Jack", tegra_rt5671_event_ext_mic),
  14940. + SND_SOC_DAPM_MIC("Int Mic", tegra_rt5671_event_int_mic),
  14941. + SND_SOC_DAPM_HP("BT Headphone", NULL),
  14942. + SND_SOC_DAPM_MIC("BT Mic", NULL),
  14943. + SND_SOC_DAPM_LINE("FM", NULL),
  14944. +};
  14945. +
  14946. +static const struct snd_soc_dapm_route ardbeg_audio_map[] = {
  14947. + {"Headphone Jack", NULL, "HPOR"},
  14948. + {"Headphone Jack", NULL, "HPOL"},
  14949. + {"IN1P", NULL, "Mic Jack"},
  14950. + {"IN1N", NULL, "Mic Jack"},
  14951. + {"micbias2", NULL, "Int Mic"},
  14952. + {"IN2P", NULL, "micbias2"},
  14953. + {"IN2N", NULL, "micbias2"},
  14954. + {"IN4P", NULL, "micbias2"},
  14955. + {"IN4N", NULL, "micbias2"},
  14956. + {"Int Left Spk", NULL, "Left Spk Playback"},
  14957. + {"Int Right Spk", NULL, "Right Spk Playback"},
  14958. + {"BT Headphone", NULL, "BT Playback"},
  14959. + {"BT Capture", NULL, "BT Mic"},
  14960. + {"FM Capture", NULL, "FM"},
  14961. +};
  14962. +
  14963. +static const struct snd_kcontrol_new ardbeg_controls[] = {
  14964. + SOC_DAPM_PIN_SWITCH("Int Left Spk"),
  14965. + SOC_DAPM_PIN_SWITCH("Int Right Spk"),
  14966. + SOC_DAPM_PIN_SWITCH("Headphone Jack"),
  14967. + SOC_DAPM_PIN_SWITCH("Mic Jack"),
  14968. + SOC_DAPM_PIN_SWITCH("Int Mic"),
  14969. + SOC_DAPM_PIN_SWITCH("BT Headphone"),
  14970. + SOC_DAPM_PIN_SWITCH("BT Mic"),
  14971. + SOC_DAPM_PIN_SWITCH("FM"),
  14972. +};
  14973. +
  14974. +static int tegra_rt5671_init(struct snd_soc_pcm_runtime *rtd)
  14975. +{
  14976. + struct snd_soc_codec *codec = rtd->codec;
  14977. + struct snd_soc_card *card = codec->card;
  14978. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  14979. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  14980. + int ret;
  14981. +
  14982. + if (gpio_is_valid(pdata->gpio_spkr_en)) {
  14983. + ret = gpio_request(pdata->gpio_spkr_en, "spkr_en");
  14984. + if (ret) {
  14985. + dev_err(card->dev, "cannot get spkr_en gpio\n");
  14986. + return ret;
  14987. + }
  14988. + machine->gpio_requested |= GPIO_SPKR_EN;
  14989. +
  14990. + gpio_direction_output(pdata->gpio_spkr_en, 0);
  14991. + }
  14992. +
  14993. + if (gpio_is_valid(pdata->gpio_hp_mute)) {
  14994. + ret = gpio_request(pdata->gpio_hp_mute, "hp_mute");
  14995. + if (ret) {
  14996. + dev_err(card->dev, "cannot get hp_mute gpio\n");
  14997. + return ret;
  14998. + }
  14999. + machine->gpio_requested |= GPIO_HP_MUTE;
  15000. +
  15001. + gpio_direction_output(pdata->gpio_hp_mute, 0);
  15002. + }
  15003. +
  15004. + if (gpio_is_valid(pdata->gpio_int_mic_en)) {
  15005. + ret = gpio_request(pdata->gpio_int_mic_en, "int_mic_en");
  15006. + if (ret) {
  15007. + dev_err(card->dev, "cannot get int_mic_en gpio\n");
  15008. + } else {
  15009. + machine->gpio_requested |= GPIO_INT_MIC_EN;
  15010. +
  15011. + /* Disable int mic; enable signal is active-high */
  15012. + gpio_direction_output(pdata->gpio_int_mic_en, 0);
  15013. + }
  15014. + }
  15015. +
  15016. + if (gpio_is_valid(pdata->gpio_ext_mic_en)) {
  15017. + ret = gpio_request(pdata->gpio_ext_mic_en, "ext_mic_en");
  15018. + if (ret) {
  15019. + dev_err(card->dev, "cannot get ext_mic_en gpio\n");
  15020. + } else {
  15021. + machine->gpio_requested |= GPIO_EXT_MIC_EN;
  15022. +
  15023. + /* Disable ext mic; enable signal is active-low */
  15024. + gpio_direction_output(pdata->gpio_ext_mic_en, 1);
  15025. + }
  15026. + }
  15027. +
  15028. + ret = tegra_asoc_utils_register_ctls(&machine->util_data);
  15029. + if (ret < 0)
  15030. + return ret;
  15031. +
  15032. + ret = tegra_rt5671_set_clock(rtd,
  15033. + pdata->i2s_param[HIFI_CODEC].sample_size,
  15034. + pdata->i2s_param[HIFI_CODEC].channels,
  15035. + pdata->i2s_param[HIFI_CODEC].rate);
  15036. + if (ret < 0)
  15037. + return ret;
  15038. +
  15039. + return 0;
  15040. +}
  15041. +
  15042. +static const struct snd_soc_pcm_stream tegra_rt5671_spk_params = {
  15043. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  15044. + .rate_min = 48000,
  15045. + .rate_max = 48000,
  15046. + .channels_min = 2,
  15047. + .channels_max = 2,
  15048. +
  15049. +};
  15050. +
  15051. +static const struct snd_soc_pcm_stream tegra_rt5671_bt_params = {
  15052. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  15053. + .rate_min = 8000,
  15054. + .rate_max = 8000,
  15055. + .channels_min = 1,
  15056. + .channels_max = 1,
  15057. +
  15058. +};
  15059. +
  15060. +static const struct snd_soc_pcm_stream tegra_rt5671_fm_params = {
  15061. + .formats = SNDRV_PCM_FMTBIT_S16_LE,
  15062. + .rate_min = 48000,
  15063. + .rate_max = 48000,
  15064. + .channels_min = 2,
  15065. + .channels_max = 2,
  15066. +
  15067. +};
  15068. +
  15069. +static struct snd_soc_dai_link tegra_rt5671_dai[NUM_DAI_LINKS] = {
  15070. + [DAI_LINK_HIFI] = {
  15071. + .name = "rt5671",
  15072. + .stream_name = "rt5671 PCM",
  15073. + .codec_name = "rt5671.0-001c",
  15074. + .platform_name = "tegra30-i2s.0",
  15075. + .cpu_dai_name = "tegra30-i2s.0",
  15076. + .codec_dai_name = "rt5671-aif1",
  15077. + .ignore_pmdown_time = 1,
  15078. + .init = tegra_rt5671_init,
  15079. + .ops = &tegra_rt5671_ops,
  15080. + },
  15081. + [DAI_LINK_LEFT_SPK] = {
  15082. + .name = "rt5671 Left Speaker",
  15083. + .stream_name = "rt5671 Left SPK",
  15084. + .codec_name = "tfa98xx.0-0034",
  15085. + .cpu_dai_name = "rt5671-aif2",
  15086. + .codec_dai_name = "tfa98xx-dai",
  15087. + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  15088. + SND_SOC_DAIFMT_CBS_CFS,
  15089. + .params = &tegra_rt5671_spk_params,
  15090. + .ignore_pmdown_time = 1,
  15091. + },
  15092. + [DAI_LINK_RIGHT_SPK] = {
  15093. + .name = "rt5671 Right Speaker",
  15094. + .stream_name = "rt5671 Right SPK",
  15095. + .codec_name = "tfa98xx.0-0037",
  15096. + .cpu_dai_name = "rt5671-aif2",
  15097. + .codec_dai_name = "tfa98xx-dai",
  15098. + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  15099. + SND_SOC_DAIFMT_CBS_CFS,
  15100. + .params = &tegra_rt5671_spk_params,
  15101. + .ignore_pmdown_time = 1,
  15102. + },
  15103. + [DAI_LINK_BTSCO] = {
  15104. + .name = "BT-SCO",
  15105. + .stream_name = "BT SCO PCM",
  15106. + .codec_name = "rt5671.0-001c",
  15107. + .cpu_name = "spdif-dit.1",
  15108. + .codec_dai_name = "rt5671-aif3",
  15109. + .dai_fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF |
  15110. + SND_SOC_DAIFMT_CBM_CFM,
  15111. + .params = &tegra_rt5671_bt_params,
  15112. + .ignore_pmdown_time = 1,
  15113. + },
  15114. +
  15115. + [DAI_LINK_FM] = {
  15116. + .name = "rt5671 FM",
  15117. + .stream_name = "rt5671 FM",
  15118. + .codec_name = "rt5671.0-001c",
  15119. + .cpu_name = "spdif-dit.3",
  15120. + .codec_dai_name = "rt5671-aif4",
  15121. + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  15122. + SND_SOC_DAIFMT_CBM_CFM,
  15123. + .params = &tegra_rt5671_fm_params,
  15124. + .ignore_pmdown_time = 1,
  15125. + },
  15126. +};
  15127. +
  15128. +static int tegra_rt5671_suspend_post(struct snd_soc_card *card)
  15129. +{
  15130. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  15131. + int i, suspend_allowed = 1;
  15132. +
  15133. + /*In Voice Call we ignore suspend..so check for that*/
  15134. + for (i = 0; i < machine->pcard->num_links; i++) {
  15135. + if (machine->pcard->dai_link[i].ignore_suspend) {
  15136. + suspend_allowed = 0;
  15137. + break;
  15138. + }
  15139. + }
  15140. +
  15141. + if (suspend_allowed) {
  15142. + /*This may be required if dapm setbias level is not called in
  15143. + some cases, may be due to a wrong dapm map*/
  15144. + if (machine->clock_enabled) {
  15145. + machine->clock_enabled = 0;
  15146. + tegra_asoc_utils_clk_disable(&machine->util_data);
  15147. + }
  15148. + /*TODO: Disable Audio Regulators*/
  15149. + }
  15150. +
  15151. + return 0;
  15152. +}
  15153. +
  15154. +static int tegra_rt5671_resume_pre(struct snd_soc_card *card)
  15155. +{
  15156. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  15157. + int i, suspend_allowed = 1;
  15158. +
  15159. + /*In Voice Call we ignore suspend..so check for that*/
  15160. + for (i = 0; i < machine->pcard->num_links; i++) {
  15161. + if (machine->pcard->dai_link[i].ignore_suspend) {
  15162. + suspend_allowed = 0;
  15163. + break;
  15164. + }
  15165. + }
  15166. +
  15167. + if (suspend_allowed) {
  15168. + /*This may be required if dapm setbias level is not called in
  15169. + some cases, may be due to a wrong dapm map*/
  15170. + if (!machine->clock_enabled && card->dapm.bias_level != SND_SOC_BIAS_STANDBY &&
  15171. + card->dapm.bias_level != SND_SOC_BIAS_OFF) {
  15172. + machine->clock_enabled = 1;
  15173. + tegra_asoc_utils_clk_enable(&machine->util_data);
  15174. + }
  15175. + /*TODO: Enable Audio Regulators*/
  15176. + }
  15177. +
  15178. + return 0;
  15179. +}
  15180. +
  15181. +static int tegra_rt5671_set_bias_level(struct snd_soc_card *card,
  15182. + struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
  15183. +{
  15184. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  15185. +
  15186. + if (dapm == &card->dapm) {
  15187. + if (level != SND_SOC_BIAS_STANDBY &&
  15188. + level != SND_SOC_BIAS_OFF && (!machine->clock_enabled)) {
  15189. + machine->clock_enabled = 1;
  15190. + tegra_asoc_utils_clk_enable(&machine->util_data);
  15191. + }
  15192. + dapm->bias_level = level;
  15193. + }
  15194. +
  15195. + return 0;
  15196. +}
  15197. +
  15198. +static int tegra_rt5671_set_bias_level_post(struct snd_soc_card *card,
  15199. + struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
  15200. +{
  15201. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  15202. +
  15203. + if (dapm == &card->dapm) {
  15204. + if ((level == SND_SOC_BIAS_STANDBY ||
  15205. + level == SND_SOC_BIAS_OFF) && machine->clock_enabled) {
  15206. + machine->clock_enabled = 0;
  15207. + tegra_asoc_utils_clk_disable(&machine->util_data);
  15208. + }
  15209. + dapm->bias_level = level;
  15210. + }
  15211. +
  15212. + return 0 ;
  15213. +}
  15214. +
  15215. +static struct snd_soc_codec_conf tegra_rt5671_conf[] = {
  15216. + {
  15217. + .dev_name = "tfa98xx.0-0034",
  15218. + .name_prefix = "Left Spk",
  15219. + },
  15220. + {
  15221. + .dev_name = "tfa98xx.0-0037",
  15222. + .name_prefix = "Right Spk",
  15223. + },
  15224. + {
  15225. + .dev_name = "spdif-dit.1",
  15226. + .name_prefix = "BT",
  15227. + },
  15228. + {
  15229. + .dev_name = "spdif-dit.3",
  15230. + .name_prefix = "FM",
  15231. + },
  15232. +};
  15233. +
  15234. +static struct snd_soc_card snd_soc_tegra_rt5671 = {
  15235. + .name = "tegra-rt5671",
  15236. + .owner = THIS_MODULE,
  15237. + .dai_link = tegra_rt5671_dai,
  15238. + .num_links = ARRAY_SIZE(tegra_rt5671_dai),
  15239. + .codec_conf = tegra_rt5671_conf,
  15240. + .num_configs = ARRAY_SIZE(tegra_rt5671_conf),
  15241. + .suspend_post = tegra_rt5671_suspend_post,
  15242. + .resume_pre = tegra_rt5671_resume_pre,
  15243. + .set_bias_level = tegra_rt5671_set_bias_level,
  15244. + .set_bias_level_post = tegra_rt5671_set_bias_level_post,
  15245. + .controls = ardbeg_controls,
  15246. + .num_controls = ARRAY_SIZE(ardbeg_controls),
  15247. + .dapm_widgets = ardbeg_dapm_widgets,
  15248. + .num_dapm_widgets = ARRAY_SIZE(ardbeg_dapm_widgets),
  15249. + .dapm_routes = ardbeg_audio_map,
  15250. + .num_dapm_routes = ARRAY_SIZE(ardbeg_audio_map),
  15251. + .fully_routed = true,
  15252. +};
  15253. +
  15254. +static int tegra_rt5671_driver_probe(struct platform_device *pdev)
  15255. +{
  15256. + struct snd_soc_card *card = &snd_soc_tegra_rt5671;
  15257. + struct device_node *np = pdev->dev.of_node;
  15258. + struct tegra_rt5671 *machine;
  15259. + struct tegra_asoc_platform_data *pdata = NULL;
  15260. + int ret;
  15261. + int codec_id;
  15262. + u32 val32[7];
  15263. +
  15264. + if (!pdev->dev.platform_data && !pdev->dev.of_node) {
  15265. + dev_err(&pdev->dev, "No platform data supplied\n");
  15266. + return -EINVAL;
  15267. + }
  15268. + if (pdev->dev.platform_data) {
  15269. + pdata = pdev->dev.platform_data;
  15270. + } else if (np) {
  15271. + pdata = kzalloc(sizeof(struct tegra_asoc_platform_data),
  15272. + GFP_KERNEL);
  15273. + if (!pdata) {
  15274. + dev_err(&pdev->dev, "Can't allocate tegra_asoc_platform_data struct\n");
  15275. + return -ENOMEM;
  15276. + }
  15277. +
  15278. + of_property_read_string(np, "nvidia,codec_name",
  15279. + &pdata->codec_name);
  15280. +
  15281. + of_property_read_string(np, "nvidia,codec_dai_name",
  15282. + &pdata->codec_dai_name);
  15283. +
  15284. + pdata->gpio_ldo1_en = of_get_named_gpio(np,
  15285. + "nvidia,ldo-gpios", 0);
  15286. + if (pdata->gpio_ldo1_en < 0)
  15287. + dev_warn(&pdev->dev, "Failed to get LDO_EN GPIO\n");
  15288. +
  15289. + pdata->gpio_hp_det = of_get_named_gpio(np,
  15290. + "nvidia,hp-det-gpios", 0);
  15291. + if (pdata->gpio_hp_det < 0)
  15292. + dev_warn(&pdev->dev, "Failed to get HP Det GPIO\n");
  15293. +
  15294. + pdata->gpio_codec1 = pdata->gpio_codec2 = pdata->gpio_codec3 =
  15295. + pdata->gpio_spkr_en = pdata->gpio_hp_mute =
  15296. + pdata->gpio_int_mic_en = pdata->gpio_ext_mic_en = -1;
  15297. +
  15298. + of_property_read_u32_array(np, "nvidia,i2s-param-hifi", val32,
  15299. + ARRAY_SIZE(val32));
  15300. + pdata->i2s_param[HIFI_CODEC].audio_port_id = (int)val32[0];
  15301. + pdata->i2s_param[HIFI_CODEC].is_i2s_master = (int)val32[1];
  15302. + pdata->i2s_param[HIFI_CODEC].i2s_mode = (int)val32[2];
  15303. + }
  15304. +
  15305. + if (!pdata) {
  15306. + dev_err(&pdev->dev, "No platform data supplied\n");
  15307. + return -EINVAL;
  15308. + }
  15309. +
  15310. + if (pdata->codec_name)
  15311. + card->dai_link->codec_name = pdata->codec_name;
  15312. +
  15313. + if (pdata->codec_dai_name)
  15314. + card->dai_link->codec_dai_name = pdata->codec_dai_name;
  15315. +
  15316. + machine = kzalloc(sizeof(struct tegra_rt5671), GFP_KERNEL);
  15317. + if (!machine) {
  15318. + dev_err(&pdev->dev, "Can't allocate tegra_rt5671 struct\n");
  15319. + if (np)
  15320. + kfree(pdata);
  15321. + return -ENOMEM;
  15322. + }
  15323. +
  15324. + if (gpio_is_valid(pdata->gpio_ldo1_en)) {
  15325. + ret = gpio_request(pdata->gpio_ldo1_en, "rt5671");
  15326. + if (ret)
  15327. + dev_err(&pdev->dev, "Fail gpio_request AUDIO_LDO1\n");
  15328. +
  15329. + ret = gpio_direction_output(pdata->gpio_ldo1_en, 1);
  15330. + if (ret)
  15331. + dev_err(&pdev->dev, "Fail gpio_direction AUDIO_LDO1\n");
  15332. +
  15333. + msleep(200);
  15334. + }
  15335. +
  15336. + machine->pdata = pdata;
  15337. + machine->pcard = card;
  15338. +
  15339. + ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev, card);
  15340. + if (ret)
  15341. + goto err_free_machine;
  15342. + tegra_asoc_utils_clk_disable(&machine->util_data);
  15343. +
  15344. + /*
  15345. + *codec_reg - its a GPIO (in the form of a fixed regulator) that enables
  15346. + *the basic(I2C) power for the codec and must be ON always
  15347. + */
  15348. + if (!gpio_is_valid(pdata->gpio_ldo1_en)) {
  15349. + machine->codec_reg = regulator_get(&pdev->dev, "ldoen");
  15350. + if (IS_ERR(machine->codec_reg))
  15351. + machine->codec_reg = 0;
  15352. + else
  15353. + ret = regulator_enable(machine->codec_reg);
  15354. + }
  15355. +
  15356. + /*
  15357. + *digital_reg - provided the digital power for the codec and must be
  15358. + *ON always
  15359. + */
  15360. + machine->digital_reg = regulator_get(&pdev->dev, "dbvdd");
  15361. + if (IS_ERR(machine->digital_reg))
  15362. + machine->digital_reg = 0;
  15363. + else
  15364. + ret = regulator_enable(machine->digital_reg);
  15365. +
  15366. + /*
  15367. + *analog_reg - provided the analog power for the codec and must be
  15368. + *ON always
  15369. + */
  15370. + machine->analog_reg = regulator_get(&pdev->dev, "avdd");
  15371. + if (IS_ERR(machine->analog_reg))
  15372. + machine->analog_reg = 0;
  15373. + else
  15374. + ret = regulator_enable(machine->analog_reg);
  15375. +
  15376. + /*
  15377. + *mic_reg - provided the micbias power and jack detection power
  15378. + *for the codec and must be ON always
  15379. + */
  15380. + machine->mic_reg = regulator_get(&pdev->dev, "micvdd");
  15381. + if (IS_ERR(machine->mic_reg))
  15382. + machine->mic_reg = 0;
  15383. + else
  15384. + ret = regulator_enable(machine->mic_reg);
  15385. +
  15386. + /*
  15387. + *spk_reg - provided the speaker power and can be turned ON
  15388. + *on need basis, when required
  15389. + */
  15390. + machine->spk_reg = regulator_get(&pdev->dev, "spkvdd");
  15391. + if (IS_ERR(machine->spk_reg))
  15392. + machine->spk_reg = 0;
  15393. + else
  15394. + regulator_disable(machine->spk_reg);
  15395. +
  15396. + /*
  15397. + *dmic_reg - provided the DMIC power and can be turned ON
  15398. + *on need basis, when required
  15399. + */
  15400. + machine->dmic_reg = regulator_get(&pdev->dev, "dmicvdd");
  15401. + if (IS_ERR(machine->dmic_reg))
  15402. + machine->dmic_reg = 0;
  15403. + else
  15404. + regulator_disable(machine->dmic_reg);
  15405. +
  15406. + card->dev = &pdev->dev;
  15407. + platform_set_drvdata(pdev, card);
  15408. + snd_soc_card_set_drvdata(card, machine);
  15409. +
  15410. + codec_id = pdata->i2s_param[HIFI_CODEC].audio_port_id;
  15411. + tegra_rt5671_dai[DAI_LINK_HIFI].cpu_dai_name =
  15412. + tegra_rt5671_i2s_dai_name[codec_id];
  15413. + tegra_rt5671_dai[DAI_LINK_HIFI].platform_name =
  15414. + tegra_rt5671_i2s_dai_name[codec_id];
  15415. +
  15416. + ret = snd_soc_register_card(card);
  15417. + if (ret) {
  15418. + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  15419. + ret);
  15420. + goto err_fini_utils;
  15421. + }
  15422. +
  15423. + if (!card->instantiated) {
  15424. + ret = -ENODEV;
  15425. + dev_err(&pdev->dev, "sound card not instantiated (%d)\n",
  15426. + ret);
  15427. + goto err_unregister_card;
  15428. + }
  15429. +
  15430. + ret = tegra_asoc_utils_set_parent(&machine->util_data,
  15431. + pdata->i2s_param[HIFI_CODEC].is_i2s_master);
  15432. + if (ret) {
  15433. + dev_err(&pdev->dev, "tegra_asoc_utils_set_parent failed (%d)\n",
  15434. + ret);
  15435. + goto err_unregister_card;
  15436. + }
  15437. +
  15438. + return 0;
  15439. +
  15440. +err_unregister_card:
  15441. + snd_soc_unregister_card(card);
  15442. +err_fini_utils:
  15443. + tegra_asoc_utils_fini(&machine->util_data);
  15444. +err_free_machine:
  15445. + if (np)
  15446. + kfree(machine->pdata);
  15447. +
  15448. + kfree(machine);
  15449. +
  15450. + return ret;
  15451. +}
  15452. +
  15453. +static int tegra_rt5671_driver_remove(struct platform_device *pdev)
  15454. +{
  15455. + struct snd_soc_card *card = platform_get_drvdata(pdev);
  15456. + struct tegra_rt5671 *machine = snd_soc_card_get_drvdata(card);
  15457. + struct tegra_asoc_platform_data *pdata = machine->pdata;
  15458. + struct device_node *np = pdev->dev.of_node;
  15459. +
  15460. + if (machine->gpio_requested & GPIO_EXT_MIC_EN)
  15461. + gpio_free(pdata->gpio_ext_mic_en);
  15462. + if (machine->gpio_requested & GPIO_INT_MIC_EN)
  15463. + gpio_free(pdata->gpio_int_mic_en);
  15464. + if (machine->gpio_requested & GPIO_HP_MUTE)
  15465. + gpio_free(pdata->gpio_hp_mute);
  15466. + if (machine->gpio_requested & GPIO_SPKR_EN)
  15467. + gpio_free(pdata->gpio_spkr_en);
  15468. +
  15469. + if (machine->digital_reg)
  15470. + regulator_put(machine->digital_reg);
  15471. + if (machine->analog_reg)
  15472. + regulator_put(machine->analog_reg);
  15473. + if (machine->mic_reg)
  15474. + regulator_put(machine->mic_reg);
  15475. + if (machine->spk_reg)
  15476. + regulator_put(machine->spk_reg);
  15477. + if (machine->dmic_reg)
  15478. + regulator_put(machine->dmic_reg);
  15479. + if (machine->codec_reg)
  15480. + regulator_put(machine->codec_reg);
  15481. +
  15482. + if (gpio_is_valid(pdata->gpio_ldo1_en)) {
  15483. + gpio_set_value(pdata->gpio_ldo1_en, 0);
  15484. + gpio_free(pdata->gpio_ldo1_en);
  15485. + }
  15486. +
  15487. + snd_soc_unregister_card(card);
  15488. +
  15489. + tegra_asoc_utils_fini(&machine->util_data);
  15490. +
  15491. + if (np)
  15492. + kfree(machine->pdata);
  15493. +
  15494. + kfree(machine);
  15495. +
  15496. + return 0;
  15497. +}
  15498. +
  15499. +static const struct of_device_id tegra_rt5671_of_match[] = {
  15500. + { .compatible = "nvidia,tegra-audio-rt5671", },
  15501. + {},
  15502. +};
  15503. +
  15504. +static struct platform_driver tegra_rt5671_driver = {
  15505. + .driver = {
  15506. + .name = DRV_NAME,
  15507. + .owner = THIS_MODULE,
  15508. + .pm = &snd_soc_pm_ops,
  15509. + .of_match_table = tegra_rt5671_of_match,
  15510. + },
  15511. + .probe = tegra_rt5671_driver_probe,
  15512. + .remove = tegra_rt5671_driver_remove,
  15513. +};
  15514. +
  15515. +static int __init tegra_rt5671_modinit(void)
  15516. +{
  15517. + return platform_driver_register(&tegra_rt5671_driver);
  15518. +}
  15519. +module_init(tegra_rt5671_modinit);
  15520. +
  15521. +static void __exit tegra_rt5671_modexit(void)
  15522. +{
  15523. + platform_driver_unregister(&tegra_rt5671_driver);
  15524. +}
  15525. +module_exit(tegra_rt5671_modexit);
  15526. +
  15527. +MODULE_AUTHOR("Nikesh Oswal <noswal@nvidia.com>");
  15528. +MODULE_DESCRIPTION("Tegra+rt5671 machine ASoC driver");
  15529. +MODULE_LICENSE("GPL");
  15530. +MODULE_ALIAS("platform:" DRV_NAME);
  15531. --
  15532. 2.7.4
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