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BGB Low-Cost FPU SIMD for RISC-V

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Oct 16th, 2024
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  1. BGB Low-Cost FPU-SIMD Extension for RISC-V:
  2. * Goal: Cheap FP-SIMD ISA.
  3. ** Will aim to be cheaper to implement than V.
  4. * Will mostly reuse the FPU extensions (F, D, Zfh) as a base.
  5. ** This will primarily modify the semantics of the existing instructions.
  6. ** A goal is to remain fully backwards compatible with F and D.
  7.  
  8. General:
  9. * Will use F0..F31 for FP-SIMD Vectors.
  10. ** These registers will remain 64-bit.
  11. * FADD.S / FSUB.S / FMUL.S will be reused.
  12. ** Essentially, FADD.S and PADD.S will be considered equivalent.
  13. ** They will differ mostly in their canonical results for the high bits.
  14. * Basic case need only assume 64 bit vectors.
  15. ** Support for 128 bit vectors will be considered optional.
  16.  
  17.  
  18. Canonical FPU scalar S and H ops will fill the high order bits with all 1s, resulting in NaN values. This extension will change the behavior, such that the high order bits will contain additional floating point elements when not holding NaNs.
  19.  
  20. Ops may be NaN preserving:
  21. * If the high input is a NaN, the high output should also be NaN.
  22. * FLW and FLH are to produce NaN extended results.
  23. * Some operations may differentiate behavior based on high-order NaN.
  24. ** The high NaN on the input will separate FADD.S from PADD.S.
  25. ** Though, in many cases, this distinction will be largely irrelevant.
  26.  
  27.  
  28. The type bits for floating point operations will be understood as:
  29. * 00: 2x Binary32
  30. * 01: 1x Binary64
  31. * 10: 4x Binary16
  32. * 11: Binary128 (Reserved)
  33.  
  34. Optionally, the rounding mode may also signal an additional vector size:
  35. * 000=RNE, 001=RTZ , 010=RDN , 011=RUP
  36. * 100=RMM, 101=2xRTZ, 110=2xRNE, 111=DYN
  37.  
  38. In the 2xRNE and 2xRTZ cases, the registers will be a 128-bit register pairs.
  39. * Only even numbered register numbers will be allowed.
  40. * These may be N/A if (FLEN==128).
  41. ** If used with (FLEN==128), it may signal a logical 256 bit vector.
  42.  
  43. For the 2x cases, the type will be understood as:
  44. * 00: 4x Binary32
  45. * 01: 2x Binary64
  46. * 10: 8x Binary16 (Optional)
  47. * 11: Binary128 (Reserved)
  48.  
  49.  
  50. If (FLEN==128), the SIMD vectors will be understood as always being nominally 128 bits, and semantics will need to be adjusted as needed to deal with the larger registers.
  51.  
  52. Most of this specification will assume an implementation with (FLEN==64).
  53.  
  54. For sake of definition, one will define:
  55. * 2 element 64-bit vector:
  56. ** (31: 0): X
  57. ** (63:32): Y
  58. * 4 element 64-bit vector:
  59. ** (15: 0): X
  60. ** (31:16): Y
  61. ** (47:32): Z
  62. ** (63:48): W
  63. * 4 element 128-bit vector:
  64. ** F0(31: 0): X
  65. ** F0(63:32): Y
  66. ** F1(31: 0): Z
  67. ** F1(63:32): W
  68.  
  69.  
  70. === FLx / FSx ===
  71.  
  72. * iiiiiii-iiiii-mmmmm-zzz-nnnnn-00-00111 (FP LOAD)
  73. * iiiiiii-iiiii-mmmmm-001-nnnnn-00-00111 FLH Fn, Rm, Disp12_I
  74. * iiiiiii-iiiii-mmmmm-010-nnnnn-00-00111 FLW Fn, Rm, Disp12_I
  75. * iiiiiii-iiiii-mmmmm-011-nnnnn-00-00111 FLD Fn, Rm, Disp12_I
  76.  
  77. * iiiiiii-iiiii-mmmmm-zzz-nnnnn-01-00111 (FP STORE)
  78. * iiiiiii-ttttt-mmmmm-001-iiiii-01-00111 FSH Rm, Disp12_S, Ft
  79. * iiiiiii-ttttt-mmmmm-010-iiiii-01-00111 FSW Rm, Disp12_S, Ft
  80. * iiiiiii-ttttt-mmmmm-011-iiiii-01-00111 FSD Rm, Disp12_S, Ft
  81.  
  82. The FLH and FLW instructions will load 16 and 32 bits, filling the high order bits with all ones.
  83.  
  84. FLD will load 64 bits.
  85.  
  86. FSH, FSW, and FSD will store 16, 32 or 64 bits.
  87.  
  88. A pair of FLD or FSD operations may be used to load or store a 128-bit vector with freeform alignment.
  89.  
  90. These operations will be understood to load or store the raw bits given in the register, and may not make assumptions regarding the semantic contents of said registers.
  91.  
  92.  
  93. === FLX and FSX (FLEN==64) ===
  94.  
  95. * iiiiiii-iiiii-mmmmm-100-nnnnn-00-00111 FLX XFn, Rm, Disp12_I
  96. * iiiiiii-ttttt-mmmmm-100-iiiii-01-00111 FSX Rm, Disp12_S, XFt
  97.  
  98. FLX and FSX will be optional.
  99.  
  100. These will be N/E if (FLEN==128), in which case they will map to the FLQ and FSQ instructions (other encodings are not available as the V extension ate all of them).
  101.  
  102.  
  103. If supported, FLX will use the same encoding as FLQ, but will load a 128-bit register pair with 64-bit FPRs. This will be mostly equivalent to a pair of FLD instructions, but may impose an alignment, and only even register numbers are allowed.
  104.  
  105. FSX is optional and will store 128 bits.
  106.  
  107. The FLX and FSX instructions will have a required minimum alignment of 8 bytes.
  108.  
  109.  
  110. === PADD/PSUB/PMUL ===
  111.  
  112. * 0000000-ttttt-mmmmm-rrr-nnnnn-10-10011 PADD.S Fn, Fm, Ft
  113. * 0000100-ttttt-mmmmm-rrr-nnnnn-10-10011 PSUB.S Fn, Fm, Ft
  114. * 0001000-ttttt-mmmmm-rrr-nnnnn-10-10011 PMUL.S Fn, Fm, Ft
  115.  
  116. * 0000010-ttttt-mmmmm-rrr-nnnnn-10-10011 PADD.H Fn, Fm, Ft
  117. * 0000110-ttttt-mmmmm-rrr-nnnnn-10-10011 PSUB.H Fn, Fm, Ft
  118. * 0001010-ttttt-mmmmm-rrr-nnnnn-10-10011 PMUL.H Fn, Fm, Ft
  119.  
  120. Perform a SIMD vector operation.
  121.  
  122. These will use the same encodings as the scalar operations and will alias with them. The distinction between the scalar and simd operations will be based primarily on how they are used.
  123.  
  124. The operation will be performed pairwise between each element:
  125. * { AX, AY } + { BX, BY } => { AX + BX, AY + BY }
  126. * { AX, AY } - { BX, BY } => { AX - BX, AY - BY }
  127. * { AX, AY } * { BX, BY } => { AX * BX, AY * BY }
  128.  
  129.  
  130. === PDIV ===
  131.  
  132. * 0001100-ttttt-mmmmm-rrr-nnnnn-10-10011 PDIV.S Fn, Fm, Ft
  133. * 0001110-ttttt-mmmmm-rrr-nnnnn-10-10011 PDIV.H Fn, Fm, Ft
  134.  
  135. Note that PDIV may potentially be slow.
  136.  
  137.  
  138. The existence of SIMD PDIV operators may be considered semi-optional.
  139. * An implementation may perform a scalar FDIV if the high values are NaN.
  140. * An implementation may trap and emulate if the high values are not NaN.
  141.  
  142. On an implementation with unknown PDIV performance, it may be preferable to fake it manually using Newton-Raphson.
  143.  
  144. The implementation specifics of any traps or emulation are outside the scope of this spec, but it may make sense for software to be able to assume that it exists, even if it is slow.
  145.  
  146.  
  147. === PADDX/PSUBX/PMULX (Optional) ===
  148.  
  149. * 0000000-ttttt-mmmmm-rrr-nnnnn-10-10011 PADDX.S XFn, XFm, XFt
  150. * 0000100-ttttt-mmmmm-rrr-nnnnn-10-10011 PSUBX.S XFn, XFm, XFt
  151. * 0001000-ttttt-mmmmm-rrr-nnnnn-10-10011 PMULX.S XFn, XFm, XFt
  152.  
  153. * 0000001-ttttt-mmmmm-rrr-nnnnn-10-10011 PADDX.D XFn, XFm, XFt
  154. * 0000101-ttttt-mmmmm-rrr-nnnnn-10-10011 PSUBX.D XFn, XFm, XFt
  155. * 0001001-ttttt-mmmmm-rrr-nnnnn-10-10011 PMULX.D XFn, XFm, XFt
  156.  
  157. * 0000010-ttttt-mmmmm-rrr-nnnnn-10-10011 PADDX.H XFn, XFm, XFt //1
  158. * 0000110-ttttt-mmmmm-rrr-nnnnn-10-10011 PSUBX.H XFn, XFm, XFt
  159. * 0001010-ttttt-mmmmm-rrr-nnnnn-10-10011 PMULX.H XFn, XFm, XFt
  160.  
  161.  
  162. These will be encoded by setting the rounding mode to 101 or 110.
  163.  
  164. In this case, the vector will be a 128-bit register pair.
  165. Only even register numbers will be valid.
  166.  
  167.  
  168. 1: Note that the Binary16 operations meed not be supported if the implementation does not support 8 element vectors, even if it does otherwise support 128-bit operations.
  169.  
  170.  
  171. === PDIVX ===
  172.  
  173. * 0001100-ttttt-mmmmm-rrr-nnnnn-10-10011 PDIVX.S XFn, XFm, XFt
  174. * 0001101-ttttt-mmmmm-rrr-nnnnn-10-10011 PDIVX.D XFn, XFm, XFt
  175. * 0001110-ttttt-mmmmm-rrr-nnnnn-10-10011 PDIVX.H XFn, XFm, XFt
  176.  
  177. These will be encoded by setting the rounding mode to 101 or 110, operating on a register pair.
  178.  
  179. Similarly, the existence of SIMD PDIV operators may be considered as optional.
  180.  
  181.  
  182. === FSGNJ / FSGNJN / FSGNJX ===
  183.  
  184. * 0010000-ttttt-mmmmm-000-nnnnn-10-10011 PSGNJ.S Fn, Fm, Ft
  185. * 0010000-ttttt-mmmmm-001-nnnnn-10-10011 PSGNJN.S Fn, Fm, Ft
  186. * 0010000-ttttt-mmmmm-010-nnnnn-10-10011 PSGNJX.S Fn, Fm, Ft
  187.  
  188. * 0010001-ttttt-mmmmm-000-nnnnn-10-10011 FSGNJ.D Fn, Fm, Ft
  189. * 0010001-ttttt-mmmmm-001-nnnnn-10-10011 FSGNJN.D Fn, Fm, Ft
  190. * 0010001-ttttt-mmmmm-010-nnnnn-10-10011 FSGNJX.D Fn, Fm, Ft
  191.  
  192. * 0010010-ttttt-mmmmm-000-nnnnn-10-10011 PSGNJ.H Fn, Fm, Ft
  193. * 0010010-ttttt-mmmmm-001-nnnnn-10-10011 PSGNJN.H Fn, Fm, Ft
  194. * 0010010-ttttt-mmmmm-010-nnnnn-10-10011 PSGNJX.H Fn, Fm, Ft
  195.  
  196. These copy the value bits from Fm, with the sign bits copied from Ft.
  197. * FSGNJ: Copies sign bit directly.
  198. * FSGNJN: Inverts the sign bit from the source.
  199. * FSGNJX: Takes the XOR of the sign bits.
  200.  
  201. Where:
  202. * The D form only modifies bit 63.
  203. * The F form modifies 63 and 31.
  204. * The H form modifies 63, 47, 31, and 15.
  205.  
  206.  
  207. === FLE / FLT / FEQ ===
  208.  
  209. These instructions will not be modified, and as such will only apply to the low order element of each vector.
  210.  
  211.  
  212. === PMIN / PMAX ===
  213.  
  214. * 0010100-ttttt-mmmmm-000-nnnnn-10-10011 PMIN.S Fn, Fm, Ft
  215. * 0010100-ttttt-mmmmm-001-nnnnn-10-10011 PMAX.S Fn, Fm, Ft
  216.  
  217. * 0010110-ttttt-mmmmm-000-nnnnn-10-10011 PMIN.H Fn, Fm, Ft
  218. * 0010110-ttttt-mmmmm-001-nnnnn-10-10011 PMAX.H Fn, Fm, Ft
  219.  
  220. Select the minimum and maximum of each element.
  221. These will lack 128-bit equivalents.
  222.  
  223.  
  224. === Pack Operations (Possible) ===
  225.  
  226. * 0010000-ttttt-mmmmm-100-nnnnn-10-10011 ? FPKBB.H Fn, Fm, Ft
  227. * 0010000-ttttt-mmmmm-101-nnnnn-10-10011 ? FPKBT.H Fn, Fm, Ft
  228. * 0010000-ttttt-mmmmm-110-nnnnn-10-10011 ? FPKTB.H Fn, Fm, Ft
  229. * 0010000-ttttt-mmmmm-111-nnnnn-10-10011 ? FPKTT.H Fn, Fm, Ft
  230.  
  231. * 0010001-ttttt-mmmmm-100-nnnnn-10-10011 ? FPKBB.S Fn, Fm, Ft
  232. * 0010001-ttttt-mmmmm-101-nnnnn-10-10011 ? FPKBT.S Fn, Fm, Ft
  233. * 0010001-ttttt-mmmmm-110-nnnnn-10-10011 ? FPKTB.S Fn, Fm, Ft
  234. * 0010001-ttttt-mmmmm-111-nnnnn-10-10011 ? FPKTT.S Fn, Fm, Ft
  235.  
  236. These will compose a value by selecting values from a pair of registers.
  237. * BB: Select the low order value from both registers.
  238. * BT: Select the low order value from Fm, high order from Ft.
  239. * TB: Select the high order value from Fm, low order from Ft.
  240. * TT: Select the high order value from both registers.
  241.  
  242. The new register will be composed by putting selected the value from Fm into the high-order bits of the output, and the value from Ft into the low order bits.
  243.  
  244. For S, the selection size will be 32 bits from each register, producing a 64 bit result.
  245.  
  246. For H, the selection will be 16 bits, selecting (15:0) or (31:16) from each register, and producing a result in the low 32 bits. The high 32 bits will be filled with zeroes.
  247.  
  248.  
  249.  
  250. === Conversion Ops ===
  251.  
  252. * 0100000-00001-mmmmm-rrr-nnnnn-10-10011 FCVT.S.D Fn, Fm
  253. * 0100001-00000-mmmmm-rrr-nnnnn-10-10011 FCVT.D.S Fn, Fm
  254.  
  255. * 0100000-00010-mmmmm-rrr-nnnnn-10-10011 PCVT.S.H Fn, Fm
  256. * 0100010-00000-mmmmm-rrr-nnnnn-10-10011 PCVT.H.S Fn, Fm
  257.  
  258. * 0100001-00010-mmmmm-rrr-nnnnn-10-10011 FCVT.D.H Fn, Fm
  259. * 0100010-00001-mmmmm-rrr-nnnnn-10-10011 FCVT.H.D Fn, Fm
  260.  
  261. * 0100000-00110-mmmmm-rrr-nnnnn-10-10011 PCVT.S.BF16 Fn, Fm
  262. * 0100010-01000-mmmmm-rrr-nnnnn-10-10011 PCVT.BF16.S Fn, Fm
  263.  
  264. * 0100001-00110-mmmmm-rrr-nnnnn-10-10011 FCVT.D.BF16 Fn, Fm
  265. * 0100010-01001-mmmmm-rrr-nnnnn-10-10011 FCVT.BF16.D Fn, Fm
  266.  
  267. * 0100000-01010-mmmmm-rrr-nnnnn-10-10011 PCVTHI.S.H Fn, Fm
  268. * 0100000-01110-mmmmm-rrr-nnnnn-10-10011 PCVTHI.S.BF16 Fn, Fm
  269.  
  270.  
  271. * 0100000-00010-mmmmm-rrr-nnnnn-10-10011 PCVTX.S.H XFn, Fm //Rm=2X
  272. * 0100010-00000-mmmmm-rrr-nnnnn-10-10011 PCVTX.H.S Fn, XFm //Rm=2X
  273.  
  274. * 0100000-00110-mmmmm-rrr-nnnnn-10-10011 PCVTX.S.BF16 XFn, Fm //Rm=2X
  275. * 0100010-01000-mmmmm-rrr-nnnnn-10-10011 PCVTX.BF16.S Fn, XFm //Rm=2X
  276.  
  277. Convert between floating point formats.
  278.  
  279. Here:
  280. * FCVT will convert a single scalar value.
  281. * PCVT will convert a pair of values.
  282. * PCVTHI will convert a pair of values, taken from the high-order bits.
  283.  
  284. Example Conversion of a 4x Binary16 vector to 4x Binary32:
  285. PCVT.S.H F12, F10
  286. PCVTHI.S.H F13, F10
  287. Or:
  288. PCVTX.S.H F12, F10 //4 element conversion
  289.  
  290. Example Conversion of a 4x Binary32 vector to 4x Binary16:
  291. PCVT.H.S F12, F10
  292. PCVT.H.S F13, F11
  293. FPKBB.S F12, F12, F13
  294. Or:
  295. PCVTX.H.S F12, F10 //4 element conversion
  296.  
  297.  
  298.  
  299. === PSQRT ===
  300.  
  301. * 0101100-00000-mmmmm-rrr-nnnnn-10-10011 PSQRT.S Fn, Fm
  302. * 0101101-00000-mmmmm-rrr-nnnnn-10-10011 FSQRT.D Fn, Fm
  303. * 0101110-00000-mmmmm-rrr-nnnnn-10-10011 PSQRT.H Fn, Fm
  304.  
  305. * 0101100-00000-mmmmm-rrr-nnnnn-10-10011 PSQRTX.S XFn, XFm //Rm=2X
  306. * 0101101-00000-mmmmm-rrr-nnnnn-10-10011 PSQRTX.D XFn, XFm //Rm=2X
  307.  
  308. Perform a packed Square Root operation.
  309.  
  310. Packed Square Root is semi-optional, if not supported:
  311. * If high values are NaN, perform a scalar Square Root;
  312. * If high values are not NaN, trap and emulate.
  313.  
  314.  
  315. === Helper Ops (Possible) ===
  316.  
  317. * 1111000-zzzzz-mmmmm-001-nnnnn-10-10011 FOPxx.S Fn, Fm
  318. * 1111001-zzzzz-mmmmm-001-nnnnn-10-10011 FOPxx.D Fn, Fm
  319. * 1111010-zzzzz-mmmmm-001-nnnnn-10-10011 FOPxx.H Fn, Fm
  320.  
  321. Fast Approximate Reciprocal:
  322. * 1111000-00001-mmmmm-001-nnnnn-10-10011 PRCPA.S Fn, Fm
  323. * 1111001-00001-mmmmm-001-nnnnn-10-10011 FRCPA.D Fn, Fm
  324. * 1111010-00001-mmmmm-001-nnnnn-10-10011 PRCPA.H Fn, Fm
  325.  
  326. Fast Approximate Square Root:
  327. * 1111000-00010-mmmmm-001-nnnnn-10-10011 PSQRTA.S Fn, Fm
  328. * 1111001-00010-mmmmm-001-nnnnn-10-10011 FSQRTA.D Fn, Fm
  329. * 1111010-00010-mmmmm-001-nnnnn-10-10011 PSQRTA.H Fn, Fm
  330.  
  331. The RCPA and SQRTA oparations would try to generate a fast approximation of a reciprocal or square root that could then be used to start the Newton-Raphson iteration process.
  332.  
  333.  
  334. === PMADD (Optional) ===
  335.  
  336. * uuuuu00-ttttt-sssss-rrr-nnnnn-10-00011 PMADD.S Fn, Fs, Ft, Fu (F)
  337. * uuuuu10-ttttt-sssss-rrr-nnnnn-10-00011 PMADD.H Fn, Fs, Ft, Fu (H)
  338.  
  339. * uuuuu00-ttttt-sssss-rrr-nnnnn-10-00111 PMSUB.S Fn, Fs, Ft, Fu (F)
  340. * uuuuu10-ttttt-sssss-rrr-nnnnn-10-00111 PMSUB.H Fn, Fs, Ft, Fu (H)
  341.  
  342. * uuuuu00-ttttt-sssss-rrr-nnnnn-10-01011 PNMSUB.S Fn, Fs, Ft, Fu (F)
  343. * uuuuu10-ttttt-sssss-rrr-nnnnn-10-01011 PNMSUB.H Fn, Fs, Ft, Fu (H)
  344.  
  345. * uuuuu00-ttttt-sssss-rrr-nnnnn-10-01111 PNMADD.S Fn, Fs, Ft, Fu (F)
  346. * uuuuu10-ttttt-sssss-rrr-nnnnn-10-01111 PNMADD.H Fn, Fs, Ft, Fu (H)
  347.  
  348.  
  349. If supported, the MADD operations may perform a SIMD MADD.
  350. * These are otherwise equivalent to the FMADD operations.
  351. * If high element is NaN, it is the same as FMADD.
  352.  
  353.  
  354. === Examples ===
  355.  
  356.  
  357. Hypothetical Binary16 SW divider (concept):
  358. __v4h_rcp:
  359. FMV.X.D X10, F10
  360. LI X11, 0x7800780078007800
  361. LI X13, 0x4000400040004000
  362. SUB X12, X11, X10
  363. FMV.D.X F13, X13
  364. FMV.D.X F11, X12
  365. PMUL.H F12, F10, F11
  366. PSUB.H F14, F13, F12
  367. PMUL.H F11, F11, F14
  368. //iterate some more:
  369. PMUL.H F12, F10, F11
  370. PSUB.H F14, F13, F12
  371. PMUL.H F11, F11, F14
  372. PMUL.H F12, F10, F11
  373. PSUB.H F14, F13, F12
  374. PMUL.H F10, F11, F14
  375. RET
  376.  
  377. __v4h_div:
  378. FMV.D F16, F11
  379. FMV.X.D X10, F11
  380. LI X11, 0x7800780078007800
  381. LI X13, 0x4000400040004000
  382. SUB X12, X11, X10
  383. FMV.D.X F13, X13
  384. FMV.D.X F11, X12
  385. PMUL.H F12, F16, F11
  386. PSUB.H F14, F13, F12
  387. PMUL.H F11, F11, F14
  388. //iterate some more:
  389. PMUL.H F12, F16, F11
  390. PSUB.H F14, F13, F12
  391. PMUL.H F11, F11, F14
  392. PMUL.H F12, F16, F11
  393. PSUB.H F14, F13, F12
  394. PMUL.H F11, F11, F14
  395. //final divide:
  396. PMUL.H F10, F10, F11
  397. RET
  398.  
  399. Though, as-is, this will not necessarily give stable convergence (it is often necessary to fudge the values in the first iteration stage to get convergence stable). This can be taken more as a conceptual example.
  400.  
  401. What if we have PRCPA.H:
  402. __v4h_div:
  403. LI X13, 0x4000400040004000
  404. FMV.D F16, F11
  405. FMV.D.X F13, X13
  406. FRPCA.H F11, F11
  407. PMUL.H F12, F16, F11
  408. PSUB.H F14, F13, F12
  409. PMUL.H F11, F11, F14
  410. //iterate some more:
  411. PMUL.H F12, F16, F11
  412. PSUB.H F14, F13, F12
  413. PMUL.H F11, F11, F14
  414. PMUL.H F12, F16, F11
  415. PSUB.H F14, F13, F12
  416. PMUL.H F11, F11, F14
  417. //final divide:
  418. PMUL.H F10, F10, F11
  419. RET
  420.  
  421.  
  422.  
  423.  
  424. === Misc ===
  425.  
  426.  
  427. * 0000100-ttttt-mmmmm-100-nnnnn-01-10011 PACK Rn, Rm, Rt (B)
  428. * 0100100-ttttt-mmmmm-100-nnnnn-01-10011 PACKU Rn, Rm, Rt (B)
  429.  
  430. * 0100iii-iiiii-mmmmm-001-nnnnn-00-11011 PSHUF.W Rn, Rm, Imm8 (BGB)
  431.  
  432.  
  433. * 0000111-ttttt-mmmmm-001-nnnnn-11-10111 PKBB16 Rn, Rm, Rt (P)
  434. * 0001111-ttttt-mmmmm-001-nnnnn-11-10111 PKBT16 Rn, Rm, Rt (P)
  435. * 0010111-ttttt-mmmmm-001-nnnnn-11-10111 PKTB16 Rn, Rm, Rt (P)
  436. * 0011111-ttttt-mmmmm-001-nnnnn-11-10111 PKTT16 Rn, Rm, Rt (P)
  437.  
  438. * 0000111-ttttt-mmmmm-010-nnnnn-11-10111 PKBB32 Rn, Rm, Rt (P)
  439. * 0001111-ttttt-mmmmm-010-nnnnn-11-10111 PKBT32 Rn, Rm, Rt (P)
  440. * 0010111-ttttt-mmmmm-010-nnnnn-11-10111 PKTB32 Rn, Rm, Rt (P)
  441. * 0011111-ttttt-mmmmm-010-nnnnn-11-10111 PKTT32 Rn, Rm, Rt (P)
  442.  
  443.  
Tags: simd RISC-V RV64 RV64G
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