dupa

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-- Company:
-- Engineer:
--
-- Create Date:    09:08:56 12/11/2019
-- Design Name:
-- Module Name:    freqdividerv2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freqdividerv2 is
    Port ( Q : out  STD_LOGIC;
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC);
end freqdividerv2;

architecture Behavioral of freqdividerv2 is

signal mode STD_LOGIC;
signal temp STD_LOGIC;
signal counter unsigned;

component freqdivider
	port (modi, rst, clk: in STD_LOGIC;
	Q: out STD_LOGIC;)
end component



begin

	FD: freqdivider port map(mode=>modi, clk=>clk, rst=>rst, temp=>Q);
	if(rst



end Behavioral;