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  1. -----------------------------------------------------------------------------
  2. Neill Corlett's Yamaha AICA notes
  3. Based on:
  4. - The official AICA spec
  5. - Yamato's aica_v08.txt (yamato@20to4.net)
  6. - Much experimentation
  7. -----------------------------------------------------------------------------
  8.  
  9. LOGARITHMIC VOLUMES
  10.  
  11. Like many Yamaha sound chips, the AICA uses logarithmic volume levels.
  12. Here's how that works:
  13.  
  14. A value of 0 means no attenuation, or full volume. From there, every
  15. increment of a constant amount decreases the volume level by 3dB. Of course,
  16. "3dB" in the literature is just a fancy way of saying "half". And the values
  17. aren't logarithmic at all, but a log/linear approximation.
  18.  
  19. To convert a "logarithmic" attenuation level to a volume multiplier:
  20. 1. You first need to know what increment constitutes a 3dB decrease. We'll
  21. call this I. This is going to always be a power of 2.
  22. 2. Divide (by which I mean shift) the attenuation level by this constant to
  23. get the "exponent", and the remaining lowest bits are the "mantissa".
  24. 3. Invert all bits in the mantissa, then add I to it.
  25. 4. Shift the mantissa left to whatever precision you want.
  26. 5. Shift the mantissa right by the exponent.
  27.  
  28. One of the advantages of logarithmic attenuation levels is that you can apply
  29. several volumes on top of each other by adding them, and this has the same
  30. effect as if you'd multiplied the linear volume levels together. I suspect
  31. this is what's happening, though I haven't tested specifically for it yet.
  32.  
  33. -----------------------------------------------------------------------------
  34.  
  35. RESAMPLING
  36.  
  37. ...appears to be linear.
  38.  
  39. -----------------------------------------------------------------------------
  40.  
  41. AMPLITUDE ENVELOPE CALCULATION
  42.  
  43. This is a typical 4-stage envelope: Attack, Decay, Sustain, Release. The
  44. envelope gets louder during attack, and can only remain the same or quieter
  45. during Decay, Sustain, and Release. (There is no increase sustain mode.)
  46.  
  47. The envelope uses a logarithmic attenuation level where 0 means no
  48. attenuation (full volume) and every increment of 0x40 decreases the volume
  49. by 3dB. The level can range from 0x000 to 0x3BF. Note that if the
  50. attenuation level exceeds 0x3BF _at any time_, the channel will become
  51. inactive and the attenuation level will appear as 0x1FFF.
  52.  
  53. "EFFECTIVE RATE" refers to the following:
  54. - If KRS == 0xF: EFFECTIVE RATE = RATE*2
  55. - If KRS < 0xF: EFFECTIVE RATE = (KRS+OCT+RATE)*2+FNS
  56. (where FNS is bit 9 of SampleRatePitch)
  57. EFFECTIVE RATE is truncated to the range of 0x00-0x3C if necessary.
  58.  
  59. After a key on, the attack attenuation level begins at 0x280. Note that a
  60. key on event is completely ignored unless the channel is either inactive
  61. (attenuation level exceeds 0x3BF) or is presently in the release state.
  62.  
  63. During attack, subtract ((currentlevel >> N)+1) from the current level at
  64. each step, where N is the following:
  65.  
  66. STEP mod 4 is
  67. EFFECTIVE RATE 0 1 2 3
  68. ------------------------------------
  69. 0x30 or less 4 4 4 4
  70. 0x31 3 4 4 4
  71. 0x32 3 4 3 4
  72. 0x33 3 3 3 4
  73. 0x34 3 3 3 3
  74. 0x35 2 3 3 3
  75. 0x36 2 3 2 3
  76. 0x37 2 2 2 3
  77. 0x38 2 2 2 2
  78. 0x39 1 2 2 2
  79. 0x3A 1 2 1 2
  80. 0x3B 1 1 1 2
  81. 0x3C or greater 1 1 1 1
  82.  
  83. Once the envelope level reaches 0, transition to the decay state.
  84.  
  85. Decay is linear in the attenuation level. Simply add the following constants
  86. to the attenuation level at each step:
  87.  
  88. STEP mod 4 is
  89. EFFECTIVE RATE 0 1 2 3
  90. ------------------------------------
  91. 0x30 or less 1 1 1 1
  92. 0x31 2 1 1 1
  93. 0x32 2 1 2 1
  94. 0x33 2 2 2 1
  95. 0x34 2 2 2 2
  96. 0x35 4 2 2 2
  97. 0x36 4 2 4 2
  98. 0x37 4 4 4 2
  99. 0x38 4 4 4 4
  100. 0x39 8 4 4 4
  101. 0x3A 8 4 8 4
  102. 0x3B 8 8 8 4
  103. 0x3C or greater 8 8 8 8
  104.  
  105. The step timing, for both attack and decay, is as follows:
  106.  
  107. EFFECTIVE RATE Step occurs every N samples
  108. --------------------------------------------------
  109. 0x00 Never
  110. 0x01 Never
  111. 0x02 8192, 4096, 4096
  112. 0x03 8192, 4096, 4096, 4096, 4096, 4096, 4096
  113. 0x04 4096
  114. 0x05 4096, 4096, 4096, 2048, 2048
  115. 0x06 (same as 0x02 shifted right by 1)
  116. ... ...
  117. 0x30 and up 2
  118.  
  119. During decay, when the attenuation level reaches the "decay level", defined
  120. as DL << 5, transition to the sustain state.
  121.  
  122. Sustain follows the same formula as decay and continues until either the
  123. envelope attenuation level exceeds 0x3BF, or a key off event occurs.
  124.  
  125. After a key off, transition to the release state. Release also follows the
  126. same formula as decay. When the envelope attenuation level exceeds 0x3BF,
  127. the channel becomes inactive.
  128.  
  129. If "voff" is set, then this envelope is still computed, but the attenuation
  130. has no effect. However, the channel will still end abruptly once the level
  131. exceeds 0x3BF.
  132.  
  133. -----------------------------------------------------------------------------
  134.  
  135. FILTER ENVELOPE CALCULATION
  136.  
  137. Filter envelopes follow the same step timings as amplitude envelopes (key
  138. scaling is also shared between filter and amplitude), and likely the same
  139. step sizes as in the decay phases of amplitude envelopes (based on a few
  140. trials).
  141.  
  142. The only difference is that instead of an attenuation level, it uses a 13-bit
  143. lowpass value.
  144.  
  145. - Start at FLV0
  146. - Attack: Add or subtract the attack step size until you reach FLV1
  147. - Decay: Add or subtract the decay (1) step size until you reach FLV2
  148. - Sustain: Add or subtract the sustain (2) step size until you reach FLV3
  149. - Wait for a key off
  150. - Release: Add or subtract the release step size
  151.  
  152. If "lpoff" is set, then this envelope is still computed, but the filter
  153. itself has no effect.
  154.  
  155. -----------------------------------------------------------------------------
  156.  
  157. LOW FREQUENCY OSCILLATOR (LFO)
  158.  
  159. There are 6 components to the LFO:
  160.  
  161. - The "reset" bit, meaning the LFO phase is zeroed on every sample loop start
  162. - The LFO frequency (0x00-0x1F)
  163. - Pitch modulation waveform type
  164. - Pitch modulation depth
  165. - Amplitude modulation waveform type
  166. - Amplitude modulation depth
  167.  
  168. Here is the LFO period, in samples, for every frequency value:
  169.  
  170. f=0x00:0x3FC00 f=0x08:0x0FC00 f=0x10:0x03C00 f=0x18:0x00C00
  171. f=0x01:0x37C00 f=0x09:0x0BC00 f=0x11:0x03400 f=0x19:0x00A00
  172. f=0x02:0x2FC00 f=0x0A:0x0DC00 f=0x12:0x02C00 f=0x1A:0x00800
  173. f=0x03:0x27C00 f=0x0B:0x09C00 f=0x13:0x02400 f=0x1B:0x00600
  174. f=0x04:0x1FC00 f=0x0C:0x07C00 f=0x14:0x01C00 f=0x1C:0x00400
  175. f=0x05:0x1BC00 f=0x0D:0x06C00 f=0x15:0x01800 f=0x1D:0x00300
  176. f=0x06:0x17C00 f=0x0E:0x05C00 f=0x16:0x01400 f=0x1E:0x00200
  177. f=0x07:0x13C00 f=0x0F:0x04C00 f=0x17:0x01000 f=0x1F:0x00100
  178.  
  179. LFO pitch depth:
  180.  
  181. The pitch can vary by a maximum of plus or minus (base phaseinc)>>(10-d)
  182. d=0: do not apply pitch modulation
  183. d=1: base phaseinc of 0x40000 can sway from 0x3FE00 to 0x40200
  184. ...
  185. d=7: base phaseinc of 0x40000 can sway from 0x38000 to 0x48000
  186.  
  187. LFO pitch waveform:
  188.  
  189. 0: sawtooth, starting in the middle, going higher
  190. 1: square, high pitch for first half, low pitch for second half
  191. 2: triangle, starting in the middle, going higher, much like sin(x)
  192. 3: noise
  193.  
  194. LFO amplitude depth:
  195.  
  196. Amplitude modulation adds positive values to the envelope attenuation, so it
  197. can only make the resulting output softer, not louder.
  198. d=7: can add up to 24dB or 0x200 to envelope attenuation
  199. d=6: can add up to 12dB or 0x100 to envelope attenuation
  200. d=5: can add up to 6dB or 0x080 to envelope attenuation
  201. d=4: can add up to 3dB or 0x040 to envelope attenuation
  202. d=3: can add up to 0x020 to envelope attenuation
  203. d=2: can add up to 0x010 to envelope attenuation
  204. d=1: can add up to 0x008 to envelope attenuation
  205. d=0: do not apply amplitude modulation
  206.  
  207. LFO amplitude waveform:
  208.  
  209. 0: sawtooth, starting at 0 (no attenuation), going up (more attenuation)
  210. 1: square, 0 for first half, max attenuation second half
  211. 2: triangle, starting at 0, going down then up
  212. 3: noise
  213.  
  214. LFO phase resets on every sample loop start if the reset bit is set.
  215. It never resets in any other circumstances (not even on key on).
  216.  
  217. -----------------------------------------------------------------------------
  218.  
  219. RESONANT LOWPASS FILTER
  220.  
  221. If lpoff=0, the channel output is run through a resonant lowpass filter. The
  222. algorithm works like this:
  223.  
  224. out = f * in + (1.0 - f + q) * prev_out - q * prev_prev_out
  225.  
  226. Where f and q are coefficients. Exactly how f and q are computed, I'm still
  227. not 100% sure. I have a fairly good idea for f:
  228.  
  229. f = (((filtervalue & 0xFF) | 0x100) << 4) >> ((filtervalue>>8)^0x1F)
  230.  
  231. Where filtervalue is the filter envelope level, and f becomes a linear value
  232. in the range of 0x0000 (0.0) to 0x1FFF (almost 1.0).
  233.  
  234. I'm less certain about q. For now, I intend to simply use the Q register
  235. value, where 0x00=0.0 and 0x20=1.0 (max is 0x1F).
  236.  
  237. -----------------------------------------------------------------------------
  238.  
  239. ADPCM SAMPLE FORMAT
  240.  
  241. The ADPCM sample format is standard Yamaha ADPCM. It's the same format used
  242. in the YMZ280B.
  243.  
  244. -----------------------------------------------------------------------------
  245.  
  246. REGISTERS
  247.  
  248. The AICA registers are accessible starting at 0x800000 on the ARM7 side and
  249. 0xA0700000 on the SH4 side. Register addresses in this document will usually
  250. refer to an offset from either 0x800000 or 0xA0700000.
  251.  
  252. There are 64 channels and a set of registers associated with each, a set of
  253. common registers, and a set of registers associated with the effects DSP.
  254.  
  255. -----------------------------------------------------------------------------
  256.  
  257. CHANNEL REGISTERS
  258.  
  259. The area at 0x0000-0x1FFF contains the channel registers. There are 32
  260. 32-bit registers for each channel, but only the first 18 are used, and only
  261. the lowest 16 bits have any effect.
  262.  
  263. Channel 0's registers start at 0x0000, channel 1's at 0x0080, and so on.
  264.  
  265. All register writes take effect immediately. NONE of the channel registers
  266. are temporarily stored until key-on (as was the case on the PSX SPU).
  267.  
  268. When you read from a channel register, you'll simply get the last value that
  269. was written to it, EXCEPT for bits which are not saved (always return 0).
  270. These bits are clearly labeled below.
  271.  
  272. -----------------------------------------------------------------------------
  273. 0x00 - PlayControl
  274.  
  275. bit 15 = key on execute (KYONEX) [NOY SAVED, always 0 when read]
  276. Writing a 1 bit here will execute a key on for every channel that
  277. has KYONB=1, and a key off for every channel that has KYONB=0,
  278. simultaneously. There's no way to single out individual
  279. channels. (Though it works out since redundant key on/key off
  280. events are ignored.)
  281. bit 14 = key on bit (KYONB)
  282. Set this to either 1 or 0 to "mark" a channel for key on or off.
  283. bit 13-11 = unused [NOT SAVED, always 0 when read]
  284. bit 10 = noise enable (SSCTL)
  285. 0 means read sample data from RAM, as per usual
  286. 1 means use random data instead of actually reading RAM.
  287. This seems to only affect what bytes are read. If you have the
  288. sample format set to 16-bit, you'll get random 16-bit samples.
  289. If you have the format set to ADPCM, you'll get random ADPCM
  290. samples, but I think they're still run through the ADPCM decoder.
  291. bit 9 = sample loop (LPCTL) 1=enabled, 0=disabled
  292. bit 8-7 = sample format (PCMS)
  293. 0 = 16-bit signed little-endian
  294. 1 = 8-bit signed
  295. 2 = 4-bit Yamaha ADPCM
  296. 3 = prohibited
  297. Actual behavior seems to be "sample data is all zeroes".
  298. bit 6-0 = highest 7 bits of sample start address (SA) (in bytes)
  299.  
  300. -----------------------------------------------------------------------------
  301. 0x04 - SampleAddrLow
  302.  
  303. bit 15-0 = lowest 7 bits of sample start address (SA) (in bytes)
  304.  
  305. -----------------------------------------------------------------------------
  306. 0x08 - LoopStart
  307.  
  308. bit 15-0 = Loop start address (in samples)
  309. Very low values of this may not work depending on the pitch and
  310. loop mode.
  311.  
  312. -----------------------------------------------------------------------------
  313. 0x0C - LoopEnd
  314.  
  315. bit 15-0 = Loop end address (in samples)
  316. If sample looping is disabled, this acts as the total sample size.
  317. Very high values may not work depending on the pitch and loop
  318. mode.
  319. Also, you can't set this to 0xFFFF if you expect the interpolation
  320. to work.
  321.  
  322. -----------------------------------------------------------------------------
  323. 0x10 - AmpEnv1
  324.  
  325. bit 15-11 = sustain rate (D2R) rate, 0x00-0x1F
  326. bit 10-6 = decay rate (D1R), 0x00-0x1F
  327. bit 5 = unused [NOT SAVED, always 0 when read]
  328. bit 4-0 = attack rate (AR), 0x00-0x1F
  329.  
  330. -----------------------------------------------------------------------------
  331. 0x14 - AmpEnv2
  332.  
  333. bit 15 = unused [NOT SAVED, always 0 when read]
  334. bit 14 = link (LPSLNK), 1=on 0=off
  335. If this bit is set, then the envelope transitions to the decay
  336. state when the sample loop start address is exceeded.
  337. bit 13-10 = key rate scaling (KRS), 0x0-0xF
  338. See the amplitude envelope notes for details on this.
  339. 0xF means that all scaling is OFF.
  340. bit 9-5 = decay level (DL), 0x00-0x1F
  341. bit 4-0 = release rate (RR), 0x00-0x1F
  342.  
  343. -----------------------------------------------------------------------------
  344. 0x18 - SampleRatePitch
  345.  
  346. bit 15 = unused [SAVED]
  347. bit 14-11 = octave (OCT), signed value, -0x8 to 0x7
  348. bit 10-0 = FNS
  349.  
  350. This is basically a phase increment value, just computed in a peculiar way.
  351. phaseinc = (FNS ^ 0x400) << ((unsigned OCT value) ^ 0x8)
  352. There's 18 fractional phase bits, so phaseinc=0x40000 is the base frequency,
  353. or 44100Hz.
  354.  
  355. Supposedly if the signed OCT value is 2 or higher, and the sample format is
  356. ADPCM, the actual octave is one higher.
  357.  
  358. -----------------------------------------------------------------------------
  359. 0x1C - LFOControl
  360.  
  361. bit 15 = reset (LFORE) 1=on, 0=off
  362. If set, the LFO phase is reset at the start of EACH SAMPLE LOOP.
  363. bit 14-10 = frequency (LFOF)
  364. bit 9-8 = pitch modulation waveform (PLFOWS)
  365. bit 5-7 = pitch modulation depth (PLFOS)
  366. bit 4-3 = amplitude modulation waveform (ALFOWS)
  367. bit 2-0 = amplitude modulation depth (ALFOS)
  368.  
  369. See the LFO notes for more details.
  370.  
  371. -----------------------------------------------------------------------------
  372. 0x20 - DSPChannelSend
  373.  
  374. bit 15-8 = unused [NOT SAVED, always 0 when read]
  375. bit 7-4 = DSP send level, 0x0-0xF
  376. Scales the output of this channel to one of the effect send buses.
  377. 0xF is full volume (no attenuation), every level beneath that adds
  378. 3dB, and 0x0 means no output.
  379. bit 3-0 = DSP send channel, 0x0-0xF
  380. This affects which DSP MIXS register will receive this channel's
  381. output.
  382. I have verified that bit 19 of MIXS corresponds to bit 15 of a
  383. single 16-bit sample played at the maximum possible volume.
  384.  
  385. -----------------------------------------------------------------------------
  386. 0x24 - DirectPanVolSend
  387.  
  388. bit 15-12 = unused [SAVED]
  389. bit 11-8 = Direct send volume (DISDL), 0x0-0xF
  390. Affects how much of this channel is being sent directly to the
  391. dry output. 0xF is full volume (no attenuation), every level
  392. beneath that adds 3dB, and 0x0 means no output. (I have verified
  393. this.)
  394. bit 7-5 = unused [SAVED]
  395. bit 4-0 = Direct send pan (DIPAN), 0x00-0x1F
  396. 0x00 or 0x10 is center, 0x0F is full right, 0x1F is full left
  397. 0x00-0x0F: each step beyond 0x00 attenuates the left side by 3db
  398. (right side remains at same volume)
  399. 0x10-0x1F: each step beyond 0x10 attenuates the right side by 3db
  400. (left side remains at same volume)
  401.  
  402. -----------------------------------------------------------------------------
  403. 0x28 - LPF1Volume
  404.  
  405. bit 15-8 = constant attenuation (I think this may be TL)
  406. this value *4 seems to be added to the envelope attenuation
  407. (as in, 0x00-0xFF here corresponds to 0x000-0x3FF when referring
  408. to the envelope attenuation)
  409. every 0x10 on the constant attenuation is 3dB
  410. bit 7 = unknown [SAVED]
  411. bit 6 = voff
  412. if this bit is set to 1, the constant attenuation, envelope, and
  413. LFO volumes will not take effect. however, the note will still
  414. end when the envelope level reaches zero in the release state.
  415. bit 5 = lpoff
  416. 1 = turn off lowpass filter.
  417. bit 4-0 = Q, 0x00-0x1F
  418. filter resonance value Q = (0.75*value)-3, from -3 to 20.25 db
  419. 0x1F = 20.25dB
  420. 0x1C = 18dB
  421. 0x18 = 15dB
  422. 0x10 = 9dB
  423. 0x0C = 6dB
  424. 0x08 = 3dB
  425. 0x04 = 0dB
  426. 0x00 = -3dB
  427.  
  428. -----------------------------------------------------------------------------
  429. 0x2C - LPF2
  430.  
  431. bit 15-13 = unused [NOT SAVED, always 0 when read]
  432. bit 12-0 = filterValue0 (FLV0): starting filter frequency
  433. attack start
  434.  
  435. -----------------------------------------------------------------------------
  436. 0x30 - LPF3
  437.  
  438. bit 15-13 = unused [NOT SAVED, always 0 when read]
  439. bit 12-0 = filterValue1 (FLV1): stage 1 filter frequency
  440. decay start time
  441.  
  442. -----------------------------------------------------------------------------
  443. 0x34 - LPF4
  444.  
  445. bit 15-13 = unused [NOT SAVED, always 0 when read]
  446. bit 12-0 = filterValue2 (FLV2): stage 2 filter frequency
  447. sustain start time
  448.  
  449. -----------------------------------------------------------------------------
  450. 0x38 - LPF5
  451.  
  452. bit 15-13 = unused [NOT SAVED, always 0 when read]
  453. bit 12-0 = filterValue3 (FLV3): stage 3 filter frequency
  454. KeyOff time
  455.  
  456. -----------------------------------------------------------------------------
  457. 0x3C - LPF6
  458.  
  459. bit 15-13 = unused [NOT SAVED, always 0 when read]
  460. bit 12-0 = filterValue4 (FLV4): release filter frequency
  461.  
  462. -----------------------------------------------------------------------------
  463. 0x40 - LPF7
  464.  
  465. bit 15-13 = unused [NOT SAVED, always 0 when read]
  466. bit 12-8 = LPF attack rate (FAR), 0x00-0x1F
  467. bit 7-5 = unused [NOT SAVED, always 0 when read]
  468. bit 4-0 = LPF decay rate (FD1R), 0x00-0x1F
  469.  
  470. ----------------------------------------------------------------------------
  471. 0x44 - LPF8
  472.  
  473. bit 15-13 = unused [NOT SAVED, always 0 when read]
  474. bit 12-8 = LPF sustain rate (FD2R), 0x00-0x1F
  475. bit 7-5 = unused [NOT SAVED, always 0 when read]
  476. bit 4-0 = LPF release rate (FRR), 0x00-0x1F
  477.  
  478. -----------------------------------------------------------------------------
  479. 0x48 to 0x7C - unused
  480.  
  481. -----------------------------------------------------------------------------
  482.  
  483. COMMON REGISTERS
  484.  
  485. -----------------------------------------------------------------------------
  486. 0x2000-0x2044 - DSP Output Mixer registers
  487.  
  488. These determine how loudly the DSP effect output channels are played.
  489.  
  490. bit 15-12 = unused
  491. bit 11-8 = Effect output level (EFSDL), 0x0-0xF
  492. 0xF is no attenuation (full volume), and each value below that
  493. increases the attenuation by 3dB.
  494. bit 7-5 = unused
  495. bit 4-0 = Effect output pan (EFPAN), 0x00-0x1F
  496. This works the same as the direct output pan register.
  497.  
  498. The first 16 registers (0x2000-0x203C) correspond to mixer outputs 0-15.
  499. 0x2040 is CDDA output left. 0x2044 is CDDA output right.
  500.  
  501. -----------------------------------------------------------------------------
  502. 0x2800 - MasterVolume
  503.  
  504. bit 15 = MONO (1=mono, 0=stereo)
  505. In mono mode, pan attenuation values do not take effect.
  506. bit 14-10 = unused
  507. bit 9 = MEM8MB (1=8MB memory, 0=2MB memory)
  508. bit 8 = DAC18B (1=use 18-bit DAC, 0=use 16-bit DAC)
  509. bit 7-4 = LSI version (VER)
  510. Read this to get the LSI version of the chip. Should be 1.
  511. bit 3-0 = Master volume (MVOL)
  512. 0xF=no attenuation (full volume)
  513. Every value beneath 0xF decreases the volume by 3dB.
  514.  
  515. Whenever you read this register, the result should be 0x0010.
  516.  
  517. -----------------------------------------------------------------------------
  518. 0x2804 - RingBufferAddress
  519.  
  520. bit 15 = $T (used for LSI testing?)
  521. bit 14-13 = Ring buffer size (RBL)
  522. 0 = 8Kwords
  523. 1 = 16Kwords
  524. 2 = 32Kwords
  525. 3 = 64Kwords (where "word" means 16-bit)
  526. bit 12 = unused
  527. bit 11-0 = Ring buffer pointer (RBP)
  528. This corresponds to bits 22-11 of an actual RAM address.
  529. Each increment of RBP represents 2Kbytes of memory.
  530.  
  531. -----------------------------------------------------------------------------
  532. 0x2808 - MIDIInput
  533.  
  534. bit 15-13 = unused
  535. bit 12 = MIDI Output FIFO is full (MOFUL) 1=yes, 0=no
  536. bit 11 = MIDI Output FIFO is empty (MOEMP) 1=yes, 0=no
  537. bit 10 = MIDI Input FIFO has overflowed (MIOVF) 1=yes, 0=no
  538. bit 9 = MIDI Input FIFO is full (MIFUL) 1=yes, 0=no
  539. bit 8 = MIDI Input FIFO is empty (undocumented!) 1=yes, 0=no
  540. bit 7-0 = MIDI Input Buffer (MIBUF)
  541. Data coming in from the MIDI port in a 4-byte FIFO.
  542.  
  543. Note that when you read this register all at once, the status flags represent
  544. the state of the input FIFO _before_ you read that next byte.
  545.  
  546. -----------------------------------------------------------------------------
  547. 0x280C - ChnInfoReq
  548.  
  549. bit 15 = unused
  550. bit 14 = Amplitude or Filter select (AFSEL)
  551. 0 = we will be monitoring the amplitude envelope
  552. 1 = we will be monitoring the filter envelope
  553. bit 13-8 = Monitor select (MSLC), 0x00-0x3F
  554. Selects a channel to monitor using the monitor regs below.
  555. bit 7-0 = MIDI Output Buffer (MOBUF)
  556. Probably best not to write stuff here under normal circumstances
  557.  
  558. -----------------------------------------------------------------------------
  559. 0x2810 - PlayStatus
  560.  
  561. This register refers to the channel selected by MSLC above.
  562. Also it can refer to either the amplitude or filter envelope, depending on
  563. the AFSEL bit.
  564.  
  565. bit 15 = Loop end flag (LP)
  566. Set to 1 when the sample loop end is reached.
  567. Cleared to 0 upon reading.
  568. bit 14-13 = Current envelope state (SGC)
  569. 0=attack, 1=decay, 2=sustain, 3=release
  570. bit 12-0 = Envelope level (EG)
  571. For amplitude envelope, this is generally in the range of
  572. 0x0000-0x03BF. (0x000 means full volume/no attenuation.)
  573. Any higher attenuation level is returned as 0x1FFF.
  574. For filter envelope, you'll get all 13 bits of the current
  575. lowpass value.
  576.  
  577. (every 0x40 on the envelope attenuation level is 3dB)
  578.  
  579. -----------------------------------------------------------------------------
  580. 0x2814 - PlayPos
  581.  
  582. bit 15-0 = Current sample position from the requested channel (CA)
  583.  
  584. -----------------------------------------------------------------------------
  585. 0x2880 - ?
  586.  
  587. has to do with DMA and other obscure stuff
  588.  
  589. bit 15-9 = DMEA 22:16
  590. bit 8 = unused
  591. bit 7-5 = TSCD 2:0
  592. bit 4 = $T (used for LSI testing?)
  593. bit 3-0 = MRWINH
  594. Setting any of the bits of MRWINH to 1 prohibits sound memory
  595. access from various devices:
  596. bit 3 = main CPU
  597. bit 2 = sound CPU (yes, it will lock up if you set this to 1)
  598. bit 1 = sound samples
  599. bit 0 = effects processor
  600.  
  601. -----------------------------------------------------------------------------
  602. 0x2884 - ?
  603.  
  604. has to do with DMA and other obscure stuff
  605.  
  606. bit 15-1 = DMEA 15:1
  607. bit 0 = unused
  608.  
  609. -----------------------------------------------------------------------------
  610. 0x2888 - ?
  611.  
  612. has to do with DMA and other obscure stuff
  613.  
  614. bit 15 = GA
  615. bit 14-1 = DRGA 14:1
  616. bit 0 = unused
  617.  
  618. -----------------------------------------------------------------------------
  619. 0x288C - ?
  620.  
  621. has to do with DMA and other obscure stuff
  622.  
  623. bit 15 = DI
  624. bit 14-1 = DLG 14:1
  625. bit 0 = EX
  626.  
  627. -----------------------------------------------------------------------------
  628. 0x2890 - TimerAControl
  629.  
  630. bit 15-11 = unused
  631. bit 10-8 = Timer A prescale (TACTL)
  632. 0 = Timer increments every sample
  633. 1 = Timer increments every 2 samples
  634. 2 = Timer increments every 4 samples
  635. 3 = Timer increments every 8 samples
  636. 4 = Timer increments every 16 samples
  637. 5 = Timer increments every 32 samples
  638. 6 = Timer increments every 64 samples
  639. 7 = Timer increments every 128 samples
  640. bit 7-0 = Timer A value (TIMA)
  641. Can be written directly, maybe also read, not sure.
  642. Counts up at the rate specified by TACTL.
  643. When it overflows from 0xFF->0x00, an interrupt occurs.
  644.  
  645. -----------------------------------------------------------------------------
  646. 0x2894 - TimerBControl
  647.  
  648. bit 15-11 = unused
  649. bit 10-8 = Timer B prescale (TBCTL), similar to TACTL
  650. bit 7-0 = Timer B value (TIMB), similar to TIMA
  651.  
  652. -----------------------------------------------------------------------------
  653. 0x2898 - TimerCControl
  654.  
  655. bit 15-11 = unused
  656. bit 10-8 = Timer C prescale (TCCTL), similar to TACTL
  657. bit 7-0 = Timer C value (TIMC), similar to TIMA
  658.  
  659. -----------------------------------------------------------------------------
  660. 0x289C - Sound CPU Interrupt Enable (SCIEB)
  661. 0x28A0 - Sound CPU Interrupt Pending (SCIPD)
  662. 0x28A4 - Sound CPU Interrupt Reset (SCIRE)
  663.  
  664. The following bits apply to all 3 registers:
  665.  
  666. bit 15-11 = unused
  667. bit 10 = One-sample interval interrupt
  668. bit 9 = MIDI output interrupt
  669. bit 8 = Timer C interrupt
  670. bit 7 = Timer B interrupt
  671. bit 6 = Timer A interrupt
  672. bit 5 = CPU interrupt
  673. bit 4 = DMA end interrupt
  674. bit 3 = MIDI input interrupt
  675. bit 2 = reserved
  676. bit 1 = reserved
  677. bit 0 = External interrupt pin (used for SCSI in the devkit)
  678.  
  679. Writing SCIEB determines which of the above interrupts are enabled.
  680. (1=on, 0=off). Reading may also work, not sure.
  681.  
  682. Reading SCIPD tells you which interrupts are pending (have been signaled).
  683. (1=on, 0=off)
  684.  
  685. Writing SCIPD allows you to signal interrupts yourself, but it only works for
  686. bit 5, supposedly. (1=on, 0=off)
  687.  
  688. Writing SCIRE resets (acknowledges) whichever interrupts are set to 1 in the
  689. value you write. Probably meaning it clears the corresponding bits of SCIPD.
  690. Reading this is unlikely to work.
  691.  
  692. -----------------------------------------------------------------------------
  693. 0x28A8 - SCILV0 (usually initialized to 0x18)
  694. 0x28AC - SCILV1 (usually initialized to 0x50)
  695. 0x28B0 - SCILV2 (usually initialized to 0x08)
  696.  
  697. bit 15-8 = unused
  698. bit 7 = refers collectively to bits 7-10 of SCIEB/SCIPD/SCIRE.
  699. bit 6-0 = refers to bits 6-0 of SCIEB/SCIPD/SCIRE.
  700.  
  701. When an interrupt happens, the corresponding bits in SCILV0-2 are what forms
  702. the INTREQ number. For instance:
  703.  
  704. bit 7 6 5 4 3 2 1 0
  705. misc. TimerA SCPU DMA MIDI - - Ext.
  706. --------------------------------------------------
  707. SCILV0 0 0 0 1 1 0 0 0 = 0x18
  708. SCILV1 0 1 0 1 0 0 0 0 = 0x50
  709. SCILV2 0 0 0 0 1 0 0 0 = 0x08
  710. | | |
  711. | | +-----> MIDI INTREQ = 5
  712. | +----------> DMA INTREQ = 3
  713. +------------------------> Timer A INTREQ = 2
  714.  
  715. No, nothing to do with overclocking or burning. ;)
  716.  
  717. -----------------------------------------------------------------------------
  718. 0x28B4 - Main CPU Interrupt Enable (MCIEB)
  719. 0x28B8 - Main CPU Interrupt Pending (MCIPD)
  720. 0x28BC - Main CPU Interrupt Reset (MCIRE)
  721.  
  722. Same as SCIEB/SCIPD/SCIRE, but refers to the Main CPU.
  723.  
  724. The usual application of this is to set bit 5 of MCIEB (enable CPU interrupt)
  725. and then set bit 5 of MCIPD (set pending CPU interrupt). That sends an
  726. interrupt to the SH4 side.
  727.  
  728. -----------------------------------------------------------------------------
  729. 0x2C00: ARMReset
  730.  
  731. bit 15-1 = unused
  732. bit 0 = Reset ARM CPU
  733.  
  734. There are actually other bits in this register, but they're inaccessible from
  735. the ARM side, and undefined on the AICA. There's probably no use accessing
  736. this reg on the ARM side anyway.
  737.  
  738. -----------------------------------------------------------------------------
  739. 0x2D00 - INTRequest
  740.  
  741. bit 15-8 = unused
  742. bit 7-3 = unknown
  743. bit 0-2 = Current interrupt request level (INTREQ)
  744.  
  745. Whenever there's an interrupt, the INTREQ number (determined by SCILV0-2) is
  746. stored here.
  747.  
  748. -----------------------------------------------------------------------------
  749. 0x2D04 - INTClear
  750.  
  751. bit 15-9 = unused
  752. bit 8 = RP
  753. bit 7-0 = M7-M0
  754.  
  755. Writing 0x01 to M7-M0 signals an end-of-interrupt to the AICA.
  756. Sometimes this is done 4 times, perhaps to clear a queue.
  757.  
  758. -----------------------------------------------------------------------------
  759. 0x2E00 - RTCHi
  760.  
  761. bit 15-0 = RTC bits 31-16
  762. Realtime clock, counts seconds.
  763.  
  764. -----------------------------------------------------------------------------
  765. 0x2E04 - RTCLo
  766.  
  767. bit 15-0 = RTC bits 15-0
  768. Realtime clock, counts seconds.
  769.  
  770. -----------------------------------------------------------------------------
  771.  
  772. DSP REGISTERS
  773.  
  774. All values used internally in the DSP are linear integers, signed, 2's
  775. complement. By default, external ringbuffer memory is read and written in a
  776. special floating-point format, but all internal calculations are integer.
  777.  
  778. Every DSP register described here is a 32-bit register, but only the lowest
  779. 16 bits are used.
  780.  
  781. 0x3000-0x31FF: Coefficients (COEF), 128 registers, 13 bits each
  782. 0x3000: bits 15-3 = COEF(0)
  783. 0x3004: bits 15-3 = COEF(1)
  784. ...
  785. 0x31FC: bits 15-3 = COEF(127)
  786. You could interpret these as 16-bit signed (2's complement)
  787. coefficients with the lowest 3 bits are always 0.
  788. Each of the 128 COEFs is used by the corresponding instruction
  789. (MPRO).
  790.  
  791. 0x3200-0x32FF: External memory addresses (MADRS), 64 registers, 16 bits each
  792. 0x3200: bits 15-0 = MADRS(0)
  793. ...
  794. 0x3204: bits 15-0 = MADRS(1)
  795. 0x32FC: bits 15-0 = MADRS(63)
  796. These are memory offsets that refer to locations in the
  797. external ringbuffer. Every increment of a MADRS register
  798. represents 2 bytes.
  799.  
  800. 0x3400-0x3BFF: DSP program (MPRO), 128 registers, 64 bits each
  801. 0x3400: bits 15-0 = bits 63-48 of first instruction
  802. 0x3404: bits 15-0 = bits 47-32 of first instruction
  803. 0x3408: bits 15-0 = bits 31-16 of first instruction
  804. 0x340C: bits 15-0 = bits 15-0 of first instruction
  805. 0x3410: bits 15-0 = bits 63-48 of second instruction
  806. ...
  807. 0x3BFC: bits 15-0 = bits 15-0 of last instruction
  808.  
  809. 0x4000-0x43FF: Temp buffer (TEMP), 128 registers, 24 bits each
  810. 0x4000: bits 7-0 = bits 7-0 of TEMP(0)
  811. 0x4004: bits 15-0 = bits 23-8 of TEMP(0)
  812. 0x4008: bits 7-0 = bits 7-0 of TEMP(1)
  813. ...
  814. 0x43FC: bits 15-0 = bits 23-8 of TEMP(127)
  815. The temp buffer is configured as a ring buffer, so pointers
  816. referring to it decrement by 1 each sample.
  817.  
  818. 0x4400-0x44FF: Memory data (MEMS), 32 registers, 24 bits each
  819. 0x4400: bits 7-0 = bits 7-0 of MEMS(0)
  820. 0x4404: bits 15-0 = bits 23-8 of MEMS(0)
  821. 0x4408: bits 7-0 = bits 7-0 of MEMS(1)
  822. ...
  823. 0x44FC: bits 15-0 = bits 23-8 of MEMS(31)
  824. Used for holding data that was read out of the ringbuffer.
  825.  
  826. 0x4500-0x457F: Mixer input data (MIXS), 16 registers, 20 bits each
  827. 0x4500: bits 3-0 = bits 3-0 of MIXS(0)
  828. 0x4504: bits 15-0 = bits 19-4 of MIXS(0)
  829. 0x4508: bits 3-0 = bits 3-0 of MIXS(1)
  830. ...
  831. 0x457C: bits 15-0 = bits 19-4 of MIXS(15)
  832. These are the 16 send buses coming from the 64 main channels.
  833.  
  834. 0x4580-0x45BF: Effect output data (EFREG), 16 registers, 16 bits each
  835. 0x4580: bits 15-0 = EFREG(0)
  836. 0x4584: bits 15-0 = EFREG(1)
  837. ...
  838. 0x45BC: bits 15-0 = EFREG(15)
  839. These are the 16 sound outputs.
  840.  
  841. 0x45C0-0x45C7: External input data stack (EXTS), 2 registers, 16 bits each
  842. 0x45C0: bits 15-0 = EXTS(0)
  843. 0x45C4: bits 15-0 = EXTS(1)
  844. These come from CDDA left and right, respectively.
  845.  
  846. -----------------------------------------------------------------------------
  847.  
  848. DSP PROGRAM
  849.  
  850. The DSP contains a 128-step program. All 128 steps are executed in order on
  851. every sample. There's no branching or looping.
  852.  
  853. The instruction word format (MPRO) is as follows:
  854.  
  855. bit 63-57 = TRA [6:0]
  856. bit 56 = TWT
  857. bit 55-49 = TWA [6:0]
  858. bit 48 = unused
  859. --------
  860. bit 47 = XSEL
  861. bit 46-45 = YSEL [1:0]
  862. bit 44-39 = IRA [5:0]
  863. bit 38 = IWT
  864. bit 37-33 = IWA [4:0]
  865. bit 32 = unused
  866. --------
  867. bit 31 = TABLE
  868. bit 30 = MWT
  869. bit 29 = MRD
  870. bit 28 = EWT
  871. bit 27-24 = EWA [3:0]
  872. bit 23 = ADRL
  873. bit 22 = FRCL
  874. bit 21-20 = SHFT [1:0]
  875. bit 19 = YRL
  876. bit 18 = NEGB
  877. bit 17 = ZERO
  878. bit 16 = BSEL
  879. --------
  880. bit 15 = NOFL
  881. bit 14-9 = MASA [5:0]
  882. bit 8 = ADREB
  883. bit 7 = NXADR
  884. bit 6-0 = unused
  885.  
  886. Here's what happens on each step. In the following description, I will be
  887. referring to these internal registers:
  888.  
  889. MDEC_CT.... 16-bit unsigned register which is decremented on every sample
  890. INPUTS..... 24-bit signed input value
  891. B.......... 26-bit signed addend
  892. X.......... 24-bit signed multiplicand
  893. Y.......... 13-bit signed multiplier
  894. ACC........ 26-bit signed accumulator
  895. SHIFTED.... 24-bit signed shifted output value
  896. Y_REG...... 24-bit signed latch register
  897. FRC_REG.... 13-bit fractional address
  898. ADRS_REG... 12-bit whole address
  899.  
  900. In the course of one step, all of the following occur in order:
  901.  
  902. (Beginning of step)
  903.  
  904. - Input read
  905.  
  906. A 24-bit value (INPUTS) is read from either MEMS, MIXS, or EXTS, depending
  907. on the value of IRA:
  908.  
  909. IRA 0x00-0x1F: one of the MEMS registers (0x00-0x1F)
  910. IRA 0x20-0x2F: one of the MIXS registers (0x0-0xF)
  911. IRA 0x30-0x31: one of the EXTS registers (0 or 1)
  912. other values: undefined
  913.  
  914. If the source register is less than 24 bits, it's promoted to 24-bit by
  915. shifting left.
  916.  
  917. - Input write
  918.  
  919. If IWT is set, then the memory data from a MRD (either 2 or 3 instructions
  920. ago) is copied into the MEMS register indicated by IWA (0x00-0x1F).
  921.  
  922. If NOFL was set 2 instructions ago (only), the value is simply promoted
  923. from 16 to 24-bit by shifting left. Otherwise, it's converted from 16-bit
  924. float format to 24-bit integer. (See float notes)
  925.  
  926. - B selection
  927.  
  928. A 26-bit value (B) is read from one of two sources:
  929.  
  930. If BSEL=0: The TEMP register indicated by ((TRA + MDEC_CT) & 0x7F).
  931. This value is sign-extended from 24 to 26 bits, not shifted.
  932. If BSEL=1: The accumulator (ACC), already 26 bits.
  933.  
  934. If NEGB=1, this value is then made negative. (B becomes 0-B)
  935. If ZERO=1, this value becomes zero, regardless of all other bits.
  936.  
  937. - X selection
  938.  
  939. A 24-bit value (X) is read from one of two sources:
  940.  
  941. If XSEL=0: One of the TEMP registers indicated by ((TRA + MDEC_CT) & 0x7F).
  942. If XSEL=1: The INPUTS register.
  943.  
  944. - Y selection
  945.  
  946. A 13-bit value (Y) is read from one of four sources:
  947. If YSEL=0: Y becomes FRC_REG
  948. If YSEL=1: Y becomes this instruction's COEF
  949. If YSEL=2: Y becomes bits 23-11 of Y_REG
  950. If YSEL=3: Y becomes bits 15-4 of Y_REG, ZERO-EXTENDED to 13 bits.
  951.  
  952. - Y latch
  953.  
  954. If YRL is set, Y_REG becomes INPUTS.
  955.  
  956. - Shift of previous accumulator
  957.  
  958. A 24-bit value (SHIFTED) is set to one of the following:
  959.  
  960. If SHFT=0: SHIFTED becomes ACC, with saturation
  961. If SHFT=1: SHIFTED becomes ACC*2, with saturation
  962. If SHFT=2: SHIFTED becomes ACC*2, with the highest bits simply cut off
  963. If SHFT=3: SHIFTED becomes ACC, with the highest bits simply cut off
  964.  
  965. If saturation is enabled, SHIFTED is clipped to the range
  966. -0x800000...0x7FFFFF.
  967.  
  968. - Multiply and accumulate
  969.  
  970. A 26-bit value (ACC) becomes ((X * Y) >> 12) + B.
  971. The multiplication is signed. I don't think the addition includes
  972. saturation.
  973.  
  974. - Temp write
  975.  
  976. If TWT is set, the value SHIFTED is written to the temp buffer address
  977. indicated by ((TWA + MDEC_CT) & 0x7F).
  978.  
  979. - Fractional address latch
  980.  
  981. If FRCL is set, FRC_REG (13-bit) becomes one of the following:
  982.  
  983. If SHFT=3: FRC_REG = lowest 12 bits of SHIFTED, ZERO-EXTENDED to 13 bits.
  984. Other values of SHFT: FRC_REG = bits 23-11 of SHIFTED.
  985.  
  986. - Memory operations
  987.  
  988. If either MRD or MWT are set, we are performing a memory operation (on the
  989. external ringbuffer) and we'll need to compute an address.
  990.  
  991. Start with the 16-bit value of the MADRS register indicated by MASA
  992. (0x00-0x3F).
  993. If TABLE=0, add the 16-bit value MDEC_CT.
  994. If ADREB=1, add the 12-bit value ADRS_REG, zero-extended.
  995. If NXADR=1, add 1.
  996. If TABLE=0, mod the address so it's within the proper ringbuffer size.
  997. For a 8Kword ringbuffer: AND by 0x1FFF
  998. For a 16Kword ringbuffer: AND by 0x3FFF
  999. For a 32Kword ringbuffer: AND by 0x7FFF
  1000. For a 64Kword ringbuffer: AND by 0xFFFF
  1001. If TABLE=1, simply AND the address by 0xFFFF.
  1002. Shift the address left by 1 (so it's referring to a word offset).
  1003. Add (RBP<<11).
  1004. This is the address, in main memory, you'll be reading or writing.
  1005.  
  1006. If MRD is set, read the 16-bit word at the calculated address and put it
  1007. in a temporary place. It will then be accessible by the instruction either
  1008. 2 or 3 steps ahead. That instruction will have to use a IWT to get the
  1009. result. Don't perform any conversions yet; let the IWT handle it later on.
  1010.  
  1011. If MWT is set, write the value of SHIFTED into memory at the calculated
  1012. address. If NOFL=1, simply shift it right by 8 to make it 16-bit.
  1013. Otherwise, convert from 24-bit integer to 16-bit float (see float notes).
  1014.  
  1015. - Address latch
  1016.  
  1017. If ADRL is set, ADRS_REG (12-bit) becomes one of the following:
  1018.  
  1019. If SHFT=3: ADRS_REG = INPUTS >> 16 (signed shift with sign extension).
  1020. Other values of SHFT: ADRS_REG = bits 23-12 of SHIFTED.
  1021.  
  1022. - Effect output write
  1023.  
  1024. If EWT is set, write (SHIFTED >> 8) into the EFREG register specified by
  1025. EWA (0x0-0xF).
  1026.  
  1027. (End of step)
  1028.  
  1029. Supposedly, external memory reads and writes (MRD/MWT) are only allowed on
  1030. odd steps (prohibited on step 0, allowed on step 1, etc.), but I found that
  1031. MWT seems to work on any step. I'm just not sure if it's guaranteed to write
  1032. anything meaningful. I doubt it would hurt to allow MRD/MWT on every step in
  1033. an emulator.
  1034.  
  1035. -----------------------------------------------------------------------------
  1036.  
  1037. DSP FLOATING-POINT FORMAT
  1038.  
  1039. When reading/writing external memory, the default (unless NOFL is specified)
  1040. is to use a 16-bit floating-point format, as follows:
  1041.  
  1042. bit 15 = sign
  1043. bit 14-11 = exponent
  1044. bit 10-0 = mantissa
  1045.  
  1046. To convert from 16-bit float to 24-bit integer (on read):
  1047.  
  1048. - Take the mantissa and shift it left by 11
  1049. - Make bit 23 be the sign bit
  1050. - Make bit 22 be the reverse of the sign bit
  1051. - Shift right (signed) by the exponent
  1052.  
  1053. To convert from 24-bit integer to 16-bit float (on write):
  1054.  
  1055. - While the top 2 bits are the same, shift left
  1056. The number of times you have to shift becomes the exponent
  1057. - Shift right (signed) by 11
  1058. - Set bits 14-11 to the exponent value
  1059.  
  1060. -----------------------------------------------------------------------------
  1061.  
  1062. TODO:
  1063.  
  1064. - Obsess over the lowpass f and q coefficients some more
  1065.  
  1066. -----------------------------------------------------------------------------
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