theoretical debug

guard kernel source _snippet :)

exception generation for protection methods

hardware debugging technique ++++ > DRx


//////////////////////////////////////////
Executable file format
loadable modules table : schema_directory (offset : FFF10)

/****************************/
#define addrFUNCTIONs    0x1c
/***************************/
//////////////////////////////////////////

breakpoint condition:

DR7

For each address in registers DR0-DR3, the corresponding fields R/W0
through R/W3 specify the type of action that should cause a breakpoint. The
processor interprets these bits as follows:
00 ── Break on instruction execution only
01 ── Break on data writes only
10 ── undefined
11 ── Break on data reads or writes but not instruction fetches
Fields LEN0 through LEN3 specify the length of data item to be monitored. A
length of 1, 2, or 4 bytes may be specified. The values of the length fields
are interpreted as follows:
00 ── one-byte length
01 ── two-byte length
10 ── undefined
11 ── four-byte length

intel reference:

║ BREAKPOINT 0 LINEAR ADDRESS ║ DR0

Each of these registers contains the linear address associated with one of
four breakpoint conditions. Each breakpoint condition is further defined by
bits in DR7.



+++++ paging mechanism is activated in our core routine

i386
The debug address registers are effective whether or not paging is enabled.
The addresses in these registers are linear addresses. If paging is enabled,
the linear addresses are translated into physical addresses by the
processor's paging mechanism (as explained in Chapter 5). If paging is not
enabled, these linear addresses are the same as physical addresses.