module swfsj7(input [1:0] SW,
    input KEY0,
    output [9:0] LEDR);

    zad2 ex(SW[1], KEY0, SW[0], LEDR[9], LEDR[8:0]);
endmodule

module zad2(input w, clk, aclr,
    output reg z,
    output reg [8:0] y);

    reg [8:0] d;

    always @(*)
    begin
        d[0] = ~aclr;
        d[1] = ~y[0] & ~w | y[5] & ~w | y[6] & ~w | y[7] & ~w | y[8] & ~w;
        d[2] = y[1] & ~w;
        d[3] = y[2] & ~w;
        d[4] = y[3] & ~w | y[4] & ~w;
        d[5] = ~y[0] & w | y[1] & w | y[2] & w | y[3] & w | y[4] & w;
        d[6] = y[5] & w;
        d[7] = y[6] & w;
        d[8] = y[7] & w | y[8] & w;

        z = y[4] | y[8];
    end

    always @(posedge clk, negedge aclr)
        if (~aclr)
            y <= 0;
        else
        begin
            y <= d;
            y[0] <= 1'b1;
        end

endmodule