EPD7_C3

.globl _start
_start:             ldr pc,reset_handler_d      // Exception vector
                    ldr pc,undefined_handler_d
                    ldr pc,swi_handler_d
                    ldr pc,prefetch_handler_d
                    ldr pc,data_handler_d
                    ldr pc,unused_handler_d
                    ldr pc,irq_handler_d
                    ldr pc,fiq_handler_d

reset_handler_d:    .word reset_handler
undefined_handler_d:.word hang
swi_handler_d:      .word swi_handler
prefetch_handler_d: .word hang
data_handler_d:     .word hang
unused_handler_d:   .word hang
irq_handler_d:      .word irq_handler
fiq_handler_d:      .word hang

UARTDR:             .word 0x101f1000            // UART data register address
UARTFR:             .word 0x101f1018            // UART flag register address
UARTCR:             .word 0x101f1030            // UART control register address
UARTIMSC:           .word 0x101f1038            // UART interrupt mask address
UARTICR:            .word 0x101f1044            // UART interrupt clear address

TIMER0_LOAD:        .word 0x101E2000            // TIMER0 registers
TIMER0_VALUE:       .word 0x101E2004
TIMER0_CONTROL:     .word 0x101E2008
TIMER0_INTCLR:      .word 0x101E200C
TIMER0_RIS:         .word 0x101E2010
TIMER0_MIS:         .word 0x101E2014
TIMER0_BGLOAD:      .word 0x101E2018

VICINTENABLE:       .word 0x10140010            // Vectorize interrupt controller

reset_handler:      mov r0,#0x10000             // Copy exception vector
                    mov r1,#0x00000
                    ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
                    stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
                    ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
                    stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
                    msr cpsr_c,#0xD1            // FIQ 110 10001
                    mov sp,#0x100000
                    msr cpsr_c,#0xD2            // IRQ 110 10010
                    mov sp,#0x200000
                    msr cpsr_c,#0xD3            // SVC 110 10011
                    mov sp,#0x300000
                    msr cpsr_c,#0xD7            // ABT 110 10111
                    mov sp,#0x400000
                    msr cpsr_c,#0xDB            // UND 110 11011
                    mov sp,#0x500000
                    msr cpsr_c,#0xDF            // SYS 110 11111
                    mov sp,#0x600000
                    msr cpsr_c,#0xD0            // USER 110 10000
                    mov sp,#0x700000
                    b main                      // start main

hang:               b hang

str_swi:            .asciz "swi "
                    .align

swi_handler:        stmfd sp!,{r0,r1,r5,lr}     // SWI handler routine
                    ldr r5,[lr,#-4]
                    bic r5,r5,#0xff000000
                    ldr r0,=str_swi
                    bl printString
                    mov r0,r5
                    bl printInt
                    mov r0,#'\n'
                    bl write_uart

                    mrs r0, spsr // Leemos reg estado
                    cmp r5, #100
                    biceq r0, #0x80 //#0b10000000 = 0x80 Borrar el bit I (numero 7)

                    msr spsr, r0  // Escribe reg estado con el valor (procesado o no) anterior

                    ldmfd sp!,{r0,r1,r5,pc}^

cont_seg:           .word 0
cont_min:           .word 0

irq_message:        .asciz "It works!\n"
                    .align
irq_handler:        sub lr, #4 @ En FIQ e IRQ debemos restar 4 para no saltarnos la instruccion en curso
                    stmfd sp!,{r0-r10,lr}

                    mov r4,#0x0             @ Primero: Limpiar interrupciones correspondientes
                    ldr r5,TIMER0_INTCLR
                    str r4,[r5]
                    /* ldr r0, =irq_message @ mostramos el mensaje
                    bl printString */
                    ldr r1,=cont_seg
                    ldr r0,[r1]
                    add r0, #1
                    str r0, [r1]
                    bl printInt
                    mov r0,#'\r'
                    bl write_uart


                    ldmfd sp!,{r0-r10,pc}^

.globl write_uart
write_uart:         stmdb sp!,{r4}
                    ldr r4,UARTDR
                    strb r0,[r4]
                    ldmia sp!,{r4}
                    bx lr

.globl read_uart
read_uart:          stmdb sp!,{r4,r5}
                    ldr r4,UARTFR
                    ldr r4,UARTDR
                    ldrb r0,[r4]
                    ldmia sp!,{r4,r5}
                    bx lr

/* init_timer0:     stmdb sp!,{r4,r5}
                    mov r4,r0
                    ldr r5,TIMER0_LOAD
                    str r4,[r5]
                    mov r4,#0x0
                    ldr r5,TIMER0_INTCLR
                    str r4,[r5]
                    mov r4,#0xe2            // 0xe2 = 0b11100010 (hab. timer, modo periodico)
                    ldr r5,TIMER0_CONTROL
                    str r4,[r5]
                    mov r4,#0x10            // Habilitamos el dispositivo de la linea 4 (0x10 = 0b0010000)
                    ldr r5,VICINTENABLE
                    str r4,[r5]
                    ldmia sp!,{r4,r5}
                    bx lr */
aux_int_uart0:      .word 0x301
init_uart0:         stmdb sp!,{r4,r5}
                    mov r4,#0x0
                    ldr r5,UARTICR
                    str r4,[r5]
                    ldr r4, =aux_int_uart0          // Habilitamos bits 9, 8, 0 (habilita tx, rx, device)
                    ldr r5,UARTCR
                    mov r4, #0x10
                    ldr r5, UARTIMSC
                    str r4,[r5]                     // Habilitamos bit 4 (interrupciones en entrada de datos)
                    ldr r5, VICINTENABLE
                    ldr r4, [r5]
                    orr r4, #0x1000         // Habilitamos el dispositivo de la linea 12
                    str r4, [r5]
                    ldmia sp!,{r4,r5}
                    bx lr

/* valor_timer0: .word 0x1e8480 // 2seg */
valor_timer0: .word 0xf4240  // 1 seg
.globl main
main:               ldr r0, =valor_timer0
                    ldr r0, [r0]
                    bl init_uart0
                    swi #100 @ Habilitamos las IRQ
loop_for_ever:      b loop_for_ever