library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;




entity lab4 is
    port(
        c0, c1, c2, c3: in std_logic;
        y : out std_logic_vector(0 to 6)
    );
end lab4;

architecture display of lab4 is

begin
y <= "0000001" when c0 = '0' and c1 = '0' and c2 = '0' and c3 = '0' else
    "1001111" when c0 =  '0' and c1 = '0' and c2 = '0' and c3 = '1' else
    "0010010" when c0 =  '0' and c1 = '0' and c2 = '1' and c3 = '0' else
    "0000110"when c0 =  '0' and c1 = '0' and c2 = '1' and c3 = '1' else
    "1001100" when c0 = '0' and c1 = '1' and c2 = '0' and c3 = '0' else
    "0100100" when c0 =  '0' and c1 = '1' and c2 = '0' and c3 = '1' else
    "0100000" when c0 =  '0' and c1 = '1' and c2 = '1' and c3 = '0' else
    "0001111" when c0 =  '0' and c1 = '1' and c2 = '1' and c3 = '1' else
    "0000000" when c0 =  '1' and c1 = '0' and c2 = '0' and c3 = '0' else
    "0000100" when c0 =  '1' and c1 = '0' and c2 = '0' and c3 = '1' else
	 "0001000" when c0 =  '1' and c1 = '0' and c2 = '1' and c3 = '0' else
	 "1100000" when c0 =  '1' and c1 = '0' and c2 = '1' and c3 = '1' else
	 "0110001" when c0 =  '1' and c1 = '1' and c2 = '0' and c3 = '0' else
	 "1000010" when c0 =  '1' and c1 = '1' and c2 = '0' and c3 = '1' else
	 "0110000" when c0 =  '1' and c1 = '1' and c2 = '1' and c3 = '0' else
	 "0111000" when c0 =  '1' and c1 = '1' and c2 = '1' and c3 = '1';
end display;