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  1. From 4af44fbc97bc51eb742f0d6555bde23cf580d4e3 Mon Sep 17 00:00:00 2001
  2. From: graysky <graysky@archlinux.us>
  3. Date: Sun, 6 Jun 2021 09:41:36 -0400
  4. Subject: [PATCH] more uarches for kernel 5.8+
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8.  
  9. FEATURES
  10. This patch adds additional CPU options to the Linux kernel accessible under:
  11. Processor type and features --->
  12. Processor family --->
  13.  
  14. With the release of gcc 11.1 and clang 12.0, several generic 64-bit levels are
  15. offered which are good for supported Intel or AMD CPUs:
  16. • x86-64-v2
  17. • x86-64-v3
  18. • x86-64-v4
  19.  
  20. Users of glibc 2.33 and above can see which level is supported by current
  21. hardware by running:
  22. /lib/ld-linux-x86-64.so.2 --help | grep supported
  23.  
  24. Alternatively, compare the flags from /proc/cpuinfo to this list.[1]
  25.  
  26. CPU-specific microarchitectures include:
  27. • AMD Improved K8-family
  28. • AMD K10-family
  29. • AMD Family 10h (Barcelona)
  30. • AMD Family 14h (Bobcat)
  31. • AMD Family 16h (Jaguar)
  32. • AMD Family 15h (Bulldozer)
  33. • AMD Family 15h (Piledriver)
  34. • AMD Family 15h (Steamroller)
  35. • AMD Family 15h (Excavator)
  36. • AMD Family 17h (Zen)
  37. • AMD Family 17h (Zen 2)
  38. • AMD Family 19h (Zen 3)†
  39. • Intel Silvermont low-power processors
  40. • Intel Goldmont low-power processors (Apollo Lake and Denverton)
  41. • Intel Goldmont Plus low-power processors (Gemini Lake)
  42. • Intel 1st Gen Core i3/i5/i7 (Nehalem)
  43. • Intel 1.5 Gen Core i3/i5/i7 (Westmere)
  44. • Intel 2nd Gen Core i3/i5/i7 (Sandybridge)
  45. • Intel 3rd Gen Core i3/i5/i7 (Ivybridge)
  46. • Intel 4th Gen Core i3/i5/i7 (Haswell)
  47. • Intel 5th Gen Core i3/i5/i7 (Broadwell)
  48. • Intel 6th Gen Core i3/i5/i7 (Skylake)
  49. • Intel 6th Gen Core i7/i9 (Skylake X)
  50. • Intel 8th Gen Core i3/i5/i7 (Cannon Lake)
  51. • Intel 10th Gen Core i7/i9 (Ice Lake)
  52. • Intel Xeon (Cascade Lake)
  53. • Intel Xeon (Cooper Lake)*
  54. • Intel 3rd Gen 10nm++ i3/i5/i7/i9-family (Tiger Lake)*
  55. • Intel 3rd Gen 10nm++ Xeon (Sapphire Rapids)‡
  56. • Intel 11th Gen i3/i5/i7/i9-family (Rocket Lake)‡
  57. • Intel 12th Gen i3/i5/i7/i9-family (Alder Lake)‡
  58.  
  59. Notes: If not otherwise noted, gcc >=9.1 is required for support.
  60. *Requires gcc >=10.1 or clang >=10.0
  61. †Required gcc >=10.3 or clang >=12.0
  62. ‡Required gcc >=11.1 or clang >=12.0
  63.  
  64. It also offers to compile passing the 'native' option which, "selects the CPU
  65. to generate code for at compilation time by determining the processor type of
  66. the compiling machine. Using -march=native enables all instruction subsets
  67. supported by the local machine and will produce code optimized for the local
  68. machine under the constraints of the selected instruction set."[2]
  69.  
  70. Users of Intel CPUs should select the 'Intel-Native' option and users of AMD
  71. CPUs should select the 'AMD-Native' option.
  72.  
  73. MINOR NOTES RELATING TO INTEL ATOM PROCESSORS
  74. This patch also changes -march=atom to -march=bonnell in accordance with the
  75. gcc v4.9 changes. Upstream is using the deprecated -match=atom flags when I
  76. believe it should use the newer -march=bonnell flag for atom processors.[3]
  77.  
  78. It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The
  79. recommendation is to use the 'atom' option instead.
  80.  
  81. BENEFITS
  82. Small but real speed increases are measurable using a make endpoint comparing
  83. a generic kernel to one built with one of the respective microarchs.
  84.  
  85. See the following experimental evidence supporting this statement:
  86. https://github.com/graysky2/kernel_gcc_patch
  87.  
  88. REQUIREMENTS
  89. linux version >=5.8
  90. gcc version >=9.0 or clang version >=9.0
  91.  
  92. ACKNOWLEDGMENTS
  93. This patch builds on the seminal work by Jeroen.[5]
  94.  
  95. REFERENCES
  96. 1. https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/77566eb03bc6a326811cb7e9
  97. 2. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html#index-x86-Options
  98. 3. https://bugzilla.kernel.org/show_bug.cgi?id=77461
  99. 4. https://github.com/graysky2/kernel_gcc_patch/issues/15
  100. 5. http://www.linuxforge.net/docs/linux/linux-gcc.php
  101.  
  102. Signed-off-by: graysky <graysky@archlinux.us>
  103. ---
  104. arch/x86/Kconfig.cpu | 332 ++++++++++++++++++++++++++++++--
  105. arch/x86/Makefile | 47 ++++-
  106. arch/x86/include/asm/vermagic.h | 66 +++++++
  107. 3 files changed, 428 insertions(+), 17 deletions(-)
  108.  
  109. diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
  110. index 814fe0d349b0..8acf6519d279 100644
  111. --- a/arch/x86/Kconfig.cpu
  112. +++ b/arch/x86/Kconfig.cpu
  113. @@ -157,7 +157,7 @@ config MPENTIUM4
  114.  
  115.  
  116. config MK6
  117. - bool "K6/K6-II/K6-III"
  118. + bool "AMD K6/K6-II/K6-III"
  119. depends on X86_32
  120. help
  121. Select this for an AMD K6-family processor. Enables use of
  122. @@ -165,7 +165,7 @@ config MK6
  123. flags to GCC.
  124.  
  125. config MK7
  126. - bool "Athlon/Duron/K7"
  127. + bool "AMD Athlon/Duron/K7"
  128. depends on X86_32
  129. help
  130. Select this for an AMD Athlon K7-family processor. Enables use of
  131. @@ -173,12 +173,98 @@ config MK7
  132. flags to GCC.
  133.  
  134. config MK8
  135. - bool "Opteron/Athlon64/Hammer/K8"
  136. + bool "AMD Opteron/Athlon64/Hammer/K8"
  137. help
  138. Select this for an AMD Opteron or Athlon64 Hammer-family processor.
  139. Enables use of some extended instructions, and passes appropriate
  140. optimization flags to GCC.
  141.  
  142. +config MK8SSE3
  143. + bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
  144. + help
  145. + Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
  146. + Enables use of some extended instructions, and passes appropriate
  147. + optimization flags to GCC.
  148. +
  149. +config MK10
  150. + bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
  151. + help
  152. + Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
  153. + Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
  154. + Enables use of some extended instructions, and passes appropriate
  155. + optimization flags to GCC.
  156. +
  157. +config MBARCELONA
  158. + bool "AMD Barcelona"
  159. + help
  160. + Select this for AMD Family 10h Barcelona processors.
  161. +
  162. + Enables -march=barcelona
  163. +
  164. +config MBOBCAT
  165. + bool "AMD Bobcat"
  166. + help
  167. + Select this for AMD Family 14h Bobcat processors.
  168. +
  169. + Enables -march=btver1
  170. +
  171. +config MJAGUAR
  172. + bool "AMD Jaguar"
  173. + help
  174. + Select this for AMD Family 16h Jaguar processors.
  175. +
  176. + Enables -march=btver2
  177. +
  178. +config MBULLDOZER
  179. + bool "AMD Bulldozer"
  180. + help
  181. + Select this for AMD Family 15h Bulldozer processors.
  182. +
  183. + Enables -march=bdver1
  184. +
  185. +config MPILEDRIVER
  186. + bool "AMD Piledriver"
  187. + help
  188. + Select this for AMD Family 15h Piledriver processors.
  189. +
  190. + Enables -march=bdver2
  191. +
  192. +config MSTEAMROLLER
  193. + bool "AMD Steamroller"
  194. + help
  195. + Select this for AMD Family 15h Steamroller processors.
  196. +
  197. + Enables -march=bdver3
  198. +
  199. +config MEXCAVATOR
  200. + bool "AMD Excavator"
  201. + help
  202. + Select this for AMD Family 15h Excavator processors.
  203. +
  204. + Enables -march=bdver4
  205. +
  206. +config MZEN
  207. + bool "AMD Zen"
  208. + help
  209. + Select this for AMD Family 17h Zen processors.
  210. +
  211. + Enables -march=znver1
  212. +
  213. +config MZEN2
  214. + bool "AMD Zen 2"
  215. + help
  216. + Select this for AMD Family 17h Zen 2 processors.
  217. +
  218. + Enables -march=znver2
  219. +
  220. +config MZEN3
  221. + bool "AMD Zen 3"
  222. + depends on (CC_IS_GCC && GCC_VERSION >= 100300) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  223. + help
  224. + Select this for AMD Family 19h Zen 3 processors.
  225. +
  226. + Enables -march=znver3
  227. +
  228. config MCRUSOE
  229. bool "Crusoe"
  230. depends on X86_32
  231. @@ -270,7 +356,7 @@ config MPSC
  232. in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
  233.  
  234. config MCORE2
  235. - bool "Core 2/newer Xeon"
  236. + bool "Intel Core 2"
  237. help
  238.  
  239. Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
  240. @@ -278,6 +364,8 @@ config MCORE2
  241. family in /proc/cpuinfo. Newer ones have 6 and older ones 15
  242. (not a typo)
  243.  
  244. + Enables -march=core2
  245. +
  246. config MATOM
  247. bool "Intel Atom"
  248. help
  249. @@ -287,6 +375,182 @@ config MATOM
  250. accordingly optimized code. Use a recent GCC with specific Atom
  251. support in order to fully benefit from selecting this option.
  252.  
  253. +config MNEHALEM
  254. + bool "Intel Nehalem"
  255. + select X86_P6_NOP
  256. + help
  257. +
  258. + Select this for 1st Gen Core processors in the Nehalem family.
  259. +
  260. + Enables -march=nehalem
  261. +
  262. +config MWESTMERE
  263. + bool "Intel Westmere"
  264. + select X86_P6_NOP
  265. + help
  266. +
  267. + Select this for the Intel Westmere formerly Nehalem-C family.
  268. +
  269. + Enables -march=westmere
  270. +
  271. +config MSILVERMONT
  272. + bool "Intel Silvermont"
  273. + select X86_P6_NOP
  274. + help
  275. +
  276. + Select this for the Intel Silvermont platform.
  277. +
  278. + Enables -march=silvermont
  279. +
  280. +config MGOLDMONT
  281. + bool "Intel Goldmont"
  282. + select X86_P6_NOP
  283. + help
  284. +
  285. + Select this for the Intel Goldmont platform including Apollo Lake and Denverton.
  286. +
  287. + Enables -march=goldmont
  288. +
  289. +config MGOLDMONTPLUS
  290. + bool "Intel Goldmont Plus"
  291. + select X86_P6_NOP
  292. + help
  293. +
  294. + Select this for the Intel Goldmont Plus platform including Gemini Lake.
  295. +
  296. + Enables -march=goldmont-plus
  297. +
  298. +config MSANDYBRIDGE
  299. + bool "Intel Sandy Bridge"
  300. + select X86_P6_NOP
  301. + help
  302. +
  303. + Select this for 2nd Gen Core processors in the Sandy Bridge family.
  304. +
  305. + Enables -march=sandybridge
  306. +
  307. +config MIVYBRIDGE
  308. + bool "Intel Ivy Bridge"
  309. + select X86_P6_NOP
  310. + help
  311. +
  312. + Select this for 3rd Gen Core processors in the Ivy Bridge family.
  313. +
  314. + Enables -march=ivybridge
  315. +
  316. +config MHASWELL
  317. + bool "Intel Haswell"
  318. + select X86_P6_NOP
  319. + help
  320. +
  321. + Select this for 4th Gen Core processors in the Haswell family.
  322. +
  323. + Enables -march=haswell
  324. +
  325. +config MBROADWELL
  326. + bool "Intel Broadwell"
  327. + select X86_P6_NOP
  328. + help
  329. +
  330. + Select this for 5th Gen Core processors in the Broadwell family.
  331. +
  332. + Enables -march=broadwell
  333. +
  334. +config MSKYLAKE
  335. + bool "Intel Skylake"
  336. + select X86_P6_NOP
  337. + help
  338. +
  339. + Select this for 6th Gen Core processors in the Skylake family.
  340. +
  341. + Enables -march=skylake
  342. +
  343. +config MSKYLAKEX
  344. + bool "Intel Skylake X"
  345. + select X86_P6_NOP
  346. + help
  347. +
  348. + Select this for 6th Gen Core processors in the Skylake X family.
  349. +
  350. + Enables -march=skylake-avx512
  351. +
  352. +config MCANNONLAKE
  353. + bool "Intel Cannon Lake"
  354. + select X86_P6_NOP
  355. + help
  356. +
  357. + Select this for 8th Gen Core processors
  358. +
  359. + Enables -march=cannonlake
  360. +
  361. +config MICELAKE
  362. + bool "Intel Ice Lake"
  363. + select X86_P6_NOP
  364. + help
  365. +
  366. + Select this for 10th Gen Core processors in the Ice Lake family.
  367. +
  368. + Enables -march=icelake-client
  369. +
  370. +config MCASCADELAKE
  371. + bool "Intel Cascade Lake"
  372. + select X86_P6_NOP
  373. + help
  374. +
  375. + Select this for Xeon processors in the Cascade Lake family.
  376. +
  377. + Enables -march=cascadelake
  378. +
  379. +config MCOOPERLAKE
  380. + bool "Intel Cooper Lake"
  381. + depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
  382. + select X86_P6_NOP
  383. + help
  384. +
  385. + Select this for Xeon processors in the Cooper Lake family.
  386. +
  387. + Enables -march=cooperlake
  388. +
  389. +config MTIGERLAKE
  390. + bool "Intel Tiger Lake"
  391. + depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
  392. + select X86_P6_NOP
  393. + help
  394. +
  395. + Select this for third-generation 10 nm process processors in the Tiger Lake family.
  396. +
  397. + Enables -march=tigerlake
  398. +
  399. +config MSAPPHIRERAPIDS
  400. + bool "Intel Sapphire Rapids"
  401. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  402. + select X86_P6_NOP
  403. + help
  404. +
  405. + Select this for third-generation 10 nm process processors in the Sapphire Rapids family.
  406. +
  407. + Enables -march=sapphirerapids
  408. +
  409. +config MROCKETLAKE
  410. + bool "Intel Rocket Lake"
  411. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  412. + select X86_P6_NOP
  413. + help
  414. +
  415. + Select this for eleventh-generation processors in the Rocket Lake family.
  416. +
  417. + Enables -march=rocketlake
  418. +
  419. +config MALDERLAKE
  420. + bool "Intel Alder Lake"
  421. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  422. + select X86_P6_NOP
  423. + help
  424. +
  425. + Select this for twelfth-generation processors in the Alder Lake family.
  426. +
  427. + Enables -march=alderlake
  428. +
  429. config GENERIC_CPU
  430. bool "Generic-x86-64"
  431. depends on X86_64
  432. @@ -294,6 +558,50 @@ config GENERIC_CPU
  433. Generic x86-64 CPU.
  434. Run equally well on all x86-64 CPUs.
  435.  
  436. +config GENERIC_CPU2
  437. + bool "Generic-x86-64-v2"
  438. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  439. + depends on X86_64
  440. + help
  441. + Generic x86-64 CPU.
  442. + Run equally well on all x86-64 CPUs with min support of x86-64-v2.
  443. +
  444. +config GENERIC_CPU3
  445. + bool "Generic-x86-64-v3"
  446. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  447. + depends on X86_64
  448. + help
  449. + Generic x86-64-v3 CPU with v3 instructions.
  450. + Run equally well on all x86-64 CPUs with min support of x86-64-v3.
  451. +
  452. +config GENERIC_CPU4
  453. + bool "Generic-x86-64-v4"
  454. + depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
  455. + depends on X86_64
  456. + help
  457. + Generic x86-64 CPU with v4 instructions.
  458. + Run equally well on all x86-64 CPUs with min support of x86-64-v4.
  459. +
  460. +config MNATIVE_INTEL
  461. + bool "Intel-Native optimizations autodetected by the compiler"
  462. + help
  463. +
  464. + Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
  465. + the optimum settings to use based on your processor. Do NOT use this
  466. + for AMD CPUs. Intel Only!
  467. +
  468. + Enables -march=native
  469. +
  470. +config MNATIVE_AMD
  471. + bool "AMD-Native optimizations autodetected by the compiler"
  472. + help
  473. +
  474. + Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
  475. + the optimum settings to use based on your processor. Do NOT use this
  476. + for Intel CPUs. AMD Only!
  477. +
  478. + Enables -march=native
  479. +
  480. endchoice
  481.  
  482. config X86_GENERIC
  483. @@ -318,7 +626,7 @@ config X86_INTERNODE_CACHE_SHIFT
  484. config X86_L1_CACHE_SHIFT
  485. int
  486. default "7" if MPENTIUM4 || MPSC
  487. - default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
  488. + default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD || X86_GENERIC || GENERIC_CPU || GENERIC_CPU2 || GENERIC_CPU3 || GENERIC_CPU4
  489. default "4" if MELAN || M486SX || M486 || MGEODEGX1
  490. default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
  491.  
  492. @@ -336,11 +644,11 @@ config X86_ALIGNMENT_16
  493.  
  494. config X86_INTEL_USERCOPY
  495. def_bool y
  496. - depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
  497. + depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL
  498.  
  499. config X86_USE_PPRO_CHECKSUM
  500. def_bool y
  501. - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
  502. + depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD
  503.  
  504. config X86_USE_3DNOW
  505. def_bool y
  506. @@ -360,26 +668,26 @@ config X86_USE_3DNOW
  507. config X86_P6_NOP
  508. def_bool y
  509. depends on X86_64
  510. - depends on (MCORE2 || MPENTIUM4 || MPSC)
  511. + depends on (MCORE2 || MPENTIUM4 || MPSC || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL)
  512.  
  513. config X86_TSC
  514. def_bool y
  515. - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
  516. + depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD) || X86_64
  517.  
  518. config X86_CMPXCHG64
  519. def_bool y
  520. - depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8
  521. + depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD
  522.  
  523. # this should be set for all -march=.. options where the compiler
  524. # generates cmov.
  525. config X86_CMOV
  526. def_bool y
  527. - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
  528. + depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD)
  529.  
  530. config X86_MINIMUM_CPU_FAMILY
  531. int
  532. default "64" if X86_64
  533. - default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8)
  534. + default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MNATIVE_INTEL || MNATIVE_AMD)
  535. default "5" if X86_32 && X86_CMPXCHG64
  536. default "4"
  537.  
  538. diff --git a/arch/x86/Makefile b/arch/x86/Makefile
  539. index 78faf9c7e3ae..ee0cd507af8b 100644
  540. --- a/arch/x86/Makefile
  541. +++ b/arch/x86/Makefile
  542. @@ -114,11 +114,48 @@ else
  543. # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
  544. cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
  545. cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
  546. -
  547. - cflags-$(CONFIG_MCORE2) += \
  548. - $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
  549. - cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
  550. - $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
  551. + cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3)
  552. + cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
  553. + cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
  554. + cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
  555. + cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
  556. + cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
  557. + cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
  558. + cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-mno-tbm)
  559. + cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
  560. + cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-mno-tbm)
  561. + cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
  562. + cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-mno-tbm)
  563. + cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
  564. + cflags-$(CONFIG_MZEN2) += $(call cc-option,-march=znver2)
  565. + cflags-$(CONFIG_MZEN3) += $(call cc-option,-march=znver3)
  566. +
  567. + cflags-$(CONFIG_MNATIVE_INTEL) += $(call cc-option,-march=native)
  568. + cflags-$(CONFIG_MNATIVE_AMD) += $(call cc-option,-march=native)
  569. + cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell)
  570. + cflags-$(CONFIG_MCORE2) += $(call cc-option,-march=core2)
  571. + cflags-$(CONFIG_MNEHALEM) += $(call cc-option,-march=nehalem)
  572. + cflags-$(CONFIG_MWESTMERE) += $(call cc-option,-march=westmere)
  573. + cflags-$(CONFIG_MSILVERMONT) += $(call cc-option,-march=silvermont)
  574. + cflags-$(CONFIG_MGOLDMONT) += $(call cc-option,-march=goldmont)
  575. + cflags-$(CONFIG_MGOLDMONTPLUS) += $(call cc-option,-march=goldmont-plus)
  576. + cflags-$(CONFIG_MSANDYBRIDGE) += $(call cc-option,-march=sandybridge)
  577. + cflags-$(CONFIG_MIVYBRIDGE) += $(call cc-option,-march=ivybridge)
  578. + cflags-$(CONFIG_MHASWELL) += $(call cc-option,-march=haswell)
  579. + cflags-$(CONFIG_MBROADWELL) += $(call cc-option,-march=broadwell)
  580. + cflags-$(CONFIG_MSKYLAKE) += $(call cc-option,-march=skylake)
  581. + cflags-$(CONFIG_MSKYLAKEX) += $(call cc-option,-march=skylake-avx512)
  582. + cflags-$(CONFIG_MCANNONLAKE) += $(call cc-option,-march=cannonlake)
  583. + cflags-$(CONFIG_MICELAKE) += $(call cc-option,-march=icelake-client)
  584. + cflags-$(CONFIG_MCASCADELAKE) += $(call cc-option,-march=cascadelake)
  585. + cflags-$(CONFIG_MCOOPERLAKE) += $(call cc-option,-march=cooperlake)
  586. + cflags-$(CONFIG_MTIGERLAKE) += $(call cc-option,-march=tigerlake)
  587. + cflags-$(CONFIG_MSAPPHIRERAPIDS) += $(call cc-option,-march=sapphirerapids)
  588. + cflags-$(CONFIG_MROCKETLAKE) += $(call cc-option,-march=rocketlake)
  589. + cflags-$(CONFIG_MALDERLAKE) += $(call cc-option,-march=alderlake)
  590. + cflags-$(CONFIG_GENERIC_CPU2) += $(call cc-option,-march=x86-64-v2)
  591. + cflags-$(CONFIG_GENERIC_CPU3) += $(call cc-option,-march=x86-64-v3)
  592. + cflags-$(CONFIG_GENERIC_CPU4) += $(call cc-option,-march=x86-64-v4)
  593. cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
  594. KBUILD_CFLAGS += $(cflags-y)
  595.  
  596. diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagic.h
  597. index 75884d2cdec3..4e6a08d4c7e5 100644
  598. --- a/arch/x86/include/asm/vermagic.h
  599. +++ b/arch/x86/include/asm/vermagic.h
  600. @@ -17,6 +17,48 @@
  601. #define MODULE_PROC_FAMILY "586MMX "
  602. #elif defined CONFIG_MCORE2
  603. #define MODULE_PROC_FAMILY "CORE2 "
  604. +#elif defined CONFIG_MNATIVE_INTEL
  605. +#define MODULE_PROC_FAMILY "NATIVE_INTEL "
  606. +#elif defined CONFIG_MNATIVE_AMD
  607. +#define MODULE_PROC_FAMILY "NATIVE_AMD "
  608. +#elif defined CONFIG_MNEHALEM
  609. +#define MODULE_PROC_FAMILY "NEHALEM "
  610. +#elif defined CONFIG_MWESTMERE
  611. +#define MODULE_PROC_FAMILY "WESTMERE "
  612. +#elif defined CONFIG_MSILVERMONT
  613. +#define MODULE_PROC_FAMILY "SILVERMONT "
  614. +#elif defined CONFIG_MGOLDMONT
  615. +#define MODULE_PROC_FAMILY "GOLDMONT "
  616. +#elif defined CONFIG_MGOLDMONTPLUS
  617. +#define MODULE_PROC_FAMILY "GOLDMONTPLUS "
  618. +#elif defined CONFIG_MSANDYBRIDGE
  619. +#define MODULE_PROC_FAMILY "SANDYBRIDGE "
  620. +#elif defined CONFIG_MIVYBRIDGE
  621. +#define MODULE_PROC_FAMILY "IVYBRIDGE "
  622. +#elif defined CONFIG_MHASWELL
  623. +#define MODULE_PROC_FAMILY "HASWELL "
  624. +#elif defined CONFIG_MBROADWELL
  625. +#define MODULE_PROC_FAMILY "BROADWELL "
  626. +#elif defined CONFIG_MSKYLAKE
  627. +#define MODULE_PROC_FAMILY "SKYLAKE "
  628. +#elif defined CONFIG_MSKYLAKEX
  629. +#define MODULE_PROC_FAMILY "SKYLAKEX "
  630. +#elif defined CONFIG_MCANNONLAKE
  631. +#define MODULE_PROC_FAMILY "CANNONLAKE "
  632. +#elif defined CONFIG_MICELAKE
  633. +#define MODULE_PROC_FAMILY "ICELAKE "
  634. +#elif defined CONFIG_MCASCADELAKE
  635. +#define MODULE_PROC_FAMILY "CASCADELAKE "
  636. +#elif defined CONFIG_MCOOPERLAKE
  637. +#define MODULE_PROC_FAMILY "COOPERLAKE "
  638. +#elif defined CONFIG_MTIGERLAKE
  639. +#define MODULE_PROC_FAMILY "TIGERLAKE "
  640. +#elif defined CONFIG_MSAPPHIRERAPIDS
  641. +#define MODULE_PROC_FAMILY "SAPPHIRERAPIDS "
  642. +#elif defined CONFIG_ROCKETLAKE
  643. +#define MODULE_PROC_FAMILY "ROCKETLAKE "
  644. +#elif defined CONFIG_MALDERLAKE
  645. +#define MODULE_PROC_FAMILY "ALDERLAKE "
  646. #elif defined CONFIG_MATOM
  647. #define MODULE_PROC_FAMILY "ATOM "
  648. #elif defined CONFIG_M686
  649. @@ -35,6 +77,30 @@
  650. #define MODULE_PROC_FAMILY "K7 "
  651. #elif defined CONFIG_MK8
  652. #define MODULE_PROC_FAMILY "K8 "
  653. +#elif defined CONFIG_MK8SSE3
  654. +#define MODULE_PROC_FAMILY "K8SSE3 "
  655. +#elif defined CONFIG_MK10
  656. +#define MODULE_PROC_FAMILY "K10 "
  657. +#elif defined CONFIG_MBARCELONA
  658. +#define MODULE_PROC_FAMILY "BARCELONA "
  659. +#elif defined CONFIG_MBOBCAT
  660. +#define MODULE_PROC_FAMILY "BOBCAT "
  661. +#elif defined CONFIG_MBULLDOZER
  662. +#define MODULE_PROC_FAMILY "BULLDOZER "
  663. +#elif defined CONFIG_MPILEDRIVER
  664. +#define MODULE_PROC_FAMILY "PILEDRIVER "
  665. +#elif defined CONFIG_MSTEAMROLLER
  666. +#define MODULE_PROC_FAMILY "STEAMROLLER "
  667. +#elif defined CONFIG_MJAGUAR
  668. +#define MODULE_PROC_FAMILY "JAGUAR "
  669. +#elif defined CONFIG_MEXCAVATOR
  670. +#define MODULE_PROC_FAMILY "EXCAVATOR "
  671. +#elif defined CONFIG_MZEN
  672. +#define MODULE_PROC_FAMILY "ZEN "
  673. +#elif defined CONFIG_MZEN2
  674. +#define MODULE_PROC_FAMILY "ZEN2 "
  675. +#elif defined CONFIG_MZEN3
  676. +#define MODULE_PROC_FAMILY "ZEN3 "
  677. #elif defined CONFIG_MELAN
  678. #define MODULE_PROC_FAMILY "ELAN "
  679. #elif defined CONFIG_MCRUSOE
  680. --
  681. 2.31.1
  682.  
  683.  
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