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E_MX_2012-11-07

rayddteam
Nov 6th, 2012
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  1. U-Boot 2009.01.2.0.6-efikasb (Nov 02 2010 - 09:58:13)
  2.  
  3. CPU: Freescale i.MX51 family 3.0V at 800 MHz
  4. mx51 pll1: 800MHz
  5. mx51 pll2: 665MHz
  6. mx51 pll3: 216MHz
  7. ipg clock : 66500000Hz
  8. ipg per clock : 665000000Hz
  9. uart clock : 66500000Hz
  10. cspi clock : 54000000Hz
  11. Board: Efika MX Smartbook [POR]
  12. PMIC ID: 0x000045d0 [Rev: 2.0a]
  13. DRAM: 512 MB
  14. JEDEC ID: 0xbf:0x25:0x4a
  15. Reading SPI NOR flash 0x40000 [0x1000 bytes] -> ram 0xafd006e8
  16. SUCCESS
  17.  
  18. In: serial
  19. Out: serial
  20. Err: serial
  21. Boot Source: SPI NOR FLASH BOOT
  22. Hit any key to stop autoboot: 0
  23. JEDEC ID: 0xbf:0x25:0x4a
  24. 4096 KiB SST25VF032B - 4MB at 0:1 is now current device
  25. Reading SPI NOR flash 0x100000 [0x50000 bytes] -> ram 0x97800000
  26. .SUCCESS
  27.  
  28. ## Starting application at 0x97800000 ...
  29. �
  30. U-Boot 2012.04.01-g7862ffd-dirty (Aug 16 2012 - 16:53:57)
  31.  
  32. CPU: Freescale i.MX51 rev3.0 at 800 MHz
  33. Reset cause: POR
  34. Board: Efika MX, rev1.3
  35. DRAM: 512 MiB
  36. WARNING: Caches not enabled
  37. MMC: FSL_SDHC: 0
  38. SF: Detected SST25VF032B with page size 4 KiB, total 4 MiB
  39. In: serial
  40. Out: serial
  41. Err: serial
  42. Net: CPU Net Initialization Failed
  43. No ethernet found.
  44. Efika> run bsd
  45. (Re)start USB...
  46. USB: Register 10011 NbrPorts 1
  47. USB EHCI 1.00
  48. scanning bus for devices... 3 USB Device(s) found
  49. scanning bus for storage devices... 0 Storage Device(s) found
  50. scanning bus for ethernet devices... 1 Ethernet Device(s) found
  51. Waiting for Ethernet connection... done.
  52. Using asx0 device
  53. TFTP from server 192.168.10.90; our IP address is 192.168.10.87
  54. Filename 'efika_mx/kernel.uboot'.
  55. Load address: 0x91000000
  56. Loading: T #################################################################
  57. #################################################################
  58. #################################################################
  59. #################################################################
  60. ####################################################
  61. done
  62. Bytes transferred = 4572096 (45c3c0 hex)
  63. ## Booting kernel from Legacy Image at 91000000 ...
  64. Image Name: FreeBSD kernel
  65. Created: 2012-11-06 22:50:54 UTC
  66. Image Type: ARM Linux Kernel Image (uncompressed)
  67. Data Size: 4572032 Bytes = 4.4 MiB
  68. Load Address: 90100000
  69. Entry Point: 90100100
  70. Verifying Checksum ... OK
  71. Loading Kernel Image ... OK
  72. OK
  73.  
  74. Starting kernel ...
  75.  
  76. initarm: console initialized
  77. arg1 kmdp = 0xc05dfe50
  78. boothowto = 0x20001800
  79. dtbp = 0xc0442600
  80. kernel image addresses:
  81. loader passed (static) kenv:
  82. no env, null ptr
  83. processing avail regions:
  84. 90000000-b0000000 -> 90000000-90100000 = 100000
  85. 90697000-b0000000 -> 90697000-b0000000 = 1f969000
  86. fill in phys_avail:
  87. region: 0x90000000 - 0x90100000 (0x00100000)
  88. region: 0x90697000 - 0xb0000000 (0x1f969000)
  89. KDB: debugger backends: ddb
  90. KDB: current backend: ddb
  91. Copyright (c) 1992-2012 The FreeBSD Project.
  92. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
  93. The Regents of the University of California. All rights reserved.
  94. FreeBSD is a registered trademark of The FreeBSD Foundation.
  95. FreeBSD 10.0-CURRENT #51 r242678M: Wed Nov 7 00:50:42 EET 2012
  96. [email protected]:/usr/obj/arm.armv6/usr/home/ray/work/FreeBSD/Projects/Efika_MX/src/efika_mx/sys/EFIKA_MX arm
  97. WARNING: WITNESS option enabled, expect reduced performance.
  98. Preloaded elf kernel "kernel" at 0xc05dfe50.
  99. CPU: Cortex A8-r2 rev 5 (Cortex-A core)
  100. Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext
  101. WB disabled EABT branch prediction enabled
  102. LoUU:2 LoC:2 LoUIS:1
  103. Cache level 1:
  104. 32KB/64B 4-way data cache WT WB Read-Alloc
  105. 32KB/64B 4-way instruction cache Read-Alloc
  106. Cache level 2:
  107. 256KB/64B 8-way unified cache WT WB Read-Alloc Write-Alloc
  108. real memory = 536870912 (512 MB)
  109. Physical memory chunk(s):
  110. 0x90000000 - 0x900fffff, 1048576 bytes (256 pages)
  111. 0x90697000 - 0xaf629fff, 519647232 bytes (126867 pages)
  112. avail memory = 518365184 (494 MB)
  113. pmap_postinit: Allocated 274 static L1 descriptor tables
  114. random device not loaded; using insecure entropy
  115. wlan: <802.11 Link Layer>
  116. nfslock: pseudo-device
  117. null: <null device, zero device>
  118. openfirm: <Open Firmware control device>
  119. random: <entropy source, Software, Yarrow>
  120. mem: <memory>
  121. fdtbus_identify(): fdtbus_identify(driver=0xc0444d90, parent=0xc2e3a100)
  122. fdtbus_probe(): fdtbus_probe(dev=0xc2e05900); pass=2147483647
  123. fdtbus_probe(): fdtbus_probe(dev=0xc2e05900); pass=2147483647
  124. fdtbus0: <FDT main bus>
  125. newbus_device_from_fdt_node(): skipping instantiating FDT device='aliases'
  126. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  127. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  128. newbus_device_create(): added child name='cpus', node=0xd4
  129. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  130. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  131. newbus_device_create(): added child name='localbus@e0000000', node=0x1c0
  132. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  133. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  134. newbus_device_create(): added child name='soc@70000000', node=0x2c0
  135. newbus_device_from_fdt_node(): skipping instantiating FDT device='memory'
  136. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  137. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  138. newbus_device_create(): added child name='gpio-keys', node=0x1dd8
  139. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  140. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  141. newbus_device_create(): added child name='gpio-leds', node=0x1e64
  142. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  143. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  144. newbus_device_create(): added child name='sound', node=0x1f74
  145. simplebus0: <Flattened device tree simple bus> on fdtbus0
  146. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  147. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  148. fdt_reg_to_rl(): reg addr start = d006e000, end = d0071fff, count = 4000
  149. simplebus0: added child: tz-interrupt-controller@e0000000
  150.  
  151. tzic0: <TrustZone Interrupt Controller> mem 0xd006e000-0xd0071fff on simplebus0
  152. simplebus1: <Flattened device tree simple bus> on fdtbus0
  153. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  154. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  155. simplebus1: added child: aips@70000000
  156.  
  157. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  158. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  159. simplebus1: added child: aips@80000000
  160.  
  161. simplebus2: <Flattened device tree simple bus> on simplebus1
  162. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  163. fdt_reg_to_rl(): tuples = 4, tuple size = 8
  164. fdt_reg_to_rl(): reg addr start = e3fd4000, end = e3fd7fff, count = 4000
  165. fdt_reg_to_rl(): reg addr start = d0072000, end = d0075fff, count = 4000
  166. fdt_reg_to_rl(): reg addr start = d0076000, end = d0079fff, count = 4000
  167. fdt_reg_to_rl(): reg addr start = d007a000, end = d007dfff, count = 4000
  168. fdt_intr_to_rl(): decoded intr = 71, trig = 0, pol = 0
  169. fdt_intr_to_rl(): decoded intr = 72, trig = 0, pol = 0
  170. simplebus2: added child: clock@73fd4000
  171.  
  172. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  173. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  174. simplebus2: added child: spba@70000000
  175.  
  176. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  177. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  178. fdt_reg_to_rl(): reg addr start = e3f80000, end = e3f83fff, count = 4000
  179. fdt_intr_to_rl(): decoded intr = 14, trig = 0, pol = 0
  180. fdt_intr_to_rl(): decoded intr = 16, trig = 0, pol = 0
  181. fdt_intr_to_rl(): decoded intr = 17, trig = 0, pol = 0
  182. fdt_intr_to_rl(): decoded intr = 18, trig = 0, pol = 0
  183. simplebus2: added child: usb@73F80000
  184.  
  185. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  186. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  187. fdt_reg_to_rl(): reg addr start = e3f84000, end = e3f87fff, count = 4000
  188. fdt_intr_to_rl(): decoded intr = 50, trig = 0, pol = 0
  189. fdt_intr_to_rl(): decoded intr = 51, trig = 0, pol = 0
  190. simplebus2: added child: gpio@73f84000
  191.  
  192. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  193. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  194. fdt_reg_to_rl(): reg addr start = e3f88000, end = e3f8bfff, count = 4000
  195. fdt_intr_to_rl(): decoded intr = 52, trig = 0, pol = 0
  196. fdt_intr_to_rl(): decoded intr = 53, trig = 0, pol = 0
  197. simplebus2: added child: gpio@73f88000
  198.  
  199. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  200. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  201. fdt_reg_to_rl(): reg addr start = e3f8c000, end = e3f8ffff, count = 4000
  202. fdt_intr_to_rl(): decoded intr = 54, trig = 0, pol = 0
  203. fdt_intr_to_rl(): decoded intr = 55, trig = 0, pol = 0
  204. simplebus2: added child: gpio@73f8c000
  205.  
  206. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  207. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  208. fdt_reg_to_rl(): reg addr start = e3f90000, end = e3f93fff, count = 4000
  209. fdt_intr_to_rl(): decoded intr = 56, trig = 0, pol = 0
  210. fdt_intr_to_rl(): decoded intr = 57, trig = 0, pol = 0
  211. simplebus2: added child: gpio@73f90000
  212.  
  213. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  214. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  215. fdt_reg_to_rl(): reg addr start = e3f98000, end = e3f9bfff, count = 4000
  216. fdt_intr_to_rl(): decoded intr = 58, trig = 0, pol = 0
  217. simplebus2: added child: wdog@73f98000
  218.  
  219. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  220. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  221. fdt_reg_to_rl(): reg addr start = e3fa0000, end = e3fa3fff, count = 4000
  222. fdt_intr_to_rl(): decoded intr = 39, trig = 0, pol = 0
  223. simplebus2: added child: timer@73fa0000
  224.  
  225. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  226. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  227. fdt_reg_to_rl(): reg addr start = e3fa8000, end = e3fabfff, count = 4000
  228. fdt_intr_to_rl(): decoded intr = 7, trig = 0, pol = 0
  229. simplebus2: added child: iomux@73fa8000
  230.  
  231. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  232. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  233. fdt_reg_to_rl(): reg addr start = e3fbc000, end = e3fbffff, count = 4000
  234. fdt_intr_to_rl(): decoded intr = 31, trig = 0, pol = 0
  235. simplebus2: added child: serial@73fbc000
  236.  
  237. imxccm0: <Freescale Clock Control Module> mem 0xe3fd4000-0xe3fd7fff,0xd0072000-0xd0075fff,0xd0076000-0xd0079fff,0xd007a000-0xd007dfff irq 71,72 on simplebus2
  238. ref: 96000000KHz dp_ctl: 00001223 pdf: 0 mfi: 8 mfd: 2 mfn: 1 pll: 800000000
  239. ref: 96000000KHz dp_ctl: 00001223 pdf: 0 mfi: 6 mfd: 95 mfn: 89 pll: 665000000
  240. ref: 96000000KHz dp_ctl: 00001223 pdf: 2 mfi: 6 mfd: 3 mfn: 3 pll: 216000000
  241. imxccm0: PLL1=800MHz, PLL2=665MHz, PLL3=216MHz
  242. cscdr1=c30461 cscmr1=a162a020
  243. imxccm0: CPU clock=800000000, UART clock=66500000
  244. cbcmr=20c2 cbcdr=59e35145
  245. imxccm0: mainbus clock=665000000, ahb clock=133000000 ipg clock=66500000 perclk=2000000
  246. simplebus3: <Flattened device tree simple bus> on simplebus2
  247. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  248. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  249. fdt_reg_to_rl(): reg addr start = d007e000, end = d0081fff, count = 4000
  250. fdt_intr_to_rl(): decoded intr = 1, trig = 0, pol = 0
  251. simplebus3: added child: esdhc@70004000
  252.  
  253. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  254. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  255. fdt_reg_to_rl(): reg addr start = d0082000, end = d0085fff, count = 4000
  256. fdt_intr_to_rl(): decoded intr = 36, trig = 0, pol = 0
  257. simplebus3: added child: ecspi@70010000
  258.  
  259. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  260. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  261. simplebus3: added child: ssi@70014000
  262.  
  263. ehci0: <Freescale integrated EHCI controller> mem 0xe3f80000-0xe3f83fff irq 14,16,17,18 on simplebus2
  264. ehci0: [GIANT-LOCKED]
  265. ehci0: [GIANT-LOCKED]
  266. ehci0: [GIANT-LOCKED]
  267. usbus0: EHCI version 1.0
  268. usbus0 on ehci0
  269. ehci0: usbpf: Attached
  270. imx_gpt0: <Freescale i.MXxxx GPT timer> mem 0xe3fa0000-0xe3fa3fff irq 39 on simplebus2
  271. imx_gpt0: Run on 66500KHz clock.
  272. Event timer "i.MXxxx GPT Eventtimer" frequency 66500000 Hz quality 1000
  273. Timecounter "i.MX GPT Timecouter" frequency 66500000 Hz quality 1000
  274. clock: hz=100 stathz = 0
  275. imx_gpt0: timer clock frequency 66500000
  276. uart0: <imx_uart> mem 0xe3fbc000-0xe3fbffff irq 31 on simplebus2
  277. heuart0: fast interrupt
  278. simplebus4: <Flattened device tree simple bus> on simplebus1
  279. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  280. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  281. fdt_reg_to_rl(): reg addr start = d00a0000, end = d00a3fff, count = 4000
  282. fdt_intr_to_rl(): decoded intr = 6, trig = 0, pol = 0
  283. simplebus4: added child: sdma@83fb0000
  284.  
  285. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  286. fdt_reg_to_rl(): tuples = 1, tuple size = 8
  287. fdt_reg_to_rl(): reg addr start = d00a4000, end = d00a7fff, count = 4000
  288. fdt_intr_to_rl(): decoded intr = 63, trig = 0, pol = 0
  289. simplebus4: added child: i2c@83fc4000
  290.  
  291. fdt_reg_to_rl(): addr_cells = 1, size_cells = 1
  292. fdt_reg_to_rl(): tuples = -1, tuple size = 8
  293. simplebus4: added child: audmux@83fd0000
  294.  
  295. imx_gpt0: switch DELAY to use H/W counter
  296. Timecounters tick every 10.000 msec
  297. lo0: bpf attached
  298. usbus0: 480Mbps High Speed USB v2.0
  299. bootpc_init: wired to interface 'ue0'
  300. ugen0.1: <Freescale> at usbus0
  301. uhub0: <Freescale EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0
  302. uhub0: 1 port with 1 removable, self powered
  303. ugen0.2: <vendor 0x1a40> at usbus0
  304. uhub1: <vendor 0x1a40 USB 2.0 Hub MTT, class 9/0, rev 2.00/1.00, addr 2> on usbus0
  305. uhub1: MTT enabled
  306. uhub1: 4 ports with 4 removable, self powered
  307. ugen0.3: <vendor 0x2001> at usbus0
  308. axe0: <vendor 0x2001 product 0x3c05, rev 2.00/0.01, addr 3> on usbus0
  309. axe0: PHYADDR 0xe0:0x03
  310. miibus0: <MII bus> on axe0
  311. rlphy0: <IP101 10/100 PHY> PHY 3 on miibus0
  312. rlphy0: OUI 0x0009c3, model 0x0005, rev. 4
  313. rlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
  314. ue0: <USB Ethernet> on axe0
  315. ue0: bpf attached
  316. ue0: Ethernet address: 00:80:c8:3b:cf:91
  317. ue0: link state changed to DOWN
  318. Sending DHCP Discover packet from interface ue0 (00:80:c8:3b:cf:91)
  319. ue0: link state changed to UP
  320. Received DHCP Offer packet on ue0 from 192.168.10.10 (accepted) (no root path)
  321. Sending DHCP Request packet from interface ue0 (00:80:c8:3b:cf:91)
  322. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  323. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  324. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  325. DHCP/BOOTP timeout for server 255.255.255.255
  326. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  327. DHCP/BOOTP timeout for server 255.255.255.255
  328. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  329. DHCP/BOOTP timeout for server 255.255.255.255
  330. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  331. DHCP/BOOTP timeout for server 255.255.255.255
  332. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  333. DHCP/BOOTP timeout for server 255.255.255.255
  334. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  335. DHCP/BOOTP timeout for server 255.255.255.255
  336. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  337. DHCP/BOOTP timeout for server 255.255.255.255
  338. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  339. DHCP/BOOTP timeout for server 255.255.255.255
  340. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  341. DHCP/BOOTP timeout for server 255.255.255.255
  342. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  343. DHCP/BOOTP timeout for server 255.255.255.255
  344. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  345. DHCP/BOOTP timeout for server 255.255.255.255
  346. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  347. DHCP/BOOTP timeout for server 255.255.255.255
  348. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  349. DHCP/BOOTP timeout for server 255.255.255.255
  350. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  351. DHCP/BOOTP timeout for server 255.255.255.255
  352. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
  353. DHCP/BOOTP timeout for server 255.255.255.255
  354. Received DHCP Ack packet on ue0 from 192.168.10.10 (accepted) (no root path)
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