# 1 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts"
# 43 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts"
/dts-v1/;

# 1 "./scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h" 1
# 46 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 1
# 43 "arch/arm64/boot/dts/rockchip/rk3399.dtsi"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-cru.h" 1
# 44 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 45 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1







# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 46 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 48 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3399-power.h" 1
# 49 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h" 1
# 50 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip-system-status.h" 1
# 51 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/suspend/rockchip-rk3399.h" 1
# 52 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 53 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2

# 1 "arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi" 1
# 42 "arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/memory/rk3399-dram.h" 1
# 43 "arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi" 2

/ {
 ddr_timing: ddr_timing {
  compatible = "rockchip,ddr-timing";
  ddr3_speed_bin = <21>;
  pd_idle = <0>;
  sr_idle = <0>;
  sr_mc_gate_idle = <0>;
  srpd_lite_idle = <0>;
  standby_idle = <0>;
  auto_lp_dis_freq = <666>;
  ddr3_dll_dis_freq = <300>;
  phy_dll_dis_freq = <260>;

  ddr3_odt_dis_freq = <666>;
  ddr3_drv = <(40)>;
  ddr3_odt = <(120)>;
  phy_ddr3_ca_drv = <(40)>;
  phy_ddr3_dq_drv = <(40)>;
  phy_ddr3_odt = <(240)>;

  lpddr3_odt_dis_freq = <666>;
  lpddr3_drv = <(34)>;
  lpddr3_odt = <(240)>;
  phy_lpddr3_ca_drv = <(34)>;
  phy_lpddr3_dq_drv = <(34)>;
  phy_lpddr3_odt = <(240)>;

  lpddr4_odt_dis_freq = <800>;
  lpddr4_drv = <(240)>;
  lpddr4_dq_odt = <(40)>;
  lpddr4_ca_odt = <(0)>;
  phy_lpddr4_ca_drv = <(40)>;
  phy_lpddr4_ck_cs_drv = <(40)>;
  phy_lpddr4_dq_drv = <(60)>;
  phy_lpddr4_odt = <(40)>;
 };
};
# 55 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2

/ {
 compatible = "rockchip,rk3399";

 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  dsi0 = &dsi;
  dsi1 = &dsi1;
  ethernet0 = &gmac;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  i2c6 = &i2c6;
  i2c7 = &i2c7;
  i2c8 = &i2c8;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_l0>;
    };
    core1 {
     cpu = <&cpu_l1>;
    };
    core2 {
     cpu = <&cpu_l2>;
    };
    core3 {
     cpu = <&cpu_l3>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&cpu_b0>;
    };
    core1 {
     cpu = <&cpu_b1>;
    };
   };
  };

  cpu_l0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a53", "arm,armv8";
   reg = <0x0 0x0>;
   enable-method = "psci";
   #cooling-cells = <2>;
   clocks = <&cru 8>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <100>;
  };

  cpu_l1: cpu@1 {
   device_type = "cpu";
   compatible = "arm,cortex-a53", "arm,armv8";
   reg = <0x0 0x1>;
   enable-method = "psci";
   clocks = <&cru 8>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <100>;
  };

  cpu_l2: cpu@2 {
   device_type = "cpu";
   compatible = "arm,cortex-a53", "arm,armv8";
   reg = <0x0 0x2>;
   enable-method = "psci";
   clocks = <&cru 8>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <100>;
  };

  cpu_l3: cpu@3 {
   device_type = "cpu";
   compatible = "arm,cortex-a53", "arm,armv8";
   reg = <0x0 0x3>;
   enable-method = "psci";
   clocks = <&cru 8>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <100>;
  };

  cpu_b0: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a72", "arm,armv8";
   reg = <0x0 0x100>;
   enable-method = "psci";
   #cooling-cells = <2>;
   clocks = <&cru 9>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <436>;
  };

  cpu_b1: cpu@101 {
   device_type = "cpu";
   compatible = "arm,cortex-a72", "arm,armv8";
   reg = <0x0 0x101>;
   enable-method = "psci";
   clocks = <&cru 9>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   dynamic-power-coefficient = <436>;
  };

  idle-states {
   entry-method = "psci";

   CPU_SLEEP: cpu-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x0010000>;
    entry-latency-us = <120>;
    exit-latency-us = <250>;
    min-residency-us = <900>;
   };

   CLUSTER_SLEEP: cluster-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x1010000>;
    entry-latency-us = <400>;
    exit-latency-us = <500>;
    min-residency-us = <2000>;
   };
  };
 };

 pmu_a53 {
  compatible = "arm,cortex-a53-pmu";
  interrupts = <1 7 8 &ppi_cluster0>;
 };

 pmu_a72 {
  compatible = "arm,cortex-a72-pmu";
  interrupts = <1 7 8 &ppi_cluster1>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 8 0>,
        <1 14 8 0>,
        <1 11 8 0>,
        <1 10 8 0>;
  arm,no-tick-in-suspend;
 };

 xin24m: xin24m {
  compatible = "fixed-clock";
  clock-frequency = <24000000>;
  clock-output-names = "xin24m";
  #clock-cells = <0>;
 };

 dummy_cpll: dummy_cpll {
  compatible = "fixed-clock";
  clock-frequency = <0>;
  clock-output-names = "dummy_cpll";
  #clock-cells = <0>;
 };

 dummy_vpll: dummy_vpll {
  compatible = "fixed-clock";
  clock-frequency = <0>;
  clock-output-names = "dummy_vpll";
  #clock-cells = <0>;
 };

 amba {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  dmac_bus: dma-controller@ff6d0000 {
   compatible = "arm,pl330", "arm,primecell";
   reg = <0x0 0xff6d0000 0x0 0x4000>;
   interrupts = <0 5 4 0>,
         <0 6 4 0>;
   #dma-cells = <1>;
   clocks = <&cru 211>;
   clock-names = "apb_pclk";
   peripherals-req-type-burst;
  };

  dmac_peri: dma-controller@ff6e0000 {
   compatible = "arm,pl330", "arm,primecell";
   reg = <0x0 0xff6e0000 0x0 0x4000>;
   interrupts = <0 7 4 0>,
         <0 8 4 0>;
   #dma-cells = <1>;
   clocks = <&cru 212>;
   clock-names = "apb_pclk";
   peripherals-req-type-burst;
  };
 };

 gmac: ethernet@fe300000 {
  compatible = "rockchip,rk3399-gmac";
  reg = <0x0 0xfe300000 0x0 0x10000>;
  interrupts = <0 12 4 0>;
  interrupt-names = "macirq";
  clocks = <&cru 105>, <&cru 103>,
    <&cru 104>, <&cru 102>,
    <&cru 106>, <&cru 213>,
    <&cru 358>;
  clock-names = "stmmaceth", "mac_clk_rx",
         "mac_clk_tx", "clk_mac_ref",
         "clk_mac_refout", "aclk_mac",
         "pclk_mac";
  power-domains = <&power 22>;
  resets = <&cru 137>;
  reset-names = "stmmaceth";
  rockchip,grf = <&grf>;
  status = "disabled";
 };

 sdio0: dwmmc@fe310000 {
  compatible = "rockchip,rk3399-dw-mshc",
        "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe310000 0x0 0x4000>;
  interrupts = <0 64 4 0>;
  max-frequency = <150000000>;
  clocks = <&cru 494>, <&cru 77>,
    <&cru 156>, <&cru 157>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  power-domains = <&power 28>;
  resets = <&cru 121>;
  reset-names = "reset";
  status = "disabled";
 };

 sdmmc: dwmmc@fe320000 {
  compatible = "rockchip,rk3399-dw-mshc",
        "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe320000 0x0 0x4000>;
  interrupts = <0 65 4 0>;
  max-frequency = <150000000>;
  assigned-clocks = <&cru 461>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 462>, <&cru 76>,
    <&cru 154>, <&cru 155>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  power-domains = <&power 27>;
  resets = <&cru 122>;
  reset-names = "reset";
  status = "disabled";
 };

 sdhci: sdhci@fe330000 {
  compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  reg = <0x0 0xfe330000 0x0 0x10000>;
  interrupts = <0 11 4 0>;
  arasan,soc-ctl-syscon = <&grf>;
  assigned-clocks = <&cru 78>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 78>, <&cru 240>;
  clock-names = "clk_xin", "clk_ahb";
  clock-output-names = "emmc_cardclock";
  #clock-cells = <0>;
  phys = <&emmc_phy>;
  phy-names = "phy_arasan";
  power-domains = <&power 23>;
  status = "disabled";
 };

 usic: usb@fe340000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfe340000 0x0 0x30000>;
  interrupts = <0 33 4 0>;
  clocks = <&cru 460>, <&cru 121>,
    <&cru 340>;
  clock-names = "hclk_hsic", "clk_hsicphy", "pclk_hsicphy";
  rockchip-has-usic;
  status = "disabled";
 };

 usb_host0_ehci: usb@fe380000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfe380000 0x0 0x20000>;
  interrupts = <0 26 4 0>;
  clocks = <&cru 456>, <&cru 457>,
    <&cru 168>;
  clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
  phys = <&u2phy0_host>;
  phy-names = "usb";
  power-domains = <&power 14>;
  status = "disabled";
 };

 usb_host0_ohci: usb@fe3a0000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfe3a0000 0x0 0x20000>;
  interrupts = <0 28 4 0>;
  clocks = <&cru 456>, <&cru 457>,
    <&cru 168>;
  clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
  phys = <&u2phy0_host>;
  phy-names = "usb";
  power-domains = <&power 14>;
  status = "disabled";
 };

 usb_host1_ehci: usb@fe3c0000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfe3c0000 0x0 0x20000>;
  interrupts = <0 30 4 0>;
  clocks = <&cru 458>, <&cru 459>,
    <&cru 169>;
  clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
  phys = <&u2phy1_host>;
  phy-names = "usb";
  power-domains = <&power 14>;
  status = "disabled";
 };

 usb_host1_ohci: usb@fe3e0000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfe3e0000 0x0 0x20000>;
  interrupts = <0 32 4 0>;
  clocks = <&cru 458>, <&cru 459>,
    <&cru 169>;
  clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
  phys = <&u2phy1_host>;
  phy-names = "usb";
  power-domains = <&power 14>;
  status = "disabled";
 };

 usbdrd3_0: usb@fe800000 {
  compatible = "rockchip,rk3399-dwc3";
  clocks = <&cru 129>, <&cru 131>,
    <&cru 246>, <&cru 249>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk", "grf_clk";
  power-domains = <&power 24>;
  resets = <&cru 293>;
  reset-names = "usb3-otg";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  status = "disabled";
  usbdrd_dwc3_0: dwc3@fe800000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfe800000 0x0 0x100000>;
   interrupts = <0 105 4 0>;
   dr_mode = "otg";
   phys = <&u2phy0_otg>, <&tcphy0_usb3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis_u2_susphy_quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,tx-ipgap-linecheck-dis-quirk;
   snps,xhci-slow-suspend-quirk;
   snps,usb3-warm-reset-on-resume-quirk;
   status = "disabled";
  };
 };

 usbdrd3_1: usb@fe900000 {
  compatible = "rockchip,rk3399-dwc3";
  clocks = <&cru 130>, <&cru 132>,
    <&cru 247>, <&cru 249>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk", "grf_clk";
  power-domains = <&power 24>;
  resets = <&cru 294>;
  reset-names = "usb3-otg";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  status = "disabled";
  usbdrd_dwc3_1: dwc3@fe900000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfe900000 0x0 0x100000>;
   interrupts = <0 110 4 0>;
   dr_mode = "host";
   phys = <&u2phy1_otg>, <&tcphy1_usb3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis_u2_susphy_quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,tx-ipgap-linecheck-dis-quirk;
   snps,xhci-slow-suspend-quirk;
   snps,usb3-warm-reset-on-resume-quirk;
   status = "disabled";
  };
 };

 cdn_dp: dp@fec00000 {
  compatible = "rockchip,rk3399-cdn-dp";
  reg = <0x0 0xfec00000 0x0 0x100000>;
  interrupts = <0 9 4 0>;
  assigned-clocks = <&cru 114>, <&cru 161>;
  assigned-clock-rates = <100000000>, <200000000>;
  clocks = <&cru 114>, <&cru 373>,
    <&cru 161>, <&cru 367>;
  clock-names = "core-clk", "pclk", "spdif", "grf";
  power-domains = <&power 21>;
  phys = <&tcphy0_dp>, <&tcphy1_dp>;
  resets = <&cru 259>, <&cru 328>,
    <&cru 330>, <&cru 253>;
  reset-names = "spdif", "dptx", "apb", "core";
  rockchip,grf = <&grf>;
  #address-cells = <1>;
  #size-cells = <0>;
  #sound-dai-cells = <1>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   dp_in: port {
    #address-cells = <1>;
    #size-cells = <0>;
    dp_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_dp>;
    };

    dp_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_dp>;
    };
   };
  };
 };

 gic: interrupt-controller@fee00000 {
  compatible = "arm,gic-v3";
  #interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  interrupt-controller;

  reg = <0x0 0xfee00000 0 0x10000>,
        <0x0 0xfef00000 0 0xc0000>,
        <0x0 0xfff00000 0 0x10000>,
        <0x0 0xfff10000 0 0x10000>,
        <0x0 0xfff20000 0 0x10000>;
  interrupts = <1 9 4 0>;
  its: interrupt-controller@fee20000 {
   compatible = "arm,gic-v3-its";
   msi-controller;
   reg = <0x0 0xfee20000 0x0 0x20000>;
  };

  ppi-partitions {
   ppi_cluster0: interrupt-partition-0 {
    affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
   };

   ppi_cluster1: interrupt-partition-1 {
    affinity = <&cpu_b0 &cpu_b1>;
   };
  };
 };

 saradc: saradc@ff100000 {
  compatible = "rockchip,rk3399-saradc";
  reg = <0x0 0xff100000 0x0 0x100>;
  interrupts = <0 62 4 0>;
  #io-channel-cells = <1>;
  clocks = <&cru 80>, <&cru 357>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 212>;
  reset-names = "saradc-apb";
  status = "disabled";
 };

 i2c0: i2c@ff3c0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3c0000 0x0 0x1000>;
  clocks = <&pmucru 9>, <&pmucru 27>;
  clock-names = "i2c", "pclk";
  interrupts = <0 57 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c0_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c1: i2c@ff110000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff110000 0x0 0x1000>;
  clocks = <&cru 65>, <&cru 341>;
  clock-names = "i2c", "pclk";
  interrupts = <0 59 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c1_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@ff120000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff120000 0x0 0x1000>;
  clocks = <&cru 66>, <&cru 342>;
  clock-names = "i2c", "pclk";
  interrupts = <0 35 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c2_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c3: i2c@ff130000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff130000 0x0 0x1000>;
  clocks = <&cru 67>, <&cru 343>;
  clock-names = "i2c", "pclk";
  interrupts = <0 34 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c3_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c5: i2c@ff140000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff140000 0x0 0x1000>;
  clocks = <&cru 68>, <&cru 344>;
  clock-names = "i2c", "pclk";
  interrupts = <0 38 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c5_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c6: i2c@ff150000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff150000 0x0 0x1000>;
  clocks = <&cru 69>, <&cru 345>;
  clock-names = "i2c", "pclk";
  interrupts = <0 37 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c6_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c7: i2c@ff160000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff160000 0x0 0x1000>;
  clocks = <&cru 70>, <&cru 346>;
  clock-names = "i2c", "pclk";
  interrupts = <0 36 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c7_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart0: serial@ff180000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff180000 0x0 0x100>;
  clocks = <&cru 81>, <&cru 352>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 99 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
  status = "disabled";
 };

 uart1: serial@ff190000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff190000 0x0 0x100>;
  clocks = <&cru 82>, <&cru 353>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 98 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart1_xfer>;
  status = "disabled";
 };

 uart2: serial@ff1a0000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1a0000 0x0 0x100>;
  clocks = <&cru 83>, <&cru 354>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 100 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2c_xfer>;
  status = "disabled";
 };

 uart3: serial@ff1b0000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1b0000 0x0 0x100>;
  clocks = <&cru 84>, <&cru 355>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 101 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
  status = "disabled";
 };

 spi0: spi@ff1c0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1c0000 0x0 0x1000>;
  clocks = <&cru 71>, <&cru 347>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 68 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi1: spi@ff1d0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1d0000 0x0 0x1000>;
  clocks = <&cru 72>, <&cru 348>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 53 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi2: spi@ff1e0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1e0000 0x0 0x1000>;
  clocks = <&cru 73>, <&cru 349>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 52 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi4: spi@ff1f0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1f0000 0x0 0x1000>;
  clocks = <&cru 74>, <&cru 350>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 67 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi5: spi@ff200000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff200000 0x0 0x1000>;
  clocks = <&cru 75>, <&cru 351>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 132 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 thermal_zones: thermal-zones {
  soc_thermal: soc-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   sustainable-power = <1000>;

   thermal-sensors = <&tsadc 0>;

   trips {
    threshold: trip-point-0 {
     temperature = <70000>;
     hysteresis = <2000>;
     type = "passive";
    };
    target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    soc_crit: soc-crit {
     temperature = <115000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&target>;
     cooling-device =
      <&cpu_l0 (~0) (~0)>;
     contribution = <4096>;
    };
    map1 {
     trip = <&target>;
     cooling-device =
      <&cpu_b0 (~0) (~0)>;
     contribution = <1024>;
    };
    map2 {
     trip = <&target>;
     cooling-device =
      <&gpu (~0) (~0)>;
     contribution = <4096>;
    };
   };
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <1000>;

   thermal-sensors = <&tsadc 1>;
  };
 };

 tsadc: tsadc@ff260000 {
  compatible = "rockchip,rk3399-tsadc";
  reg = <0x0 0xff260000 0x0 0x100>;
  interrupts = <0 97 4 0>;
  assigned-clocks = <&cru 79>;
  assigned-clock-rates = <750000>;
  clocks = <&cru 79>, <&cru 356>;
  clock-names = "tsadc", "apb_pclk";
  resets = <&cru 232>;
  reset-names = "tsadc-apb";
  rockchip,grf = <&grf>;
  rockchip,hw-tshut-temp = <120000>;
  pinctrl-names = "init", "default", "sleep";
  pinctrl-0 = <&otp_gpio>;
  pinctrl-1 = <&otp_out>;
  pinctrl-2 = <&otp_gpio>;
  #thermal-sensor-cells = <1>;
  status = "disabled";
 };

 qos_emmc: qos@ffa58000 {
  compatible = "syscon";
  reg = <0x0 0xffa58000 0x0 0x20>;
 };

 qos_gmac: qos@ffa5c000 {
  compatible = "syscon";
  reg = <0x0 0xffa5c000 0x0 0x20>;
 };

 qos_pcie: qos@ffa60080 {
  compatible = "syscon";
  reg = <0x0 0xffa60080 0x0 0x20>;
 };

 qos_usb_host0: qos@ffa60100 {
  compatible = "syscon";
  reg = <0x0 0xffa60100 0x0 0x20>;
 };

 qos_usb_host1: qos@ffa60180 {
  compatible = "syscon";
  reg = <0x0 0xffa60180 0x0 0x20>;
 };

 qos_usb_otg0: qos@ffa70000 {
  compatible = "syscon";
  reg = <0x0 0xffa70000 0x0 0x20>;
 };

 qos_usb_otg1: qos@ffa70080 {
  compatible = "syscon";
  reg = <0x0 0xffa70080 0x0 0x20>;
 };

 qos_sd: qos@ffa74000 {
  compatible = "syscon";
  reg = <0x0 0xffa74000 0x0 0x20>;
 };

 qos_sdioaudio: qos@ffa76000 {
  compatible = "syscon";
  reg = <0x0 0xffa76000 0x0 0x20>;
 };

 qos_hdcp: qos@ffa90000 {
  compatible = "syscon";
  reg = <0x0 0xffa90000 0x0 0x20>;
 };

 qos_iep: qos@ffa98000 {
  compatible = "syscon";
  reg = <0x0 0xffa98000 0x0 0x20>;
 };

 qos_isp0_m0: qos@ffaa0000 {
  compatible = "syscon";
  reg = <0x0 0xffaa0000 0x0 0x20>;
 };

 qos_isp0_m1: qos@ffaa0080 {
  compatible = "syscon";
  reg = <0x0 0xffaa0080 0x0 0x20>;
 };

 qos_isp1_m0: qos@ffaa8000 {
  compatible = "syscon";
  reg = <0x0 0xffaa8000 0x0 0x20>;
 };

 qos_isp1_m1: qos@ffaa8080 {
  compatible = "syscon";
  reg = <0x0 0xffaa8080 0x0 0x20>;
 };

 qos_rga_r: qos@ffab0000 {
  compatible = "syscon";
  reg = <0x0 0xffab0000 0x0 0x20>;
 };

 qos_rga_w: qos@ffab0080 {
  compatible = "syscon";
  reg = <0x0 0xffab0080 0x0 0x20>;
 };

 qos_video_m0: qos@ffab8000 {
  compatible = "syscon";
  reg = <0x0 0xffab8000 0x0 0x20>;
 };

 qos_video_m1_r: qos@ffac0000 {
  compatible = "syscon";
  reg = <0x0 0xffac0000 0x0 0x20>;
 };

 qos_video_m1_w: qos@ffac0080 {
  compatible = "syscon";
  reg = <0x0 0xffac0080 0x0 0x20>;
 };

 qos_vop_big_r: qos@ffac8000 {
  compatible = "syscon";
  reg = <0x0 0xffac8000 0x0 0x20>;
 };

 qos_vop_big_w: qos@ffac8080 {
  compatible = "syscon";
  reg = <0x0 0xffac8080 0x0 0x20>;
 };

 qos_vop_little: qos@ffad0000 {
  compatible = "syscon";
  reg = <0x0 0xffad0000 0x0 0x20>;
 };

 qos_perihp: qos@ffad8080 {
  compatible = "syscon";
  reg = <0x0 0xffad8080 0x0 0x20>;
 };

 qos_gpu: qos@ffae0000 {
  compatible = "syscon";
  reg = <0x0 0xffae0000 0x0 0x20>;
 };

 pmu: power-management@ff310000 {
  compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xff310000 0x0 0x1000>;
# 973 "arch/arm64/boot/dts/rockchip/rk3399.dtsi"
  power: power-controller {
   compatible = "rockchip,rk3399-power-controller";
   #power-domain-cells = <1>;
   #address-cells = <1>;
   #size-cells = <0>;


   pd_iep@34 {
    reg = <34>;
    clocks = <&cru 225>,
      <&cru 477>;
    pm_qos = <&qos_iep>;
   };
   pd_rga@33 {
    reg = <33>;
    clocks = <&cru 220>,
      <&cru 485>;
    pm_qos = <&qos_rga_r>,
      <&qos_rga_w>;
   };
   pd_vcodec@31 {
    reg = <31>;
    clocks = <&cru 235>,
      <&cru 490>;
    pm_qos = <&qos_video_m0>;
   };
   pd_vdu@32 {
    reg = <32>;
    clocks = <&cru 237>,
      <&cru 492>;
    pm_qos = <&qos_video_m1_r>,
      <&qos_video_m1_w>;
   };


   pd_gpu@35 {
    reg = <35>;
    clocks = <&cru 208>;
    pm_qos = <&qos_gpu>;
   };


   pd_edp@25 {
    reg = <25>;
    clocks = <&cru 364>;
   };
   pd_emmc@23 {
    reg = <23>;
    clocks = <&cru 240>;
    pm_qos = <&qos_emmc>;
   };
   pd_gmac@22 {
    reg = <22>;
    clocks = <&cru 213>,
      <&cru 358>;
    pm_qos = <&qos_gmac>;
   };
   pd_perihp@14 {
    reg = <14>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&cru 192>;
    pm_qos = <&qos_perihp>,
      <&qos_pcie>,
      <&qos_usb_host0>,
      <&qos_usb_host1>;

    pd_sd@27 {
     reg = <27>;
     clocks = <&cru 462>,
       <&cru 76>;
     pm_qos = <&qos_sd>;
    };
   };
   pd_sdioaudio@28 {
    reg = <28>;
    clocks = <&cru 494>;
    pm_qos = <&qos_sdioaudio>;
   };
   pd_usb3@24 {
    reg = <24>;
    clocks = <&cru 244>;
    pm_qos = <&qos_usb_otg0>,
      <&qos_usb_otg1>;
   };
   pd_vio@15 {
    reg = <15>;
    #address-cells = <1>;
    #size-cells = <0>;

    pd_hdcp@21 {
     reg = <21>;
     clocks = <&cru 222>,
       <&cru 487>,
       <&cru 370>;
     pm_qos = <&qos_hdcp>;
    };
    pd_isp0@19 {
     reg = <19>;
     clocks = <&cru 229>,
       <&cru 479>;
     pm_qos = <&qos_isp0_m0>,
       <&qos_isp0_m1>;
    };
    pd_isp1@20 {
     reg = <20>;
     clocks = <&cru 230>,
       <&cru 480>;
     pm_qos = <&qos_isp1_m0>,
       <&qos_isp1_m1>;
    };
    pd_tcpc0@RK3399_PD_TCPC0 {
     reg = <8>;
     clocks = <&cru 126>,
       <&cru 125>;
    };
    pd_tcpc1@RK3399_PD_TCPC1 {
     reg = <9>;
     clocks = <&cru 128>,
       <&cru 127>;
    };
    pd_vo@16 {
     reg = <16>;
     #address-cells = <1>;
     #size-cells = <0>;

     pd_vopb@17 {
      reg = <17>;
      clocks = <&cru 217>,
        <&cru 473>;
      pm_qos = <&qos_vop_big_r>,
        <&qos_vop_big_w>;
     };
     pd_vopl@18 {
      reg = <18>;
      clocks = <&cru 219>,
        <&cru 475>;
      pm_qos = <&qos_vop_little>;
     };
    };
   };
  };
 };

 pmugrf: syscon@ff320000 {
  compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
  reg = <0x0 0xff320000 0x0 0x1000>;
  #address-cells = <1>;
  #size-cells = <1>;

  pmu_io_domains: io-domains {
   compatible = "rockchip,rk3399-pmu-io-voltage-domain";
   status = "disabled";
  };

  reboot-mode {
   compatible = "syscon-reboot-mode";
   offset = <0x300>;
   mode-bootloader = <(0x5242C300 + 1)>;
   mode-charge = <(0x5242C300 + 11)>;
   mode-fastboot = <(0x5242C300 + 9)>;
   mode-loader = <(0x5242C300 + 1)>;
   mode-normal = <(0x5242C300 + 0)>;
   mode-recovery = <(0x5242C300 + 3)>;
   mode-ums = <(0x5242C300 + 12)>;
  };

  pmu_pvtm: pmu-pvtm {
   compatible = "rockchip,rk3399-pmu-pvtm";
   clocks = <&pmucru 7>;
   clock-names = "pmu";
   resets = <&cru 27>;
   reset-names = "pmu";
   status = "disabled";
  };
 };

 spi3: spi@ff350000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff350000 0x0 0x1000>;
  clocks = <&pmucru 3>, <&pmucru 31>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 60 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart4: serial@ff370000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff370000 0x0 0x100>;
  clocks = <&pmucru 6>, <&pmucru 34>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 102 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart4_xfer>;
  status = "disabled";
 };

 i2c4: i2c@ff3d0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3d0000 0x0 0x1000>;
  clocks = <&pmucru 10>, <&pmucru 28>;
  clock-names = "i2c", "pclk";
  interrupts = <0 56 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c4_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c8: i2c@ff3e0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3e0000 0x0 0x1000>;
  clocks = <&pmucru 11>, <&pmucru 29>;
  clock-names = "i2c", "pclk";
  interrupts = <0 58 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c8_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 pcie_phy: pcie-phy {
  compatible = "rockchip,rk3399-pcie-phy";
  #phy-cells = <0>;
  rockchip,grf = <&grf>;
  clocks = <&cru 138>;
  clock-names = "refclk";
  resets = <&cru 135>;
  reset-names = "phy";
  status = "disabled";
 };

 pcie0: pcie@f8000000 {
  compatible = "rockchip,rk3399-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  aspm-no-l0s;
  clocks = <&cru 197>, <&cru 196>,
    <&cru 327>, <&cru 160>;
  clock-names = "aclk", "aclk-perf",
         "hclk", "pm";
  bus-range = <0x0 0x1f>;
  max-link-speed = <1>;
  linux,pci-domain = <0>;
  msi-map = <0x0 &its 0x0 0x1000>;
  interrupts = <0 49 4 0>,
        <0 50 4 0>,
        <0 51 4 0>;
  interrupt-names = "sys", "legacy", "client";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie0_intc 0>,
    <0 0 0 2 &pcie0_intc 1>,
    <0 0 0 3 &pcie0_intc 2>,
    <0 0 0 4 &pcie0_intc 3>;
  phys = <&pcie_phy>;
  phy-names = "pcie-phy";
  ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
     0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
  reg = <0x0 0xf8000000 0x0 0x2000000>,
        <0x0 0xfd000000 0x0 0x1000000>;
  reg-names = "axi-base", "apb-base";
  resets = <&cru 130>, <&cru 131>,
    <&cru 132>, <&cru 133>,
    <&cru 134>, <&cru 129>,
    <&cru 128>;
  reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
         "pm", "pclk", "aclk";
  status = "disabled";
  pcie0_intc: interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
  };
 };

 pwm0: pwm@ff420000 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420000 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm0_pin>;
  clocks = <&pmucru 30>;
  clock-names = "pwm";
  status = "disabled";
 };

 pwm1: pwm@ff420010 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420010 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm1_pin>;
  clocks = <&pmucru 30>;
  clock-names = "pwm";
  status = "disabled";
 };

 pwm2: pwm@ff420020 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420020 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm2_pin>;
  clocks = <&pmucru 30>;
  clock-names = "pwm";
  status = "disabled";
 };

 pwm3: pwm@ff420030 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420030 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm3a_pin>;
  clocks = <&pmucru 30>;
  clock-names = "pwm";
  status = "disabled";
 };

 dfi: dfi@ff630000 {
  reg = <0x00 0xff630000 0x00 0x4000>;
  compatible = "rockchip,rk3399-dfi";
  rockchip,pmu = <&pmugrf>;
  clocks = <&cru 377>;
  clock-names = "pclk_ddr_mon";
  status = "disabled";
 };

 dmc: dmc {
  compatible = "rockchip,rk3399-dmc";
  devfreq-events = <&dfi>;
  interrupts = <0 1 4 0>;
  clocks = <&cru 170>;
  clock-names = "dmc_clk";
  ddr_timing = <&ddr_timing>;
  upthreshold = <40>;
  downdifferential = <20>;
  system-status-freq = <

   (1 << 0) 800000
   (1 << 3) 528000
   (1 << 1) 200000
   (1 << 5) 300000
   (1 << 4) 600000
   (1 << 16) 800000
   (1 << 13) 800000
   (1 << 12) 400000
   ((1 << 10) | (1 << 11)) 600000
   (1 << 14) 600000
  >;
  auto-min-freq = <400000>;
  auto-freq-en = <1>;
  status = "disabled";
 };

 vpu: vpu_service@ff650000 {
  compatible = "rockchip,vpu_service";
  rockchip,grf = <&grf>;
  iommus = <&vpu_mmu>;
  iommu_enabled = <1>;
  reg = <0x0 0xff650000 0x0 0x800>;
  interrupts = <0 113 4 0>,
        <0 114 4 0>;
  interrupt-names = "irq_dec", "irq_enc";
  clocks = <&cru 235>, <&cru 490>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  resets = <&cru 83>, <&cru 81>;
  reset-names = "video_h", "video_a";
  power-domains = <&power 31>;
  name = "vpu_service";
  dev_mode = <0>;

  allocator = <1>;
  status = "disabled";
 };

 vpu_mmu: iommu@ff650800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff650800 0x0 0x40>;
  interrupts = <0 115 4 0>;
  interrupt-names = "vpu_mmu";
  clocks = <&cru 235>, <&cru 490>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 31>;
  #iommu-cells = <0>;
 };

 rkvdec: rkvdec@ff660000 {
  compatible = "rockchip,rkvdec";
  rockchip,grf = <&grf>;
  iommus = <&vdec_mmu>;
  iommu_enabled = <1>;
  reg = <0x0 0xff660000 0x0 0x400>;
  interrupts = <0 116 4 0>;
  interrupt-names = "irq_dec";
  clocks = <&cru 237>, <&cru 492>,
    <&cru 159>, <&cru 158>;
  clock-names = "aclk_vcodec", "hclk_vcodec",
         "clk_cabac", "clk_core";
  resets = <&cru 91>, <&cru 89>,
   <&cru 92>, <&cru 93>,
   <&cru 88>, <&cru 90>;
  reset-names = "video_h", "video_a", "video_core", "video_cabac",
    "niu_a", "niu_h";
  power-domains = <&power 32>;
  dev_mode = <2>;
  name = "rkvdec";

  allocator = <1>;
  status = "disabled";
 };

 vdec_mmu: iommu@ff660480 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
  interrupts = <0 117 4 0>;
  interrupt-names = "vdec_mmu";
  clocks = <&cru 237>, <&cru 492>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 32>;
  #iommu-cells = <0>;
 };

 iep: iep@ff670000 {
  compatible = "rockchip,iep";
  iommu_enabled = <1>;
  iommus = <&iep_mmu>;
  reg = <0x0 0xff670000 0x0 0x800>;
  interrupts = <0 42 4 0>;
  clocks = <&cru 225>, <&cru 477>;
  clock-names = "aclk_iep", "hclk_iep";
  power-domains = <&power 34>;
  allocator = <1>;
  version = <2>;
  status = "disabled";
 };

 iep_mmu: iommu@ff670800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff670800 0x0 0x40>;
  interrupts = <0 42 4 0>;
  interrupt-names = "iep_mmu";
  #iommu-cells = <0>;
  status = "disabled";
 };

 rga: rga@ff680000 {
  compatible = "rockchip,rk3399-rga";
  reg = <0x0 0xff680000 0x0 0x10000>;
  interrupts = <0 55 4 0>;
  clocks = <&cru 220>, <&cru 485>, <&cru 109>;
  clock-names = "aclk", "hclk", "sclk";
  resets = <&cru 106>, <&cru 103>, <&cru 105>;
  reset-names = "core", "axi", "ahb";
  power-domains = <&power 33>;
  status = "disabled";
 };

 efuse0: efuse@ff690000 {
  compatible = "rockchip,rk3399-efuse";
  reg = <0x0 0xff690000 0x0 0x80>;
  #address-cells = <1>;
  #size-cells = <1>;
  clocks = <&cru 381>;
  clock-names = "pclk_efuse";


  cpu_id: cpu-id@7 {
   reg = <0x07 0x10>;
  };
  cpub_leakage: cpu-leakage@17 {
   reg = <0x17 0x1>;
  };
  gpu_leakage: gpu-leakage@18 {
   reg = <0x18 0x1>;
  };
  center_leakage: center-leakage@19 {
   reg = <0x19 0x1>;
  };
  cpul_leakage: cpu-leakage@1a {
   reg = <0x1a 0x1>;
  };
  logic_leakage: logic-leakage@1b {
   reg = <0x1b 0x1>;
  };
  wafer_info: wafer-info@1c {
   reg = <0x1c 0x1>;
  };
 };

 pmucru: pmu-clock-controller@ff750000 {
  compatible = "rockchip,rk3399-pmucru";
  reg = <0x0 0xff750000 0x0 0x1000>;
  #clock-cells = <1>;
  #reset-cells = <1>;
  assigned-clocks = <&pmucru 1>, <&pmucru 44>;
  assigned-clock-rates = <676000000>, <97000000>;
 };

 cru: clock-controller@ff760000 {
  compatible = "rockchip,rk3399-cru";
  reg = <0x0 0xff760000 0x0 0x1000>;
  #clock-cells = <1>;
  #reset-cells = <1>;
  assigned-clocks =
   <&cru 217>, <&cru 473>,
   <&cru 219>, <&cru 475>,
   <&cru 8>, <&cru 9>,
   <&cru 5>, <&cru 4>,
   <&cru 208>, <&cru 6>,
   <&cru 192>, <&cru 448>,
   <&cru 320>,
   <&cru 194>, <&cru 449>,
   <&cru 322>, <&cru 201>,
   <&cru 450>, <&cru 323>,
   <&cru 227>, <&cru 222>,
   <&cru 262>,
   <&cru 376>;
  assigned-clock-rates =
    <400000000>, <200000000>,
    <400000000>, <200000000>,
    <816000000>, <816000000>,
    <594000000>, <800000000>,
    <200000000>, <1000000000>,
    <150000000>, <75000000>,
     <37500000>,
    <100000000>, <100000000>,
     <50000000>, <600000000>,
    <100000000>, <50000000>,
    <400000000>, <400000000>,
    <200000000>,
    <200000000>;
 };

 grf: syscon@ff770000 {
  compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
  reg = <0x0 0xff770000 0x0 0x10000>;
  #address-cells = <1>;
  #size-cells = <1>;

  io_domains: io-domains {
   compatible = "rockchip,rk3399-io-voltage-domain";
   status = "disabled";
  };

  u2phy0: usb2-phy@e450 {
   compatible = "rockchip,rk3399-usb2phy";
   reg = <0xe450 0x10>;
   clocks = <&cru 123>;
   clock-names = "phyclk";
   #clock-cells = <0>;
   clock-output-names = "clk_usbphy0_480m";
   status = "disabled";

   u2phy0_host: host-port {
    #phy-cells = <0>;
    interrupts = <0 27 4 0>;
    interrupt-names = "linestate";
    status = "disabled";
   };

   u2phy0_otg: otg-port {
    #phy-cells = <0>;
    interrupts = <0 103 4 0>,
          <0 104 4 0>,
          <0 106 4 0>;
    interrupt-names = "otg-bvalid", "otg-id",
        "linestate";
    status = "disabled";
   };
  };

  u2phy1: usb2-phy@e460 {
   compatible = "rockchip,rk3399-usb2phy";
   reg = <0xe460 0x10>;
   clocks = <&cru 124>;
   clock-names = "phyclk";
   #clock-cells = <0>;
   clock-output-names = "clk_usbphy1_480m";
   status = "disabled";

   u2phy1_host: host-port {
    #phy-cells = <0>;
    interrupts = <0 31 4 0>;
    interrupt-names = "linestate";
    status = "disabled";
   };

   u2phy1_otg: otg-port {
    #phy-cells = <0>;
    interrupts = <0 108 4 0>,
          <0 109 4 0>,
          <0 111 4 0>;
    interrupt-names = "otg-bvalid", "otg-id",
        "linestate";
    status = "disabled";
   };
  };

  emmc_phy: phy@f780 {
   compatible = "rockchip,rk3399-emmc-phy";
   reg = <0xf780 0x24>;
   clocks = <&sdhci>;
   clock-names = "emmcclk";
   #phy-cells = <0>;
   status = "disabled";
  };

  mipi_dphy_rx0: mipi-dphy-rx0 {
   compatible = "rockchip,rk3399-mipi-dphy";
   clocks = <&cru 119>,
    <&cru 165>,
    <&cru 367>;
   clock-names = "dphy-ref", "dphy-cfg", "grf";
   power-domains = <&power 15>;
   status = "disabled";
  };

  pvtm: pvtm {
   compatible = "rockchip,rk3399-pvtm";
   clocks = <&cru 115>,
     <&cru 116>,
     <&cru 117>,
     <&cru 118>;
   clock-names = "core_l", "core_b", "gpu", "ddr";
   resets = <&cru 31>,
     <&cru 47>,
     <&cru 291>,
     <&cru 79>;
   reset-names = "core_l", "core_b", "gpu", "ddr";
   status = "disabled";
  };
 };

 tcphy0: phy@ff7c0000 {
  compatible = "rockchip,rk3399-typec-phy";
  reg = <0x0 0xff7c0000 0x0 0x40000>;
  #phy-cells = <1>;
  clocks = <&cru 126>,
    <&cru 125>;
  clock-names = "tcpdcore", "tcpdphy-ref";
  assigned-clocks = <&cru 126>;
  assigned-clock-rates = <50000000>;
  power-domains = <&power 8>;
  resets = <&cru 149>,
    <&cru 148>,
    <&cru 332>;
  reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
  rockchip,grf = <&grf>;
  rockchip,typec-conn-dir = <0xe580 0 16>;
  rockchip,usb3tousb2-en = <0xe580 3 19>;
  rockchip,usb3-host-disable = <0x2434 0 16>;
  rockchip,usb3-host-port = <0x2434 12 28>;
  rockchip,external-psm = <0xe588 14 30>;
  rockchip,pipe-status = <0xe5c0 0 0>;
  rockchip,uphy-dp-sel = <0x6268 19 19>;
  status = "disabled";

  tcphy0_dp: dp-port {
   #phy-cells = <0>;
  };

  tcphy0_usb3: usb3-port {
   #phy-cells = <0>;
  };
 };

 tcphy1: phy@ff800000 {
  compatible = "rockchip,rk3399-typec-phy";
  reg = <0x0 0xff800000 0x0 0x40000>;
  #phy-cells = <1>;
  clocks = <&cru 128>,
    <&cru 127>;
  clock-names = "tcpdcore", "tcpdphy-ref";
  assigned-clocks = <&cru 128>;
  assigned-clock-rates = <50000000>;
  power-domains = <&power 9>;
  resets = <&cru 157>,
    <&cru 156>,
    <&cru 333>;
  reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
  rockchip,grf = <&grf>;
  rockchip,typec-conn-dir = <0xe58c 0 16>;
  rockchip,usb3tousb2-en = <0xe58c 3 19>;
  rockchip,usb3-host-disable = <0x2444 0 16>;
  rockchip,usb3-host-port = <0x2444 12 28>;
  rockchip,external-psm = <0xe594 14 30>;
  rockchip,pipe-status = <0xe5c0 16 16>;
  rockchip,uphy-dp-sel = <0x6268 3 19>;
  status = "disabled";

  tcphy1_dp: dp-port {
   #phy-cells = <0>;
  };

  tcphy1_usb3: usb3-port {
   #phy-cells = <0>;
  };
 };

 watchdog@ff848000 {
  compatible = "snps,dw-wdt";
  reg = <0x0 0xff848000 0x0 0x100>;
  clocks = <&cru 380>;
  interrupts = <0 120 4 0>;
 };

 rktimer: rktimer@ff850000 {
  compatible = "rockchip,rk3399-timer";
  reg = <0x0 0xff850000 0x0 0x1000>;
  interrupts = <0 81 4 0>;
  clocks = <&cru 360>, <&cru 90>;
  clock-names = "pclk", "timer";
 };

 spdif: spdif@ff870000 {
  compatible = "rockchip,rk3399-spdif";
  reg = <0x0 0xff870000 0x0 0x1000>;
  interrupts = <0 66 4 0>;
  dmas = <&dmac_bus 7>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 85>, <&cru 471>;
  pinctrl-names = "default";
  pinctrl-0 = <&spdif_bus>;
  power-domains = <&power 28>;
  status = "disabled";
 };

 i2s0: i2s@ff880000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff880000 0x0 0x1000>;
  rockchip,grf = <&grf>;
  interrupts = <0 39 4 0>;
  dmas = <&dmac_bus 0>, <&dmac_bus 1>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 86>, <&cru 468>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s0_8ch_bus>;
  power-domains = <&power 28>;
  status = "disabled";
 };

 i2s1: i2s@ff890000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff890000 0x0 0x1000>;
  interrupts = <0 40 4 0>;
  dmas = <&dmac_bus 2>, <&dmac_bus 3>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 87>, <&cru 469>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s1_2ch_bus>;
  power-domains = <&power 28>;
  status = "disabled";
 };

 i2s2: i2s@ff8a0000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff8a0000 0x0 0x1000>;
  interrupts = <0 41 4 0>;
  dmas = <&dmac_bus 4>, <&dmac_bus 5>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 88>, <&cru 470>;
  power-domains = <&power 28>;
  status = "disabled";
 };

 gpu: gpu@ff9a0000 {
  compatible = "arm,malit860",
        "arm,malit86x",
        "arm,malit8xx",
        "arm,mali-midgard";

  reg = <0x0 0xff9a0000 0x0 0x10000>;

  interrupts = <0 19 4 0>,
        <0 20 4 0>,
        <0 21 4 0>;
  interrupt-names = "GPU", "JOB", "MMU";

  clocks = <&cru 208>;
  clock-names = "clk_mali";
  #cooling-cells = <2>;
  power-domains = <&power 35>;
  power-off-delay-ms = <200>;
  status = "disabled";

  gpu_power_model: power_model {
   compatible = "arm,mali-simple-power-model";
   static-coefficient = <411000>;
   dynamic-coefficient = <733>;
   ts = <32000 4700 (-80) 2>;
   thermal-zone = "gpu-thermal";
  };
 };

 vopl: vop@ff8f0000 {
  compatible = "rockchip,rk3399-vop-lit";
  reg = <0x0 0xff8f0000 0x0 0x600>,
   <0x0 0xff8f1c00 0x0 0x200>,
   <0x0 0xff8f2000 0x0 0x400>;
  reg-names = "regs", "cabc_lut", "gamma_lut";
  interrupts = <0 119 4 0>;
  clocks = <&cru 219>, <&cru 181>, <&cru 475>, <&cru 183>;
  clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
  iommus = <&vopl_mmu>;
  power-domains = <&power 18>;
  resets = <&cru 275>, <&cru 279>, <&cru 281>;
  reset-names = "axi", "ahb", "dclk";
  status = "disabled";

  vopl_out: port {
   #address-cells = <1>;
   #size-cells = <0>;

   vopl_out_dsi: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&dsi_in_vopl>;
   };

   vopl_out_edp: endpoint@1 {
    reg = <1>;
    remote-endpoint = <&edp_in_vopl>;
   };

   vopl_out_hdmi: endpoint@2 {
    reg = <2>;
    remote-endpoint = <&hdmi_in_vopl>;
   };

   vopl_out_dp: endpoint@3 {
    reg = <3>;
    remote-endpoint = <&dp_in_vopl>;
   };

   vopl_out_dsi1: endpoint@4 {
    reg = <4>;
    remote-endpoint = <&dsi1_in_vopl>;
   };
  };
 };

 vop1_pwm: voppwm@ff8f01a0 {
  compatible = "rockchip,vop-pwm";
  reg = <0x0 0xff8f01a0 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&vop1_pwm_pin>;
  clocks = <&cru 108>;
  clock-names = "pwm";
  status = "disabled";
 };

 vopl_mmu: iommu@ff8f3f00 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff8f3f00 0x0 0x100>;
  interrupts = <0 119 4 0>;
  interrupt-names = "vopl_mmu";
  clocks = <&cru 219>, <&cru 475>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 18>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 vopb: vop@ff900000 {
  compatible = "rockchip,rk3399-vop-big";
  reg = <0x0 0xff900000 0x0 0x600>,
   <0x0 0xff901c00 0x0 0x200>,
   <0x0 0xff902000 0x0 0x1000>;
  reg-names = "regs", "cabc_lut", "gamma_lut";
  interrupts = <0 118 4 0>;
  clocks = <&cru 217>, <&cru 180>, <&cru 473>, <&cru 182>;
  clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
  resets = <&cru 274>, <&cru 278>, <&cru 280>;
  reset-names = "axi", "ahb", "dclk";
  power-domains = <&power 17>;
  iommus = <&vopb_mmu>;
  status = "disabled";

  vopb_out: port {
   #address-cells = <1>;
   #size-cells = <0>;

   vopb_out_edp: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&edp_in_vopb>;
   };

   vopb_out_dsi: endpoint@1 {
    reg = <1>;
    remote-endpoint = <&dsi_in_vopb>;
   };

   vopb_out_hdmi: endpoint@2 {
    reg = <2>;
    remote-endpoint = <&hdmi_in_vopb>;
   };

   vopb_out_dp: endpoint@3 {
    reg = <3>;
    remote-endpoint = <&dp_in_vopb>;
   };

   vopb_out_dsi1: endpoint@4 {
    reg = <4>;
    remote-endpoint = <&dsi1_in_vopb>;
   };
  };
 };

 vop0_pwm: voppwm@ff9001a0 {
  compatible = "rockchip,vop-pwm";
  reg = <0x0 0xff9001a0 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&vop0_pwm_pin>;
  clocks = <&cru 107>;
  clock-names = "pwm";
  status = "disabled";
 };

 vopb_mmu: iommu@ff903f00 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff903f00 0x0 0x100>;
  interrupts = <0 118 4 0>;
  interrupt-names = "vopb_mmu";
  clocks = <&cru 217>, <&cru 473>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 17>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 rkisp1_0: rkisp1@ff910000 {
  compatible = "rockchip,rk3399-rkisp1";
  reg = <0x0 0xff910000 0x0 0x4000>;
  interrupts = <0 43 4 0>;
  clocks = <&cru 110>,
    <&cru 229>, <&cru 479>,
    <&cru 233>, <&cru 483>;
  clock-names = "clk_isp",
    "aclk_isp", "hclk_isp",
    "aclk_isp_wrap", "hclk_isp_wrap";
  devfreq = <&dmc>;
  power-domains = <&power 19>;
  iommus = <&isp0_mmu>;
  status = "disabled";
 };

 isp0_mmu: iommu@ff914000 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
  interrupts = <0 43 4 0>;
  interrupt-names = "isp0_mmu";
  #iommu-cells = <0>;
  clocks = <&cru 233>, <&cru 483>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 19>;
  rk_iommu,disable_reset_quirk;
  status = "disabled";
 };

 rkisp1_1: rkisp1@ff920000 {
  compatible = "rockchip,rk3399-rkisp1";
  reg = <0x0 0xff920000 0x0 0x4000>;
  interrupts = <0 44 4 0>;
  clocks = <&cru 111>,
    <&cru 230>, <&cru 480>,
    <&cru 234>, <&cru 484>,
    <&cru 379>;
  clock-names = "clk_isp",
    "aclk_isp", "hclk_isp",
    "aclk_isp_wrap", "hclk_isp_wrap",
    "pclk_isp_wrap";
  devfreq = <&dmc>;
  power-domains = <&power 20>;
  iommus = <&isp1_mmu>;
  status = "disabled";
 };

 isp1_mmu: iommu@ff924000 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
  interrupts = <0 44 4 0>;
  interrupt-names = "isp1_mmu";
  #iommu-cells = <0>;
  clocks = <&cru 234>, <&cru 484>;
  clock-names = "aclk", "hclk";
  power-domains = <&power 20>;
  rk_iommu,disable_reset_quirk;
  status = "disabled";
 };

 hdmi: hdmi@ff940000 {
  compatible = "rockchip,rk3399-dw-hdmi";
  reg = <0x0 0xff940000 0x0 0x20000>;
  pinctrl-names = "default";
  pinctrl-0 = <&hdmi_i2c_xfer>;
  interrupts = <0 23 4 0>;
  clocks = <&cru 372>,
    <&cru 113>,
    <&cru 7>,
    <&cru 367>;
  clock-names = "iahb", "isfr", "vpll", "grf";
  power-domains = <&power 21>;
  reg-io-width = <4>;
  rockchip,grf = <&grf>;
  status = "okay";

  ports {
   hdmi_in: port {
    #address-cells = <1>;
    #size-cells = <0>;
    hdmi_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_hdmi>;
    };
    hdmi_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_hdmi>;
    };
   };
  };
 };

 dsi: dsi@ff960000 {
  compatible = "rockchip,rk3399-mipi-dsi";
  reg = <0x0 0xff960000 0x0 0x8000>;
  interrupts = <0 45 4 0>;
  clocks = <&cru 162>, <&cru 368>,
    <&cru 163>;
  clock-names = "ref", "pclk", "phy_cfg";
  power-domains = <&power 15>;
  resets = <&cru 251>;
  reset-names = "apb";
  rockchip,grf = <&grf>;
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;

  ports {
   port {
    #address-cells = <1>;
    #size-cells = <0>;

    dsi_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_dsi>;
    };

    dsi_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_dsi>;
    };
   };
  };
 };

 dsi1: dsi@ff968000 {
  compatible = "rockchip,rk3399-mipi-dsi";
  reg = <0x0 0xff968000 0x0 0x8000>;
  interrupts = <0 46 4 0>;
  clocks = <&cru 162>, <&cru 369>,
    <&cru 164>;
  clock-names = "ref", "pclk", "phy_cfg";
  power-domains = <&power 15>;
  resets = <&cru 252>;
  reset-names = "apb";
  rockchip,grf = <&grf>;
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;

  ports {
   port {
    #address-cells = <1>;
    #size-cells = <0>;

    dsi1_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_dsi1>;
    };

    dsi1_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_dsi1>;
    };
   };
  };
 };

 mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@0xff968000 {
  compatible = "rockchip,rk3399-mipi-dphy";
  reg = <0x0 0xff968000 0x0 0x8000>;
  clocks = <&cru 119>,
   <&cru 164>,
   <&cru 367>,
   <&cru 369>;
  clock-names = "dphy-ref", "dphy-cfg",
   "grf", "pclk_mipi_dsi";
  rockchip,grf = <&grf>;
  power-domains = <&power 15>;
  status = "disabled";
 };

 edp: edp@ff970000 {
  compatible = "rockchip,rk3399-edp";
  reg = <0x0 0xff970000 0x0 0x8000>;
  interrupts = <0 10 4 0>;
  clocks = <&cru 362>, <&cru 364>;
  clock-names = "dp", "pclk";
  power-domains = <&power 25>;
  resets = <&cru 285>;
  reset-names = "dp";
  rockchip,grf = <&grf>;
  status = "disabled";
  pinctrl-names = "default";
  pinctrl-0 = <&edp_hpd>;

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   edp_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    edp_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_edp>;
    };

    edp_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_edp>;
    };
   };
  };
 };

 hdmi_hdcp2: hdmi-hdcp2@ff988000 {
  compatible = "rockchip,rk3399-hdmi-hdcp2";
  reg = <0x0 0xff988000 0x0 0x2000>;
  interrupts = <0 22 4 0>;
  clocks = <&cru 224>, <&cru 374>,
    <&cru 489>;
  clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
  status = "disabled";
 };

 display_subsystem: display-subsystem {
  compatible = "rockchip,display-subsystem";
  ports = <&vopl_out>, <&vopb_out>;
  clocks = <&cru 7>, <&cru 4>;
  clock-names = "hdmi-tmds-pll", "default-vop-pll";
  devfreq = <&dmc>;
  status = "okay";
 };

 nocp_cci_msch0: nocp-cci-msch0@ffa86000 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa86000 0x0 0x400>;
 };

 nocp_gpu_msch0: nocp-gpu-msch0@ffa86400 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa86400 0x0 0x400>;
 };

 nocp_hp_msch0: nocp-hp-msch0@ffa86800 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa86800 0x0 0x400>;
 };

 nocp_lp_msch0: nocp-lp-msch0@ffa86c00 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa86c00 0x0 0x400>;
 };

 nocp_video_msch0: nocp-video-msch0@ffa87000 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa87000 0x0 0x400>;
 };

 nocp_vio0_msch0: nocp-vio0-msch0@ffa87400 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa87400 0x0 0x400>;
 };

 nocp_vio1_msch0: nocp-vio1-msch0@ffa87800 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa87800 0x0 0x400>;
 };

 nocp_cci_msch1: nocp-cci-msch1@ffa8e000 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8e000 0x0 0x400>;
 };

 nocp_gpu_msch1: nocp-gpu-msch1@ffa8e400 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8e400 0x0 0x400>;
 };

 nocp_hp_msch1: nocp-hp-msch1@ffa8e800 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8e800 0x0 0x400>;
 };

 nocp_lp_msch1: nocp-lp-msch1@ffa8ec00 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8ec00 0x0 0x400>;
 };

 nocp_video_msch1: nocp-video-msch1@ffa8f000 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8f000 0x0 0x400>;
 };

 nocp_vio0_msch1: nocp-vio0-msch1@ffa8f400 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8f400 0x0 0x400>;
 };

 nocp_vio1_msch1: nocp-vio1-msch1@ffa8f800 {
  compatible = "rockchip,rk3399-nocp";
  reg = <0x0 0xffa8f800 0x0 0x400>;
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3399-pinctrl";
  rockchip,grf = <&grf>;
  rockchip,pmu = <&pmugrf>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  gpio0: gpio0@ff720000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff720000 0x0 0x100>;
   clocks = <&pmucru 23>;
   interrupts = <0 14 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio1: gpio1@ff730000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff730000 0x0 0x100>;
   clocks = <&pmucru 24>;
   interrupts = <0 15 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio2: gpio2@ff780000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff780000 0x0 0x100>;
   clocks = <&cru 336>;
   interrupts = <0 16 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio3: gpio3@ff788000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff788000 0x0 0x100>;
   clocks = <&cru 337>;
   interrupts = <0 17 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio4: gpio4@ff790000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff790000 0x0 0x100>;
   clocks = <&cru 338>;
   interrupts = <0 18 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  pcfg_pull_up: pcfg-pull-up {
   bias-pull-up;
  };

  pcfg_pull_down: pcfg-pull-down {
   bias-pull-down;
  };

  pcfg_pull_none: pcfg-pull-none {
   bias-disable;
  };

  pcfg_pull_up_20ma: pcfg-pull-up-20ma {
   bias-pull-up;
   drive-strength = <20>;
  };

  pcfg_pull_none_20ma: pcfg-pull-none-20ma {
   bias-disable;
   drive-strength = <20>;
  };

  pcfg_pull_none_18ma: pcfg-pull-none-18ma {
   bias-disable;
   drive-strength = <18>;
  };

  pcfg_pull_none_12ma: pcfg-pull-none-12ma {
   bias-disable;
   drive-strength = <12>;
  };

  pcfg_pull_up_8ma: pcfg-pull-up-8ma {
   bias-pull-up;
   drive-strength = <8>;
  };

  pcfg_pull_down_4ma: pcfg-pull-down-4ma {
   bias-pull-down;
   drive-strength = <4>;
  };

  pcfg_pull_up_2ma: pcfg-pull-up-2ma {
   bias-pull-up;
   drive-strength = <2>;
  };

  pcfg_pull_down_12ma: pcfg-pull-down-12ma {
   bias-pull-down;
   drive-strength = <12>;
  };

  pcfg_pull_none_13ma: pcfg-pull-none-13ma {
   bias-disable;
   drive-strength = <13>;
  };

  pcfg_output_high: pcfg-output-high {
   output-high;
  };

  pcfg_output_low: pcfg-output-low {
   output-low;
  };

  pcfg_input: pcfg-input {
   input-enable;
  };

  emmc {
   emmc_pwr: emmc-pwr {
    rockchip,pins =
     <0 5 1 &pcfg_pull_up>;
   };
  };

  gmac {
   rgmii_pins: rgmii-pins {
    rockchip,pins =

     <3 17 1 &pcfg_pull_none_13ma>,

     <3 14 1 &pcfg_pull_none>,

     <3 13 1 &pcfg_pull_none>,

     <3 12 1 &pcfg_pull_none_13ma>,

     <3 11 1 &pcfg_pull_none>,

     <3 9 1 &pcfg_pull_none>,

     <3 8 1 &pcfg_pull_none>,

     <3 7 1 &pcfg_pull_none>,

     <3 6 1 &pcfg_pull_none>,

     <3 5 1 &pcfg_pull_none_13ma>,

     <3 4 1 &pcfg_pull_none_13ma>,

     <3 3 1 &pcfg_pull_none>,

     <3 2 1 &pcfg_pull_none>,

     <3 1 1 &pcfg_pull_none_13ma>,

     <3 0 1 &pcfg_pull_none_13ma>;
   };

   rmii_pins: rmii-pins {
    rockchip,pins =

     <3 13 1 &pcfg_pull_none>,

     <3 12 1 &pcfg_pull_none_13ma>,

     <3 11 1 &pcfg_pull_none>,

     <3 10 1 &pcfg_pull_none>,

     <3 9 1 &pcfg_pull_none>,

     <3 8 1 &pcfg_pull_none>,

     <3 7 1 &pcfg_pull_none>,

     <3 6 1 &pcfg_pull_none>,

     <3 5 1 &pcfg_pull_none_13ma>,

     <3 4 1 &pcfg_pull_none_13ma>;
   };
  };

  i2c0 {
   i2c0_xfer: i2c0-xfer {
    rockchip,pins =
     <1 15 2 &pcfg_pull_none>,
     <1 16 2 &pcfg_pull_none>;
   };
  };

  i2c1 {
   i2c1_xfer: i2c1-xfer {
    rockchip,pins =
     <4 2 1 &pcfg_pull_none>,
     <4 1 1 &pcfg_pull_none>;
   };
  };

  i2c2 {
   i2c2_xfer: i2c2-xfer {
    rockchip,pins =
     <2 1 2 &pcfg_pull_none_12ma>,
     <2 0 2 &pcfg_pull_none_12ma>;
   };
  };

  i2c3 {
   i2c3_xfer: i2c3-xfer {
    rockchip,pins =
     <4 17 1 &pcfg_pull_none>,
     <4 16 1 &pcfg_pull_none>;
   };

   i2c3_gpio: i2c3_gpio {
    rockchip,pins =
     <4 17 0 &pcfg_pull_none>,
     <4 16 0 &pcfg_pull_none>;
   };

  };

  i2c4 {
   i2c4_xfer: i2c4-xfer {
    rockchip,pins =
     <1 12 1 &pcfg_pull_none>,
     <1 11 1 &pcfg_pull_none>;
   };
  };

  i2c5 {
   i2c5_xfer: i2c5-xfer {
    rockchip,pins =
     <3 11 2 &pcfg_pull_none>,
     <3 10 2 &pcfg_pull_none>;
   };
  };

  i2c6 {
   i2c6_xfer: i2c6-xfer {
    rockchip,pins =
     <2 10 2 &pcfg_pull_none>,
     <2 9 2 &pcfg_pull_none>;
   };
  };

  i2c7 {
   i2c7_xfer: i2c7-xfer {
    rockchip,pins =
     <2 8 2 &pcfg_pull_none>,
     <2 7 2 &pcfg_pull_none>;
   };
  };

  i2c8 {
   i2c8_xfer: i2c8-xfer {
    rockchip,pins =
     <1 21 1 &pcfg_pull_none>,
     <1 20 1 &pcfg_pull_none>;
   };
  };

  i2s0 {
   i2s0_8ch_bus: i2s0-8ch-bus {
    rockchip,pins =
     <3 24 1 &pcfg_pull_none>,
     <3 25 1 &pcfg_pull_none>,
     <3 26 1 &pcfg_pull_none>,
     <3 27 1 &pcfg_pull_none>,
     <3 28 1 &pcfg_pull_none>,
     <3 29 1 &pcfg_pull_none>,
     <3 30 1 &pcfg_pull_none>,
     <3 31 1 &pcfg_pull_none>;
   };

   i2s_8ch_mclk: i2s-8ch-mclk {
    rockchip,pins = <4 0 1 &pcfg_pull_none>;
   };
  };

  i2s1 {
   i2s1_2ch_bus: i2s1-2ch-bus {
    rockchip,pins =
     <4 3 1 &pcfg_pull_none>,
     <4 4 1 &pcfg_pull_none>,
     <4 5 1 &pcfg_pull_none>,
     <4 6 1 &pcfg_pull_none>,
     <4 7 1 &pcfg_pull_none>;
   };
  };

  sdio0 {
   sdio0_bus1: sdio0-bus1 {
    rockchip,pins =
     <2 20 1 &pcfg_pull_up>;
   };

   sdio0_bus4: sdio0-bus4 {
    rockchip,pins =
     <2 20 1 &pcfg_pull_up>,
     <2 21 1 &pcfg_pull_up>,
     <2 22 1 &pcfg_pull_up>,
     <2 23 1 &pcfg_pull_up>;
   };

   sdio0_cmd: sdio0-cmd {
    rockchip,pins =
     <2 24 1 &pcfg_pull_up>;
   };

   sdio0_clk: sdio0-clk {
    rockchip,pins =
     <2 25 1 &pcfg_pull_none>;
   };

   sdio0_cd: sdio0-cd {
    rockchip,pins =
     <2 26 1 &pcfg_pull_up>;
   };

   sdio0_pwr: sdio0-pwr {
    rockchip,pins =
     <2 27 1 &pcfg_pull_up>;
   };

   sdio0_bkpwr: sdio0-bkpwr {
    rockchip,pins =
     <2 28 1 &pcfg_pull_up>;
   };

   sdio0_wp: sdio0-wp {
    rockchip,pins =
     <0 3 1 &pcfg_pull_up>;
   };

   sdio0_int: sdio0-int {
    rockchip,pins =
     <0 4 1 &pcfg_pull_up>;
   };
  };

  sdmmc {
   sdmmc_bus1: sdmmc-bus1 {
    rockchip,pins =
     <4 8 1 &pcfg_pull_up>;
   };

   sdmmc_bus4: sdmmc-bus4 {
    rockchip,pins =
     <4 8 1 &pcfg_pull_up>,
     <4 9 1 &pcfg_pull_up>,
     <4 10 1 &pcfg_pull_up>,
     <4 11 1 &pcfg_pull_up>;
   };

   sdmmc_clk: sdmmc-clk {
    rockchip,pins =
     <4 12 1 &pcfg_pull_none>;
   };

   sdmmc_cmd: sdmmc-cmd {
    rockchip,pins =
     <4 13 1 &pcfg_pull_up>;
   };

   sdmmc_cd: sdmcc-cd {
    rockchip,pins =
     <0 7 1 &pcfg_pull_up>;
   };

   sdmmc_wp: sdmmc-wp {
    rockchip,pins =
     <0 8 1 &pcfg_pull_up>;
   };
  };

  spdif {
   spdif_bus: spdif-bus {
    rockchip,pins =
     <4 21 1 &pcfg_pull_none>;
   };

   spdif_bus_1: spdif-bus-1 {
    rockchip,pins =
     <3 16 3 &pcfg_pull_none>;
   };
  };

  spi0 {
   spi0_clk: spi0-clk {
    rockchip,pins =
     <3 6 2 &pcfg_pull_up>;
   };
   spi0_cs0: spi0-cs0 {
    rockchip,pins =
     <3 7 2 &pcfg_pull_up>;
   };
   spi0_cs1: spi0-cs1 {
    rockchip,pins =
     <3 8 2 &pcfg_pull_up>;
   };
   spi0_tx: spi0-tx {
    rockchip,pins =
     <3 5 2 &pcfg_pull_up>;
   };
   spi0_rx: spi0-rx {
    rockchip,pins =
     <3 4 2 &pcfg_pull_up>;
   };
  };

  spi1 {
   spi1_clk: spi1-clk {
    rockchip,pins =
     <1 9 2 &pcfg_pull_up>;
   };
   spi1_cs0: spi1-cs0 {
    rockchip,pins =
     <1 10 2 &pcfg_pull_up>;
   };
   spi1_rx: spi1-rx {
    rockchip,pins =
     <1 7 2 &pcfg_pull_up>;
   };
   spi1_tx: spi1-tx {
    rockchip,pins =
     <1 8 2 &pcfg_pull_up>;
   };
  };

  spi2 {
   spi2_clk: spi2-clk {
    rockchip,pins =
     <2 11 1 &pcfg_pull_up>;
   };
   spi2_cs0: spi2-cs0 {
    rockchip,pins =
     <2 12 1 &pcfg_pull_up>;
   };
   spi2_rx: spi2-rx {
    rockchip,pins =
     <2 9 1 &pcfg_pull_up>;
   };
   spi2_tx: spi2-tx {
    rockchip,pins =
     <2 10 1 &pcfg_pull_up>;
   };
  };

  spi3 {
   spi3_clk: spi3-clk {
    rockchip,pins =
     <1 17 1 &pcfg_pull_up>;
   };
   spi3_cs0: spi3-cs0 {
    rockchip,pins =
     <1 18 1 &pcfg_pull_up>;
   };
   spi3_rx: spi3-rx {
    rockchip,pins =
     <1 15 1 &pcfg_pull_up>;
   };
   spi3_tx: spi3-tx {
    rockchip,pins =
     <1 16 1 &pcfg_pull_up>;
   };
  };

  spi4 {
   spi4_clk: spi4-clk {
    rockchip,pins =
     <3 2 2 &pcfg_pull_up>;
   };
   spi4_cs0: spi4-cs0 {
    rockchip,pins =
     <3 3 2 &pcfg_pull_up>;
   };
   spi4_rx: spi4-rx {
    rockchip,pins =
     <3 0 2 &pcfg_pull_up>;
   };
   spi4_tx: spi4-tx {
    rockchip,pins =
     <3 1 2 &pcfg_pull_up>;
   };
  };

  spi5 {
   spi5_clk: spi5-clk {
    rockchip,pins =
     <2 22 2 &pcfg_pull_up>;
   };
   spi5_cs0: spi5-cs0 {
    rockchip,pins =
     <2 23 2 &pcfg_pull_up>;
   };
   spi5_rx: spi5-rx {
    rockchip,pins =
     <2 20 2 &pcfg_pull_up>;
   };
   spi5_tx: spi5-tx {
    rockchip,pins =
     <2 21 2 &pcfg_pull_up>;
   };
  };

  tsadc {
   otp_gpio: otp-gpio {
    rockchip,pins = <1 6 0 &pcfg_pull_none>;
   };

   otp_out: otp-out {
    rockchip,pins = <1 6 1 &pcfg_pull_none>;
   };
  };

  uart0 {
   uart0_xfer: uart0-xfer {
    rockchip,pins =
     <2 16 1 &pcfg_pull_up>,
     <2 17 1 &pcfg_pull_none>;
   };

   uart0_cts: uart0-cts {
    rockchip,pins =
     <2 18 1 &pcfg_pull_none>;
   };

   uart0_rts: uart0-rts {
    rockchip,pins =
     <2 19 1 &pcfg_pull_none>;
   };
  };

  uart1 {
   uart1_xfer: uart1-xfer {
    rockchip,pins =
     <3 12 2 &pcfg_pull_up>,
     <3 13 2 &pcfg_pull_none>;
   };
  };

  uart2a {
   uart2a_xfer: uart2a-xfer {
    rockchip,pins =
     <4 8 2 &pcfg_pull_up>,
     <4 9 2 &pcfg_pull_none>;
   };
  };

  uart2b {
   uart2b_xfer: uart2b-xfer {
    rockchip,pins =
     <4 16 2 &pcfg_pull_up>,
     <4 17 2 &pcfg_pull_none>;
   };
  };

  uart2c {
   uart2c_xfer: uart2c-xfer {
    rockchip,pins =
     <4 19 1 &pcfg_pull_up>,
     <4 20 1 &pcfg_pull_none>;
   };
  };

  uart3 {
   uart3_xfer: uart3-xfer {
    rockchip,pins =
     <3 14 2 &pcfg_pull_up>,
     <3 15 2 &pcfg_pull_none>;
   };

   uart3_cts: uart3-cts {
    rockchip,pins =
     <3 18 2 &pcfg_pull_none>;
   };

   uart3_rts: uart3-rts {
    rockchip,pins =
     <3 19 2 &pcfg_pull_none>;
   };
  };

  uart4 {
   uart4_xfer: uart4-xfer {
    rockchip,pins =
     <1 7 1 &pcfg_pull_up>,
     <1 8 1 &pcfg_pull_none>;
   };
  };

  uarthdcp {
   uarthdcp_xfer: uarthdcp-xfer {
    rockchip,pins =
     <4 21 2 &pcfg_pull_up>,
     <4 22 2 &pcfg_pull_none>;
   };
  };

  pwm0 {
   pwm0_pin: pwm0-pin {
    rockchip,pins =
     <4 18 1 &pcfg_pull_none>;
   };

   pwm0_pin_pull_down: pwm0-pin-pull-down {
    rockchip,pins =
     <4 18 1 &pcfg_pull_down>;
   };

   vop0_pwm_pin: vop0-pwm-pin {
    rockchip,pins =
     <4 18 2 &pcfg_pull_none>;
   };

   vop1_pwm_pin: vop1-pwm-pin {
    rockchip,pins =
     <4 18 3 &pcfg_pull_none>;
   };
  };

  pwm1 {
   pwm1_pin: pwm1-pin {
    rockchip,pins =
     <4 22 1 &pcfg_pull_none>;
   };

   pwm1_pin_pull_down: pwm1-pin-pull-down {
    rockchip,pins =
     <4 22 1 &pcfg_pull_down>;
   };
  };

  pwm2 {
   pwm2_pin: pwm2-pin {
    rockchip,pins =
     <1 19 1 &pcfg_pull_none>;
   };

   pwm2_pin_pull_down: pwm2-pin-pull-down {
    rockchip,pins =
     <1 19 1 &pcfg_pull_down>;
   };
  };

  pwm3a {
   pwm3a_pin: pwm3a-pin {
    rockchip,pins =
     <0 6 1 &pcfg_pull_none>;
   };

   pwm3a_pin_pull_down: pwm3a-pin-pull-down {
    rockchip,pins =
     <0 6 1 &pcfg_pull_down>;
   };
  };

  pwm3b {
   pwm3b_pin: pwm3b-pin {
    rockchip,pins =
     <1 14 1 &pcfg_pull_none>;
   };

   pwm3b_pin_pull_down: pwm3b-pin-pull-down {
    rockchip,pins =
     <1 14 1 &pcfg_pull_down>;
   };
  };

  edp {
   edp_hpd: edp-hpd {
    rockchip,pins =
     <4 23 2 &pcfg_pull_none>;
   };
  };

  hdmi {
   hdmi_i2c_xfer: hdmi-i2c-xfer {
    rockchip,pins =
     <4 17 3 &pcfg_pull_none>,
     <4 16 3 &pcfg_pull_none>;
   };

   hdmi_cec: hdmi-cec {
    rockchip,pins =
     <4 23 1 &pcfg_pull_none>;
   };
  };

  pcie {
   pcie_clkreqn: pci-clkreqn {
    rockchip,pins =
     <2 26 2 &pcfg_pull_none>;
   };

   pcie_clkreqnb: pci-clkreqnb {
    rockchip,pins =
     <4 24 1 &pcfg_pull_none>;
   };

   pcie_clkreqn_cpm: pci-clkreqn-cpm {







    rockchip,pins =
     <2 26 0 &pcfg_pull_none>;
   };

   pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
    rockchip,pins =
     <4 24 0 &pcfg_pull_none>;
   };
  };
 };

 rockchip_suspend: rockchip-suspend {
  compatible = "rockchip,pm-rk3399";
  status = "disabled";
  rockchip,sleep-debug-en = <0>;
  rockchip,virtual-poweroff = <0>;
  rockchip,sleep-mode-config = <
   (0
   | (1 << 1)
   | (1 << 2)
   | (1 << 3)
   | (1 << 4)
   | (1 << 5)
   | (1 << 6)
   | (1 << 7)
   )
  >;
  rockchip,wakeup-config = <
   (0
   | (1 << 2)
   )
  >;
 };
};
# 47 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi" 1
# 43 "arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi"
# 1 "arch/arm64/boot/dts/rockchip/rk3399-sched-energy.dtsi" 1
# 43 "arch/arm64/boot/dts/rockchip/rk3399-sched-energy.dtsi"
/ {
 energy-costs {
  RK3399_CPU_COST_0: rk3399-core-cost0 {
   busy-cost-data = <
    108 46
    159 67
    216 90
    267 120
    318 153
    375 198
    401 222
   >;
   idle-cost-data = <
      6
      6
      0
      0
   >;
  };

  RK3399_CPU_COST_1: rk3399-core-cost1 {
   busy-cost-data = <
    210 129
    308 184
    419 246
    518 335
    617 428
    728 573
    827 724
    925 900
    1024 1108
   >;
   idle-cost-data = <
      15
      15
       0
       0
   >;
  };

  RK3399_CLUSTER_COST_0: rk3399-cluster-cost0 {
   busy-cost-data = <
    108 46
    159 67
    216 90
    267 120
    318 153
    375 198
    401 222
   >;
   idle-cost-data = <
    56
    56
    56
    56
   >;
  };

  RK3399_CLUSTER_COST_1: rk3399-cluster-cost1 {
   busy-cost-data = <
    210 129
    308 184
    419 246
    518 335
    617 428
    728 573
    827 724
    925 900
    1024 1108
   >;
   idle-cost-data = <
     65
     65
     65
     65
   >;
  };
 };
};
# 44 "arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi" 2

/ {
 cluster0_opp: opp-table0 {
  compatible = "operating-points-v2";
  opp-shared;

  nvmem-cells = <&cpul_leakage>;
  nvmem-cell-names = "cpu_leakage";

  rockchip,pvtm-voltage-sel = <
   0 143500 0
   143501 148500 1
   148501 152000 2
   152001 999999 3
  >;
  rockchip,pvtm-freq = <408000>;
  rockchip,pvtm-volt = <1000000>;
  rockchip,pvtm-ch = <0 0>;
  rockchip,pvtm-sample-time = <1000>;
  rockchip,pvtm-number = <10>;
  rockchip,pvtm-error = <1000>;
  rockchip,pvtm-ref-temp = <41>;
  rockchip,pvtm-temp-prop = <115 66>;
  rockchip,thermal-zone = "soc-thermal";

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <800000 800000 1200000>;
   opp-microvolt-L0 = <800000 800000 1200000>;
   opp-microvolt-L1 = <800000 800000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <800000 800000 1200000>;
   opp-microvolt-L0 = <800000 800000 1200000>;
   opp-microvolt-L1 = <800000 800000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <850000 850000 1200000>;
   opp-microvolt-L0 = <850000 850000 1200000>;
   opp-microvolt-L1 = <825000 825000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-1008000000 {
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <925000 925000 1200000>;
   opp-microvolt-L0 = <925000 925000 1200000>;
   opp-microvolt-L1 = <900000 900000 1200000>;
   opp-microvolt-L2 = <875000 875000 1200000>;
   opp-microvolt-L3 = <850000 850000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <1000000 1000000 1200000>;
   opp-microvolt-L0 = <1000000 1000000 1200000>;
   opp-microvolt-L1 = <975000 975000 1200000>;
   opp-microvolt-L2 = <950000 950000 1200000>;
   opp-microvolt-L3 = <925000 925000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <1125000 1125000 1200000>;
   opp-microvolt-L0 = <1125000 1125000 1200000>;
   opp-microvolt-L1 = <1100000 1100000 1200000>;
   opp-microvolt-L2 = <1075000 1075000 1200000>;
   opp-microvolt-L3 = <1050000 1050000 1200000>;
   clock-latency-ns = <40000>;
  };
 };

 cluster1_opp: opp-table1 {
  compatible = "operating-points-v2";
  opp-shared;

  nvmem-cells = <&cpub_leakage>;
  nvmem-cell-names = "cpu_leakage";

  rockchip,pvtm-voltage-sel = <
   0 149000 0
   149001 155000 1
   155001 160000 2
   160001 999999 3
  >;
  rockchip,pvtm-freq = <408000>;
  rockchip,pvtm-volt = <1000000>;
  rockchip,pvtm-ch = <1 0>;
  rockchip,pvtm-sample-time = <1000>;
  rockchip,pvtm-number = <10>;
  rockchip,pvtm-error = <1000>;
  rockchip,pvtm-ref-temp = <41>;
  rockchip,pvtm-temp-prop = <71 35>;
  rockchip,thermal-zone = "soc-thermal";

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <800000 800000 1200000>;
   opp-microvolt-L0 = <800000 800000 1200000>;
   opp-microvolt-L1 = <800000 800000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <800000 800000 1200000>;
   opp-microvolt-L0 = <800000 800000 1200000>;
   opp-microvolt-L1 = <800000 800000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <825000 825000 1200000>;
   opp-microvolt-L0 = <825000 825000 1200000>;
   opp-microvolt-L1 = <825000 825000 1200000>;
   opp-microvolt-L2 = <800000 800000 1200000>;
   opp-microvolt-L3 = <800000 800000 1200000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-1008000000 {
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <875000 875000 1200000>;
   opp-microvolt-L0 = <875000 875000 1200000>;
   opp-microvolt-L1 = <850000 850000 1200000>;
   opp-microvolt-L2 = <850000 850000 1200000>;
   opp-microvolt-L3 = <850000 850000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <950000 950000 1200000>;
   opp-microvolt-L0 = <950000 950000 1200000>;
   opp-microvolt-L1 = <925000 925000 1200000>;
   opp-microvolt-L2 = <900000 900000 1200000>;
   opp-microvolt-L3 = <875000 875000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <1025000 1025000 1200000>;
   opp-microvolt-L0 = <1025000 1025000 1200000>;
   opp-microvolt-L1 = <1000000 1000000 1200000>;
   opp-microvolt-L2 = <1000000 1000000 1200000>;
   opp-microvolt-L3 = <975000 975000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <1100000 1100000 1200000>;
   opp-microvolt-L0 = <1100000 1100000 1200000>;
   opp-microvolt-L1 = <1075000 1075000 1200000>;
   opp-microvolt-L2 = <1050000 1050000 1200000>;
   opp-microvolt-L3 = <1025000 1025000 1200000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <1200000 1200000 1200000>;
   opp-microvolt-L0 = <1200000 1200000 1200000>;
   opp-microvolt-L1 = <1175000 1175000 1200000>;
   opp-microvolt-L2 = <1150000 1150000 1200000>;
   opp-microvolt-L3 = <1125000 1125000 1200000>;
   clock-latency-ns = <40000>;
  };
 };

 gpu_opp_table: opp-table2 {
  compatible = "operating-points-v2";

  nvmem-cells = <&gpu_leakage>;
  nvmem-cell-names = "gpu_leakage";

  rockchip,pvtm-voltage-sel = <
   0 121000 0
   121001 125500 1
   125501 128500 2
   128501 999999 3
  >;
  rockchip,pvtm-freq = <200000>;
  rockchip,pvtm-volt = <900000>;
  rockchip,pvtm-ch = <3 0>;
  rockchip,pvtm-sample-time = <1000>;
  rockchip,pvtm-number = <10>;
  rockchip,pvtm-error = <1000>;
  rockchip,pvtm-ref-temp = <41>;
  rockchip,pvtm-temp-prop = <46 12>;
  rockchip,thermal-zone = "gpu-thermal";

  opp-200000000 {
   opp-hz = /bits/ 64 <200000000>;
   opp-microvolt = <800000>;
   opp-microvolt-L0 = <800000>;
   opp-microvolt-L1 = <800000>;
   opp-microvolt-L2 = <800000>;
   opp-microvolt-L3 = <800000>;
  };
  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <800000>;
   opp-microvolt-L0 = <800000>;
   opp-microvolt-L1 = <800000>;
   opp-microvolt-L2 = <800000>;
   opp-microvolt-L3 = <800000>;
  };
  opp-400000000 {
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <825000>;
   opp-microvolt-L0 = <825000>;
   opp-microvolt-L1 = <825000>;
   opp-microvolt-L2 = <800000>;
   opp-microvolt-L3 = <800000>;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <925000>;
   opp-microvolt-L0 = <925000>;
   opp-microvolt-L1 = <925000>;
   opp-microvolt-L2 = <900000>;
   opp-microvolt-L3 = <900000>;
  };
  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <1100000>;
   opp-microvolt-L0 = <1100000>;
   opp-microvolt-L1 = <1075000>;
   opp-microvolt-L2 = <1050000>;
   opp-microvolt-L3 = <1025000>;
  };
 };

 dmc_opp_table: opp-table3 {
  compatible = "operating-points-v2";

  opp-200000000 {
   opp-hz = /bits/ 64 <200000000>;
   opp-microvolt = <900000>;
  };
  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <900000>;
  };
  opp-400000000 {
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <900000>;
  };
  opp-528000000 {
   opp-hz = /bits/ 64 <528000000>;
   opp-microvolt = <900000>;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <900000>;
  };
  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <900000>;
  };
 };
};

&cpu_l0 {
 operating-points-v2 = <&cluster0_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
};

&cpu_l1 {
 operating-points-v2 = <&cluster0_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
};

&cpu_l2 {
 operating-points-v2 = <&cluster0_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
};

&cpu_l3 {
 operating-points-v2 = <&cluster0_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>;
};

&cpu_b0 {
 operating-points-v2 = <&cluster1_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>;
};

&cpu_b1 {
 operating-points-v2 = <&cluster1_opp>;
 sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>;
};

&gpu {
 operating-points-v2 = <&gpu_opp_table>;
};

&dmc {
 operating-points-v2 = <&dmc_opp_table>;
};
# 48 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi" 1
# 43 "arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/display/drm_mipi_dsi.h" 1
# 44 "arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi" 1
# 51 "arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi"
&sdhci {
  assigned-clocks = <&cru 78>;
  assigned-clock-parents = <&cru 5>;
  assigned-clock-rates = <200000000>;
};

&uart0 {
  assigned-clocks = <&cru 172>;
  assigned-clock-parents = <&cru 5>;
};

&uart1 {
  assigned-clocks = <&cru 173>;
  assigned-clock-parents = <&cru 5>;
};

&uart2 {
  assigned-clocks = <&cru 173>;
  assigned-clock-parents = <&cru 5>;
};

&uart3 {
  assigned-clocks = <&cru 173>;
  assigned-clock-parents = <&cru 5>;
};

&uart4 {
  assigned-clocks = <&pmucru 12>;
  assigned-clock-parents = <&pmucru 1>;
};

&spdif {
  assigned-clocks = <&cru 177>;
  assigned-clock-parents = <&cru 5>;
};

&i2s0{
  assigned-clocks = <&cru 174>;
  assigned-clock-parents = <&cru 5>;
};

&i2s1 {
  assigned-clocks = <&cru 175>;
  assigned-clock-parents = <&cru 5>;
};

&i2s2 {
  assigned-clocks = <&cru 176>;
  assigned-clock-parents = <&cru 5>;
};

&cru {
  assigned-clocks =
   <&cru 192>, <&cru 194>,
   <&cru 450>, <&cru 76>,
   <&cru 240>, <&cru 205>,
   <&cru 461>, <&cru 159>,
   <&cru 158>, <&cru 244>,
   <&cru 190>, <&cru 201>,
   <&cru 390>, <&cru 213>,
   <&cru 136>, <&cru 135>,
   <&cru 8>, <&cru 9>,
   <&cru 6>, <&cru 208>,
   <&cru 5>, <&cru 192>,
   <&cru 448>, <&cru 320>,
   <&cru 194>, <&cru 449>,
   <&cru 322>, <&cru 450>,
   <&cru 323>, <&cru 65>,
   <&cru 66>, <&cru 67>,
   <&cru 68>, <&cru 69>,
   <&cru 70>, <&cru 71>,
   <&cru 72>, <&cru 73>,
   <&cru 74>, <&cru 75>,
   <&cru 250>, <&cru 229>,
   <&cru 230>, <&cru 107>,
   <&cru 108>, <&cru 362>,
   <&cru 222>, <&cru 227>,
   <&cru 461>, <&cru 133>,
   <&cru 134>, <&cru 78>,
   <&cru 240>, <&cru 205>,
   <&cru 225>, <&cru 220>,
   <&cru 109>, <&cru 237>,
   <&cru 235>, <&cru 376>,
   <&cru 213>, <&cru 159>,
   <&cru 158>, <&cru 244>,
   <&cru 190>, <&cru 201>,
   <&cru 390>, <&cru 136>,
   <&cru 135>, <&cru 217>,
   <&cru 473>, <&cru 219>,
   <&cru 475>;
  assigned-clock-rates =
    <75000000>, <50000000>,
    <50000000>, <50000000>,
    <50000000>, <100000000>,
    <50000000>, <150000000>,
    <150000000>, <150000000>,
    <50000000>, <150000000>,
    <50000000>, <100000000>,
    <75000000>, <75000000>,
    <816000000>, <816000000>,
    <600000000>, <200000000>,
    <800000000>, <150000000>,
    <75000000>, <37500000>,
    <100000000>, <100000000>,
    <50000000>, <100000000>,
    <50000000>, <100000000>,
    <100000000>, <100000000>,
    <100000000>, <100000000>,
    <100000000>, <50000000>,
    <50000000>, <50000000>,
    <50000000>, <50000000>,
    <200000000>, <400000000>,
    <400000000>, <100000000>,
    <100000000>, <100000000>,
    <400000000>, <400000000>,
    <200000000>, <100000000>,
    <200000000>, <200000000>,
    <100000000>, <400000000>,
    <400000000>, <400000000>,
    <400000000>, <300000000>,
    <400000000>, <200000000>,
    <400000000>, <300000000>,
    <300000000>, <300000000>,
    <300000000>, <300000000>,
    <100000000>, <150000000>,
    <150000000>, <400000000>,
    <100000000>, <400000000>,
    <100000000>;
};
# 45 "arch/arm64/boot/dts/rockchip/rk3399-linux.dtsi" 2

/ {
 compatible = "rockchip,linux", "rockchip,rk3399";

 chosen {
  bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  drm_logo: drm-logo@00000000 {
   compatible = "rockchip,drm-logo";
   reg = <0x0 0x0 0x0 0x0>;
  };
 };

 cif_isp0: cif_isp@ff910000 {
  compatible = "rockchip,rk3399-cif-isp";
  rockchip,grf = <&grf>;
  reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
  reg-names = "register", "dsihost-register";
  clocks =
   <&cru 231>, <&cru 233>,
   <&cru 481>, <&cru 483>,
   <&cru 110>, <&cru 165>,
   <&cru 137>, <&cru 137>,
   <&cru 119>;
  clock-names =
   "aclk_isp0_noc", "aclk_isp0_wrapper",
   "hclk_isp0_noc", "hclk_isp0_wrapper",
   "clk_isp0", "pclk_dphyrx",
   "clk_cif_out", "clk_cif_pll",
   "pclk_dphy_ref";
  interrupts = <0 43 4 0>;
  interrupt-names = "cif_isp10_irq";
  power-domains = <&power 19>;
  rockchip,isp,iommu-enable = <1>;
  iommus = <&isp0_mmu>;
  status = "disabled";
 };

 cif_isp1: cif_isp@ff920000 {
  compatible = "rockchip,rk3399-cif-isp";
  rockchip,grf = <&grf>;
  reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
  reg-names = "register", "dsihost-register";
  clocks =
   <&cru 232>, <&cru 234>,
   <&cru 482>, <&cru 484>,
   <&cru 111>, <&cru 379>,
   <&cru 164>,
   <&cru 369>, <&cru 120>,
   <&cru 137>, <&cru 137>,
   <&cru 119>;
  clock-names =
   "aclk_isp1_noc", "aclk_isp1_wrapper",
   "hclk_isp1_noc", "hclk_isp1_wrapper",
   "clk_isp1", "pclkin_isp1",
   "pclk_dphytxrx",
   "pclk_mipi_dsi","mipi_dphy_cfg",
   "clk_cif_out", "clk_cif_pll",
   "pclk_dphy_ref";
  interrupts = <0 44 4 0>;
  interrupt-names = "cif_isp10_irq";
  power-domains = <&power 20>;
  rockchip,isp,iommu-enable = <1>;
  iommus = <&isp1_mmu>;
  status = "disabled";
 };
};

&display_subsystem {
 status = "okay";

 ports = <&vopb_out>, <&vopl_out>;
 logo-memory-region = <&drm_logo>;

 route {
  route_hdmi: route-hdmi {
   status = "okay";
   logo,uboot = "logo.bmp";
   logo,kernel = "logo_kernel.bmp";
   logo,mode = "center";
   charge_logo,mode = "center";
   connect = <&vopl_out_hdmi>;
  };

  route_dsi: route-dsi {
   status = "disabled";
   logo,uboot = "logo.bmp";
   logo,kernel = "logo_kernel.bmp";
   logo,mode = "center";
   charge_logo,mode = "center";
   connect = <&vopb_out_dsi>;
  };

  route_edp: route-edp {
   status = "disabled";
   logo,uboot = "logo.bmp";
   logo,kernel = "logo_kernel.bmp";
   logo,mode = "center";
   charge_logo,mode = "center";
   connect = <&vopb_out_edp>;
  };
 };
};

&pinctrl {
 isp {
  cif_clkout: cif-clkout {
   rockchip,pins =

    <2 11 3 &pcfg_pull_none>;
  };

  isp_dvp_d0d7: isp-dvp-d0d7 {
   rockchip,pins =
    <4 27 0 &pcfg_pull_none>,

    <2 11 3 &pcfg_pull_none>,

    <2 0 3 &pcfg_pull_none>,

    <2 1 3 &pcfg_pull_none>,

    <2 2 3 &pcfg_pull_none>,

    <2 3 3 &pcfg_pull_none>,

    <2 4 3 &pcfg_pull_none>,

    <2 5 3 &pcfg_pull_none>,

    <2 6 3 &pcfg_pull_none>,

    <2 7 3 &pcfg_pull_none>,

    <2 8 3 &pcfg_pull_none>,

    <2 9 3 &pcfg_pull_none>,

    <2 10 3 &pcfg_pull_none>;
  };

  isp_shutter: isp-shutter {
   rockchip,pins =

    <1 1 1 &pcfg_pull_none>,

    <1 0 1 &pcfg_pull_none>;
  };

  isp_flash_trigger: isp-flash-trigger {

   rockchip,pins = <1 3 1 &pcfg_pull_none>;
  };

  isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {

   rockchip,pins = <0 17 0 &pcfg_pull_none>;
  };
 };

 cam_pins {
  cam0_default_pins: cam0-default-pins {
   rockchip,pins =
    <4 27 0 &pcfg_pull_none>,
    <2 11 3 &pcfg_pull_none>;
  };
  cam0_sleep_pins: cam0-sleep-pins {
   rockchip,pins =
    <4 27 3 &pcfg_pull_none>,
    <2 11 0 &pcfg_pull_none>;
  };
 };
};
# 49 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 1
# 12 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h" 1
# 13 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 2
# 50 "arch/arm64/boot/dts/rockchip/rk3399-firefly-linux.dts" 2

/ {
 model = "Rockchip RK3399 Firefly Board (Linux Opensource)";
 compatible = "rockchip,rk3399-firefly-linux", "rockchip,rk3399";

 backlight: backlight {
  status = "disabled";
  compatible = "pwm-backlight";
  pwms = <&pwm0 0 25000 0>;
  brightness-levels = <
     0 1 2 3 4 5 6 7
     8 9 10 11 12 13 14 15
    16 17 18 19 20 21 22 23
    24 25 26 27 28 29 30 31
    32 33 34 35 36 37 38 39
    40 41 42 43 44 45 46 47
    48 49 50 51 52 53 54 55
    56 57 58 59 60 61 62 63
    64 65 66 67 68 69 70 71
    72 73 74 75 76 77 78 79
    80 81 82 83 84 85 86 87
    88 89 90 91 92 93 94 95
    96 97 98 99 100 101 102 103
   104 105 106 107 108 109 110 111
   112 113 114 115 116 117 118 119
   120 121 122 123 124 125 126 127
   128 129 130 131 132 133 134 135
   136 137 138 139 140 141 142 143
   144 145 146 147 148 149 150 151
   152 153 154 155 156 157 158 159
   160 161 162 163 164 165 166 167
   168 169 170 171 172 173 174 175
   176 177 178 179 180 181 182 183
   184 185 186 187 188 189 190 191
   192 193 194 195 196 197 198 199
   200 201 202 203 204 205 206 207
   208 209 210 211 212 213 214 215
   216 217 218 219 220 221 222 223
   224 225 226 227 228 229 230 231
   232 233 234 235 236 237 238 239
   240 241 242 243 244 245 246 247
   248 249 250 251 252 253 254 255>;
  default-brightness-level = <200>;
 };

 clkin_gmac: external-gmac-clock {
  compatible = "fixed-clock";
  clock-frequency = <125000000>;
  clock-output-names = "clkin_gmac";
  #clock-cells = <0>;
 };

 dw_hdmi_audio: dw-hdmi-audio {
  status = "disabled";
  compatible = "rockchip,dw-hdmi-audio";
  #sound-dai-cells = <0>;
 };

 edp_panel: edp-panel {
  status = "disabled";
  compatible = "sharp,lcd-f402", "panel-simple";
  backlight = <&backlight>;
  power-supply = <&vcc_lcd>;
  enable-gpios = <&gpio4 29 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&lcd_panel_reset>;

  ports {
   panel_in_edp: endpoint {
    remote-endpoint = <&edp_out_panel>;
   };
  };
 };

 fiq_debugger: fiq-debugger {
  compatible = "rockchip,fiq-debugger";
  rockchip,serial-id = <2>;
  rockchip,signal-irq = <182>;
  rockchip,wake-irq = <0>;
  rockchip,irq-mode-enable = <1>;
  rockchip,baudrate = <1500000>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2c_xfer>;
 };

 gpio-keys {
  compatible = "gpio-keys";
  #address-cells = <1>;
  #size-cells = <0>;
  autorepeat;

  pinctrl-names = "default";
  pinctrl-0 = <&pwrbtn>;

  button@0 {
   gpios = <&gpio0 5 1>;
   linux,code = <116>;
   label = "GPIO Key Power";
   linux,input-type = <1>;
   gpio-key,wakeup = <1>;
   debounce-interval = <100>;
  };
 };

 rt5640-sound {
  compatible = "simple-audio-card";
  simple-audio-card,format = "i2s";
  simple-audio-card,name = "rockchip,rt5640-codec";
  simple-audio-card,mclk-fs = <256>;
  simple-audio-card,widgets =
   "Microphone", "Mic Jack",
   "Headphone", "Headphone Jack";
  simple-audio-card,routing =
   "Mic Jack", "MICBIAS1",
   "IN1P", "Mic Jack",
   "Headphone Jack", "HPOL",
   "Headphone Jack", "HPOR";
  simple-audio-card,cpu {
   sound-dai = <&i2s1>;
  };
  simple-audio-card,codec {
   sound-dai = <&rt5640>;
  };
 };

 hdmi-dp-sound {
        status = "okay";
        compatible = "rockchip,rk3399-hdmi-dp";
        rockchip,cpu = <0xcb>;
        rockchip,codec = <0xcc 0xcd>;
    };

 hdmi_codec: hdmi-codec {
  compatible = "simple-audio-card";
  simple-audio-card,format = "i2s";
  simple-audio-card,mclk-fs = <256>;
  simple-audio-card,name = "HDMI-CODEC";

  simple-audio-card,cpu {
   sound-dai = <&i2s2>;
  };

  simple-audio-card,codec {
   sound-dai = <&hdmi>;
  };
 };

 spdif-sound {
  status = "okay";
  compatible = "simple-audio-card";
  simple-audio-card,name = "ROCKCHIP,SPDIF";
  simple-audio-card,cpu {
   sound-dai = <&spdif>;
  };
  simple-audio-card,codec {
   sound-dai = <&spdif_out>;
  };
 };

 spdif_out: spdif-out {
  status = "okay";
  compatible = "linux,spdif-dit";
  #sound-dai-cells = <0>;
 };

 sdio_pwrseq: sdio-pwrseq {
  compatible = "mmc-pwrseq-simple";
  clocks = <&rk808 1>;
  clock-names = "ext_clock";
  pinctrl-names = "default";
  pinctrl-0 = <&wifi_enable_h>;







  reset-gpios = <&gpio0 10 1>;
 };

 vcc3v3_pcie: vcc3v3-pcie-regulator {
  compatible = "regulator-fixed";
  enable-active-high;
  regulator-always-on;
  regulator-boot-on;
  gpio = <&gpio1 17 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&pcie_drv>;
  regulator-name = "vcc3v3_pcie";
 };

 vcc3v3_sys: vcc3v3-sys {
  compatible = "regulator-fixed";
  regulator-name = "vcc3v3_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
 };

 vcc5v0_host: vcc5v0-host-regulator {
  compatible = "regulator-fixed";
  enable-active-high;
  gpio = <&gpio1 0 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&host_vbus_drv>;
  regulator-name = "vcc5v0_host";
  regulator-always-on;
 };

 vcc5v0_sys: vcc5v0-sys {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
 };

 vcc_phy: vcc-phy-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc_phy";
  regulator-always-on;
  regulator-boot-on;
 };

 vdd_log: vdd-log {
  compatible = "pwm-regulator";
  pwms = <&pwm2 0 25000 1>;
  regulator-name = "vdd_log";
  regulator-min-microvolt = <800000>;
  regulator-max-microvolt = <1400000>;
  regulator-always-on;
  regulator-boot-on;


  rockchip,pwm_id= <2>;
  rockchip,pwm_voltage = <900000>;
 };

 vccadc_ref: vccadc-ref {
  compatible = "regulator-fixed";
  regulator-name = "vcc1v8_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <1800000>;
  regulator-max-microvolt = <1800000>;
 };

 vcc_lcd: vcc-lcd-regulator {
  compatible = "regulator-fixed";
  regulator-always-on;
  regulator-boot-on;
  enable-active-high;
  gpio = <&gpio1 1 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&lcd_en>;
  regulator-name = "vcc_lcd";
 };

 xin32k: xin32k {
  compatible = "fixed-clock";
  clock-frequency = <32768>;
  clock-output-names = "xin32k";
  #clock-cells = <0>;
 };

 wireless-wlan {
  compatible = "wlan-platdata";
  rockchip,grf = <&grf>;
  wifi_chip_type = "ap6354";
  sdio_vref = <1800>;
  WIFI,host_wake_irq = <&gpio0 3 0>;
  status = "okay";
 };

 wireless-bluetooth {
  compatible = "bluetooth-platdata";

  uart_rts_gpios = <&gpio2 19 1>;
  pinctrl-names = "default", "rts_gpio";
  pinctrl-0 = <&uart0_rts>;
  pinctrl-1 = <&uart0_gpios>;

  BT,reset_gpio = <&gpio0 9 0>;
  BT,wake_gpio = <&gpio2 26 0>;
  BT,wake_host_irq = <&gpio0 4 0>;
  status = "okay";
 };
};

&cpu_l0 {
 cpu-supply = <&vdd_cpu_l>;
};

&cpu_l1 {
 cpu-supply = <&vdd_cpu_l>;
};

&cpu_l2 {
 cpu-supply = <&vdd_cpu_l>;
};

&cpu_l3 {
 cpu-supply = <&vdd_cpu_l>;
};

&cpu_b0 {
 cpu-supply = <&vdd_cpu_b>;
};

&cpu_b1 {
 cpu-supply = <&vdd_cpu_b>;
};

&display_subsystem {
 status = "okay";
};

&edp {
 status = "disabled";

 ports {
  edp_out: port@1 {
   reg = <1>;
   #address-cells = <1>;
   #size-cells = <0>;

   edp_out_panel: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&panel_in_edp>;
   };
  };
 };
};

&emmc_phy {
 status = "okay";
};

&gmac {
 phy-supply = <&vcc_phy>;
 phy-mode = "rgmii";
 clock_in_out = "input";
 snps,reset-gpio = <&gpio3 15 1>;
 snps,reset-active-low;
 snps,reset-delays-us = <0 10000 50000>;
 assigned-clocks = <&cru 166>;
 assigned-clock-parents = <&clkin_gmac>;
 pinctrl-names = "default";
 pinctrl-0 = <&rgmii_pins>;
 tx_delay = <0x28>;
 rx_delay = <0x11>;
 status = "okay";
};

&gpu {
 status = "okay";
 mali-supply = <&vdd_gpu>;
};

&hdmi {
 #address-cells = <1>;
 #size-cells = <0>;
 #sound-dai-cells = <0>;
 status = "okay";
};

&i2c0 {
 status = "okay";
 i2c-scl-rising-time-ns = <168>;
 i2c-scl-falling-time-ns = <4>;
 clock-frequency = <400000>;

 vdd_cpu_b: syr827@40 {
  compatible = "silergy,syr827";
  reg = <0x40>;
  vin-supply = <&vcc5v0_sys>;
  regulator-compatible = "fan53555-reg";
  regulator-name = "vdd_cpu_b";
  regulator-min-microvolt = <712500>;
  regulator-max-microvolt = <1500000>;
  regulator-ramp-delay = <1000>;
  vsel-gpios = <&gpio1 18 0>;
  fcs,suspend-voltage-selector = <1>;
  regulator-always-on;
  regulator-boot-on;
  regulator-initial-state = <3>;
   regulator-state-mem {
   regulator-off-in-suspend;
  };
 };

 vdd_gpu: syr828@41 {
  compatible = "silergy,syr828";
  reg = <0x41>;
  vin-supply = <&vcc5v0_sys>;
  regulator-compatible = "fan53555-reg";
  regulator-name = "vdd_gpu";
  regulator-min-microvolt = <712500>;
  regulator-max-microvolt = <1500000>;
  regulator-ramp-delay = <1000>;
  fcs,suspend-voltage-selector = <1>;
  regulator-always-on;
  regulator-boot-on;
  regulator-initial-state = <3>;
   regulator-state-mem {
   regulator-off-in-suspend;
  };
 };

 rk808: pmic@1b {
  compatible = "rockchip,rk808";
  reg = <0x1b>;
  interrupt-parent = <&gpio1>;
  interrupts = <21 8>;
  pinctrl-names = "default";
  pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
  rockchip,system-power-controller;
  wakeup-source;
  #clock-cells = <1>;
  clock-output-names = "rk808-clkout1", "rk808-clkout2";

  vcc1-supply = <&vcc3v3_sys>;
  vcc2-supply = <&vcc3v3_sys>;
  vcc3-supply = <&vcc3v3_sys>;
  vcc4-supply = <&vcc3v3_sys>;
  vcc6-supply = <&vcc3v3_sys>;
  vcc7-supply = <&vcc3v3_sys>;
  vcc8-supply = <&vcc3v3_sys>;
  vcc9-supply = <&vcc3v3_sys>;
  vcc10-supply = <&vcc3v3_sys>;
  vcc11-supply = <&vcc3v3_sys>;
  vcc12-supply = <&vcc3v3_sys>;
  vddio-supply = <&vcc1v8_pmu>;

  regulators {
   vdd_center: DCDC_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;
    regulator-name = "vdd_center";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_cpu_l: DCDC_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;
    regulator-name = "vdd_cpu_l";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_ddr: DCDC_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vcc_ddr";
    regulator-state-mem {
     regulator-on-in-suspend;
    };
   };

   vcc_1v8: DCDC_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc_1v8";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcc1v8_dvp: LDO_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc1v8_dvp";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };


            vcc3v0_tp: LDO_REG2 {
                regulator-name = "vcca1v8_hdmi";
                regulator-min-microvolt = <0x1b7740>;
                regulator-max-microvolt = <0x1b7740>;
                regulator-always-on;
                regulator-boot-on;

                regulator-state-mem {
                    regulator-on-in-suspend;
                    regulator-suspend-microvolt = <0x1b7740>;
                };
            };

   vcc1v8_pmu: LDO_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc1v8_pmu";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcc_sd: LDO_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3000000>;
    regulator-name = "vcc_sd";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3000000>;
    };
   };

            vcca3v0_codec: LDO_REG5 {
                regulator-name = "vcc3v0_sd";
                regulator-min-microvolt = <0x2dc6c0>;
                regulator-max-microvolt = <0x2dc6c0>;
                regulator-always-on;
                regulator-boot-on;

                regulator-state-mem {
                    regulator-on-in-suspend;
                    regulator-suspend-microvolt = <0x2dc6c0>;
                };
            };

   vcc_1v5: LDO_REG6 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1500000>;
    regulator-max-microvolt = <1500000>;
    regulator-name = "vcc_1v5";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1500000>;
    };
   };

   vcca1v8_codec: LDO_REG7 {
                regulator-name = "vcca0v9_hdmi";
                regulator-min-microvolt = <0xdbba0>;
                regulator-max-microvolt = <0xdbba0>;
                regulator-always-on;
                regulator-boot-on;

                regulator-state-mem {
                    regulator-on-in-suspend;
                    regulator-suspend-microvolt = <0xdbba0>;
                };
            };

   vcc_3v0: LDO_REG8 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3000000>;
    regulator-name = "vcc_3v0";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3000000>;
    };
   };

   vcc3v3_s3: SWITCH_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vcc3v3_s3";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc3v3_s0: SWITCH_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vcc3v3_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };
  };
 };
};

&i2c1 {
 status = "okay";
 i2c-scl-rising-time-ns = <300>;
 i2c-scl-falling-time-ns = <15>;

 rt5640: rt5640@1c {
  #sound-dai-cells = <0>;
  compatible = "realtek,rt5640";
  reg = <0x1c>;
  clocks = <&cru 89>;
  clock-names = "mclk";
  realtek,in1-differential;
  pinctrl-names = "default";
  pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>;
  hp-con-gpio = <&gpio4 21 0>;

  io-channels = <&saradc 4>;
  hp-det-adc-value = <500>;
 };

 camera0: ov13850@10 {
  status = "okay";
  compatible = "omnivision,ov13850-v4l2-i2c-subdev";
  reg = < 0x10 >;
  device_type = "v4l2-i2c-subdev";

  clocks = <&cru 137>;
  clock-names = "clk_cif_out";

  pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
  pinctrl-0 = <&cam0_default_pins>;
  pinctrl-1 = <&cam0_sleep_pins>;

  rockchip,pd-gpio = <&gpio2 12 1>;
  rockchip,pwr-gpio = <&gpio1 23 0>;
  rockchip,pwr-2nd-gpio = <&gpio1 22 0>;
  rockchip,rst-gpio = <&gpio0 8 1>;

  rockchip,camera-module-mclk-name = "clk_cif_out";
  rockchip,camera-module-facing = "back";
  rockchip,camera-module-name = "cmk-cb0695-fv1";
  rockchip,camera-module-len-name = "lg9569a2";
  rockchip,camera-module-fov-h = "66.0";
  rockchip,camera-module-fov-v = "50.1";
  rockchip,camera-module-orientation = <0>;
  rockchip,camera-module-iq-flip = <0>;
  rockchip,camera-module-iq-mirror = <0>;
  rockchip,camera-module-flip = <1>;
  rockchip,camera-module-mirror = <0>;

  rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>;
  rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>;
  rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>;
  rockchip,camera-module-flash-support = <0>;
  rockchip,camera-module-mipi-dphy-index = <0>;
 };
};

&i2c3 {
 status = "okay";
 i2c-scl-rising-time-ns = <450>;
 i2c-scl-falling-time-ns = <15>;
};

&i2c4 {
 status = "okay";
 i2c-scl-rising-time-ns = <600>;
 i2c-scl-falling-time-ns = <20>;

 fusb0: fusb30x@22 {
  compatible = "fairchild,fusb302";
  reg = <0x22>;
  pinctrl-names = "default";
  pinctrl-0 = <&fusb0_int>;
  int-n-gpios = <&gpio1 2 0>;
  vbus-5v-gpios = <&gpio2 0 0>;
  status = "okay";
 };

 gsl3680: gsl3680@41 {
  status = "disabled";
  compatible = "gslX680-pad";
  reg = <0x41>;
  screen_max_x = <1536>;
  screen_max_y = <2048>;
  touch-gpio = <&gpio1 20 8>;
  reset-gpio = <&gpio0 12 0>;
 };

 mpu6050: mpu@68 {
  status = "disabled";
  compatible = "invensense,mpu6050";
  reg = <0x68>;
  mpu-int_config = <0x10>;
  mpu-level_shifter = <0>;
  mpu-orientation = <0 1 0 1 0 0 0 0 1>;
  orientation-x= <1>;
  orientation-y= <1>;
  orientation-z= <1>;
  irq-gpio = <&gpio1 4 8>;
  mpu-debug = <1>;
 };
};

&i2s0 {
 status = "okay";
 rockchip,i2s-broken-burst-len;
 rockchip,playback-channels = <8>;
 rockchip,capture-channels = <8>;
 #sound-dai-cells = <0>;
};

&i2s1 {
 status = "okay";
 rockchip,i2s-broken-burst-len;
 rockchip,playback-channels = <2>;
 rockchip,capture-channels = <2>;
 #sound-dai-cells = <0>;
};

&i2s2 {
 #sound-dai-cells = <0>;
 status = "okay";
};

&io_domains {
 status = "okay";

 bt656-supply = <&vcc1v8_dvp>;
 audio-supply = <&vcca1v8_codec>;
 sdmmc-supply = <&vcc_sd>;
 gpio1830-supply = <&vcc_3v0>;
};

&pcie_phy {
 status = "okay";
};

&pcie0 {
 ep-gpios = <&gpio4 25 0>;
 num-lanes = <4>;
 pinctrl-names = "default";
 pinctrl-0 = <&pcie_clkreqn_cpm>;
 status = "okay";
};

&pmu_io_domains {
 status = "okay";
 pmu1830-supply = <&vcc_3v0>;
};

&pinctrl {
 buttons {
  pwrbtn: pwrbtn {
   rockchip,pins = <0 5 0 &pcfg_pull_up>;
  };
 };

 lcd-panel {
  lcd_panel_reset: lcd-panel-reset {
   rockchip,pins = <4 29 0 &pcfg_pull_up>;
  };

  lcd_en: lcd-en {
   rockchip,pins = <1 1 0 &pcfg_pull_up>;
  };
 };

 pcie {
  pcie_drv: pcie-drv {
   rockchip,pins =
    <1 17 0 &pcfg_pull_none>;
   };
   pcie_3g_drv: pcie-3g-drv {
   rockchip,pins =
    <0 2 0 &pcfg_pull_up>;
  };
 };

 pmic {
  vsel1_gpio: vsel1-gpio {
   rockchip,pins =
    <1 18 0 &pcfg_pull_down>;
  };

  vsel2_gpio: vsel2-gpio {
   rockchip,pins =
   <1 14 0 &pcfg_pull_down>;
  };
 };

 sdio-pwrseq {
  wifi_enable_h: wifi-enable-h {
   rockchip,pins =
    <0 10 0 &pcfg_pull_none>;
  };
 };

 wireless-bluetooth {
  uart0_gpios: uart0-gpios {
   rockchip,pins =
    <2 19 0 &pcfg_pull_none>;
  };
 };

 rt5640 {
  rt5640_hpcon: rt5640-hpcon {
   rockchip,pins = <4 21 0 &pcfg_pull_none>;
  };
 };

 pmic {
  pmic_int_l: pmic-int-l {
   rockchip,pins =
    <1 21 0 &pcfg_pull_up>;
  };

  pmic_dvs2: pmic-dvs2 {
   rockchip,pins =
    <1 18 0 &pcfg_pull_down>;
  };
 };

 usb2 {
  host_vbus_drv: host-vbus-drv {
   rockchip,pins =
    <4 25 0 &pcfg_pull_none>;
  };
 };

 fusb30x {
  fusb0_int: fusb0-int {
   rockchip,pins = <1 2 0 &pcfg_pull_up>;
  };
 };
};

&pwm0 {
 status = "okay";
};

&pwm2 {
 status = "okay";
 pinctrl-names = "active";
 pinctrl-0 = <&pwm2_pin_pull_down>;
};

&rkvdec {
 status = "okay";
};

&rockchip_suspend {
 rockchip,power-ctrl =
  <&gpio1 18 1>,
  <&gpio1 14 0>;
};

&route_edp {
 status = "disabled";
};

&saradc {
 status = "okay";
 vref-supply = <&vccadc_ref>;
};

&sdhci {
 bus-width = <8>;
 keep-power-in-suspend;
 mmc-hs400-1_8v;
 mmc-hs400-enhanced-strobe;
 non-removable;
 status = "okay";
 supports-emmc;
};

&sdmmc {
 max-frequency = <150000000>;
 supports-sd;
 bus-width = <4>;
 cap-mmc-highspeed;
 cap-sd-highspeed;
 disable-wp;
 num-slots = <1>;
 vqmmc-supply = <&vcc_sd>;
 pinctrl-names = "default";
 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 status = "okay";
};

&sdio0 {
 max-frequency = <50000000>;
 supports-sdio;
 bus-width = <4>;
 disable-wp;
 cap-sd-highspeed;
 keep-power-in-suspend;
 mmc-pwrseq = <&sdio_pwrseq>;
 non-removable;
 num-slots = <1>;
 pinctrl-names = "default";
 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
 sd-uhs-sdr104;
 status = "okay";
};

&spdif {
 status = "okay";
 pinctrl-0 = <&spdif_bus_1>;
 i2c-scl-rising-time-ns = <450>;
 i2c-scl-falling-time-ns = <15>;
 #sound-dai-cells = <0>;
};

&tcphy0 {
 extcon = <&fusb0>;
 status = "okay";
};

&tcphy1 {
 status = "okay";
};

&tsadc {

 rockchip,hw-tshut-mode = <1>;

 rockchip,hw-tshut-polarity = <1>;
 status = "okay";
};

&u2phy0 {
 status = "okay";
 extcon = <&fusb0>;

 u2phy0_otg: otg-port {
  status = "okay";
 };

 u2phy0_host: host-port {
  phy-supply = <&vcc5v0_host>;
  status = "okay";
 };
};

&u2phy1 {
 status = "okay";

 u2phy1_otg: otg-port {
  status = "okay";
 };

 u2phy1_host: host-port {
  phy-supply = <&vcc5v0_host>;
  status = "okay";
 };
};

&uart0 {
 pinctrl-names = "default";
 pinctrl-0 = <&uart0_xfer &uart0_cts>;
 status = "okay";
};

&uart2 {
 status = "okay";
};

&usbdrd3_0 {
 status = "okay";
 extcon = <&fusb0>;
};

&usbdrd3_1 {
 status = "okay";
};

&usbdrd_dwc3_0 {
 status = "okay";
};

&usbdrd_dwc3_1 {
 status = "okay";
 dr_mode = "host";
};

&usb_host0_ehci {
 status = "okay";
};

&usb_host0_ohci {
 status = "okay";
};

&usb_host1_ehci {
 status = "okay";
};

&usb_host1_ohci {
 status = "okay";
};

&cif_isp0 {
 rockchip,camera-modules-attached = <&camera0>;
 status = "okay";
};

&isp0_mmu {
 status = "okay";
};

&vopb {
 status = "okay";
};

&vopb_mmu {
 status = "okay";
};

&vopl {
 status = "okay";
};

&vopl_mmu {
 status = "okay";
};

&vpu {
 status = "okay";
};