mod_clk

`timescale 1ns / 1ps

module clk_func #(
    parameter width = 64,
    parameter step = 32,
    parameter up_down = 1,
    parameter M = 28)
(
    input clk,
    output reg [width-1:0] out
);
    initial begin
        out <= 0;
    end
    always @(posedge clk) begin
        if (up_down) begin
            if (out >= M-1) begin
                out = 0;
            end else begin
                out = out + step;
            end
        end else begin
            if (out == 0) begin
                out = M-1;
            end
            else begin
                out = out - step;
            end
        end
    end
endmodule