module KA (
    input logic clk, clrn, up,
    output logic [2:0] q
);
always_ff @ (posedge clk or negedge clrn) begin
    if (!clrn) q <= 0;
    else
    begin
q[2] <= ((~q[2])&(~q[1])&(~q[0])&(~updown)) | ((~q[2])&q[1]&updown) | (q[2]&(~q[1])&updown) | (q[2]&q[1]&(~updown)) | (q[2]&(~q[1])&q[0]);
q[1] <= ((~q[1])&(~q[0])) | (q[1]&q[0]&(~updown)) |((~q[1])&q[0]&updown);
q[0] <= (q[0]&updown) | (q[2]&(~q[0])&(~updown)) | ((~q[2])&(~q[0])&(~updown));
end end
endmodule