AC_LAB1_EX1

module half_adder(
        output sum,
        output c_out,
        input a, b);

    xor x1(sum, a, b);
    and an1(c_out, a, b);
endmodule

module full_adder(
        output sum,
        output c_out,
    input a, b, c_in);

    wire o1, o2, o3;
    half_adder h1(sum, o1, c_in, o2);
    half_adder h2(o2, o3, a, b);
    or or1(o1, o3);
endmodule