Current:
     +-------------------+
     |       Rocket      |
     |
     | mmio_axi  mem_axi |
     +----+---------+----+
          |         |
        axi2wb    axi2wb
          |         |
        64wb32    64wb32   <---- WB masters
          |         |
       ("ibus")  ("dbus")  <---- these are misnomers in Rocket's context :)
          |         |
     ---+-+-----+---+----+- LiteX 32-bit WB bus
        |       |        |
       CSRs   LiteDRAM  bootrom   <---- WB slaves
     (incl.   (datapath)
      DRAM
      init.)


Future (currently working on it):

     +-------------------+
     |       Rocket      |
     |
     | mmio_axi  mem_axi |
     +----+---------+----+
          |         |
        axi2wb    LiteDRAM datapath
          |       (AXI 64-bit slave port)
        64wb32
          |
     ---+-+--------------+- LiteX 32-bit WB bus
        |                |
       CSRs             bootrom   <---- WB slaves
     (incl.
      DRAM
      init.)