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Oct 10th, 2019
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  1. Current:
  2. +-------------------+
  3. | Rocket |
  4. |
  5. | mmio_axi mem_axi |
  6. +----+---------+----+
  7. | |
  8. axi2wb axi2wb
  9. | |
  10. 64wb32 64wb32 <---- WB masters
  11. | |
  12. ("ibus") ("dbus") <---- these are misnomers in Rocket's context :)
  13. | |
  14. ---+-+-----+---+----+- LiteX 32-bit WB bus
  15. | | |
  16. CSRs LiteDRAM bootrom <---- WB slaves
  17. (incl. (datapath)
  18. DRAM
  19. init.)
  20.  
  21.  
  22. Future (currently working on it):
  23.  
  24. +-------------------+
  25. | Rocket |
  26. |
  27. | mmio_axi mem_axi |
  28. +----+---------+----+
  29. | |
  30. axi2wb LiteDRAM datapath
  31. | (AXI 64-bit slave port)
  32. 64wb32
  33. |
  34. ---+-+--------------+- LiteX 32-bit WB bus
  35. | |
  36. CSRs bootrom <---- WB slaves
  37. (incl.
  38. DRAM
  39. init.)
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