module Shifter_tb;
reg signed [15:0] stim, fails;
reg [3:0] shift;
reg [1:0] Op;
wire [15:0] sra, ror0, ror1, ror2, ror, expected, actual;

Shifter DUT(.Shift_Out(actual), .Shift_In(stim), .imm(shift), .Op(Op));

assign ror0 = shift[0] ? {stim[0], stim[15:1]} : stim;
assign ror1 = shift[1] ? {ror0[1:0], ror0[15:2]} : ror0;
assign ror2 = shift[2] ? {ror1[3:0], ror1[15:4]} : ror1;
assign ror = shift[3] ? {ror2[7:0], ror2[15:8]} : ror2;

assign sra = $signed(stim) >>> shift;

assign expected = (Op == 2'b00) ? $signed(stim) << (shift) : ((Op == 2'b01) ? sra : ror);

initial begin
	stim = 0;
	fails = 0;
	shift = 0;
	Op = 0;
	repeat(1000) begin
		stim = $random;
		shift[1] = $random;
		Op = $random;
		if (Op == 3) Op = 2;
		#20
		if (actual != expected) begin
			fails = fails + 1;
			$display("Input: %b, Expected: %b, Actual: %b, Shift: %b, Op: %b", stim, expected, actual, shift, Op);
		end
	end
	$display("Failures: %d", fails);
	#10;
end

endmodule