`timescale 1ns / 1ps
/**
    @brief A 32-bit adder pipelined to operate at 500 MHz
 */
module HighSpeedAdder(clk, a, b, s);

    input wire clk;
    input wire[31:0] a;
    input wire[31:0] b;
    output reg[31:0] s=0;

    reg[16:0] lowsum=0;
    reg[15:0] ahi;
    reg[15:0] bhi;

    always @(posedge clk) begin

        //Sum low-order bits and save high-order for next clock
        lowsum <= a[15:0] + b[15:0];
        ahi <= a[31:16];
        bhi <= b[31:16];

        //Sum high-order bits + carry out from previous pipe stage
        s[15:0] <= lowsum[15:0];
        s[31:16] <= ahi + bhi + lowsum[16];

    end

endmodule