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Astralix

rk3188.dtsi

Astralix
Jul 5th, 2013
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  1. /*
  2. * Copyright (c) 2013 Ulrich Prinz <ulrich.prinz@googlemail.com>
  3. * based on rk3066.dtsi
  4. * Copyright (c) 2013 MundoReader S.L.
  5. * Author: Heiko Stuebner <heiko@sntech.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17.  
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include <dt-bindings/interrupt-controller/irq.h>
  20. #include <dt-bindings/interrupt-controller/arm-gic.h>
  21. #include <dt-bindings/pinctrl/rockchip.h>
  22. #include "skeleton.dtsi"
  23. #include "rk3188-clocks.dtsi"
  24.  
  25. / {
  26. compatible = "rockchip,rk3188";
  27. interrupt-parent = <&gic>;
  28.  
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32.  
  33. cpu@0 {
  34. device_type = "cpu";
  35. compatible = "arm,cortex-a9";
  36. next-level-cache = <&L2>;
  37. reg = <0x0>;
  38. };
  39. cpu@1 {
  40. device_type = "cpu";
  41. compatible = "arm,cortex-a9";
  42. next-level-cache = <&L2>;
  43. reg = <0x1>;
  44. };
  45. cpu@2 {
  46. device_type = "cpu";
  47. compatible = "arm,cortex-a9";
  48. next-level-cache = <&L2>;
  49. reg = <0x2>;
  50. };
  51. cpu@3 {
  52. device_type = "cpu";
  53. compatible = "arm,cortex-a9";
  54. next-level-cache = <&L2>;
  55. reg = <0x3>;
  56. };
  57. };
  58.  
  59. soc {
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. compatible = "simple-bus";
  63. ranges;
  64.  
  65. scu@1013c000 {
  66. compatible = "arm,cortex-a9-scu";
  67. reg = <0x1013c000 0x100>;
  68. };
  69.  
  70. sram: sram@10080000 {
  71. compatible = "rockchip,rk3066-sram", "mmio-sram";
  72. reg = <0x10080000 0x10000>;
  73. mmio-sram-reserved = <0x0 0x50>;
  74. };
  75.  
  76. pmu@20004000 {
  77. compatible = "rockchip,rk3066-pmu";
  78. reg = <0x20004000 0x100>;
  79. };
  80.  
  81. gic: interrupt-controller@1013d000 {
  82. compatible = "arm,cortex-a9-gic";
  83. interrupt-controller;
  84. #interrupt-cells = <3>;
  85. reg = <0x1013d000 0x1000>,
  86. <0x1013c100 0x0100>;
  87. };
  88.  
  89. L2: l2-cache-controller@10138000 {
  90. compatible = "arm,pl310-cache";
  91. reg = <0x10138000 0x1000>;
  92. cache-unified;
  93. cache-level = <2>;
  94. };
  95.  
  96. /* RK30_PTIMER_PHYS */
  97. local-timer@1013c600 {
  98. compatible = "arm,cortex-a9-twd-timer";
  99. /* compatible = "arm,armv7-timer"; */
  100. reg = <0x1013c600 0x20>;
  101. interrupts = <GIC_PPI 13 0x304>;
  102. clocks = <&clk_gates0 0>;
  103. };
  104.  
  105. /* RK30_TIMER6 - IRQ 96 */
  106. timer6@200380A0 {
  107. compatible = "rockchip,rk3188-dw-apb-timer-osc";
  108. reg = <0x200380A0 0x20>;
  109. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  110. clocks = <&clk_gates3 14>, <&clk_gates7 7>;
  111. clock-names = "timer", "pclk";
  112. };
  113.  
  114. /* RK30_TIMER0 - IRQ 76 */
  115. timer0@20038000 {
  116. compatible = "rockchip,rk3188-dw-apb-timer-osc";
  117. reg = <0x20038000 0x20>;
  118. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  119. clocks = <&clk_gates1 0>, <&clk_gates7 7>;
  120. clock-names = "timer", "pclk";
  121. };
  122.  
  123. /* RK30_TIMER1 - IRQ 77 */
  124. timer1@20038020 {
  125. compatible = "rockchip,rk3188-dw-apb-timer-osc";
  126. reg = <0x20038020 0x20>;
  127. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  128. clocks = <&clk_gates1 1>, <&clk_gates7 7>;
  129. clock-names = "timer", "pclk";
  130. };
  131.  
  132. /* RK30_TIMER2 - IRQ 91 */
  133. timer3@20038060 {
  134. compatible = "rockchip,rk3188-dw-apb-timer-osc";
  135. reg = <0x20038060 0x20>;
  136. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  137. clocks = <&clk_gates1 1>, <&clk_gates7 7>;
  138. clock-names = "timer", "pclk";
  139. };
  140.  
  141. /* RK30_TIMER4 - IRQ 92 */
  142. timer4@20038080 {
  143. compatible = "rockchip,rk3188-dw-apb-timer-osc";
  144. reg = <0x20038080 0x20>;
  145. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  146. clocks = <&clk_gates1 1>, <&clk_gates7 7>;
  147. clock-names = "timer", "pclk";
  148. };
  149.  
  150. watchdog@2004c000 {
  151. compatible = "snps,dw-apb-wdt";
  152. reg = <0x2004c000 0x100>;
  153. clocks = <&clk_gates7 15>;
  154. };
  155.  
  156. pinctrl@20008000 {
  157. compatible = "rockchip,rk3188-pinctrl";
  158. reg = <0x20008000 0x150>;
  159. #address-cells = <1>;
  160. #size-cells = <1>;
  161. ranges;
  162.  
  163. gpio0: gpio0@0x2000a000 {
  164. compatible = "rockchip,gpio-bank";
  165. reg = <0x2000a000 0x100>;
  166. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  167. clocks = <&clk_gates8 9>;
  168.  
  169. gpio-controller;
  170. #gpio-cells = <2>;
  171.  
  172. interrupt-controller;
  173. #interrupt-cells = <2>;
  174. };
  175.  
  176. gpio1: gpio1@0x2003c000 {
  177. compatible = "rockchip,gpio-bank";
  178. reg = <0x2003c000 0x100>;
  179. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  180. clocks = <&clk_gates8 10>;
  181.  
  182. gpio-controller;
  183. #gpio-cells = <2>;
  184.  
  185. interrupt-controller;
  186. #interrupt-cells = <2>;
  187. };
  188.  
  189. gpio2: gpio2@2003e000 {
  190. compatible = "rockchip,gpio-bank";
  191. reg = <0x2003e000 0x100>;
  192. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  193. clocks = <&clk_gates8 11>;
  194.  
  195. gpio-controller;
  196. #gpio-cells = <2>;
  197.  
  198. interrupt-controller;
  199. #interrupt-cells = <2>;
  200. };
  201.  
  202. gpio3: gpio3@20080000 {
  203. compatible = "rockchip,gpio-bank";
  204. reg = <0x20080000 0x100>;
  205. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  206. clocks = <&clk_gates8 12>;
  207.  
  208. gpio-controller;
  209. #gpio-cells = <2>;
  210.  
  211. interrupt-controller;
  212. #interrupt-cells = <2>;
  213. };
  214.  
  215. pcfg_pull_default: pcfg_pull_default {
  216. bias-pull-pin-up;
  217. };
  218.  
  219. pcfg_pull_none: pcfg_pull_none {
  220. bias-disable;
  221. };
  222.  
  223. pcfg_pull_up: pcfg_pull_up {
  224. bias-pull-up;
  225. };
  226.  
  227. pcfg_pull_down: pcfg_pull_down {
  228. bias-pull-down;
  229. };
  230.  
  231. uart0 {
  232. uart0_xfer: uart0-xfer {
  233. rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
  234. <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
  235. rockchip,config = <&pcfg_pull_default>;
  236. };
  237.  
  238. uart0_cts: uart0-cts {
  239. rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
  240. rockchip,config = <&pcfg_pull_default>;
  241. };
  242.  
  243. uart0_rts: uart0-rts {
  244. rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
  245. rockchip,config = <&pcfg_pull_default>;
  246. };
  247. };
  248.  
  249. uart1 {
  250. uart1_xfer: uart1-xfer {
  251. rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
  252. <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
  253. rockchip,config = <&pcfg_pull_default>;
  254. };
  255.  
  256. uart1_cts: uart1-cts {
  257. rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
  258. rockchip,config = <&pcfg_pull_default>;
  259. };
  260.  
  261. uart1_rts: uart1-rts {
  262. rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
  263. rockchip,config = <&pcfg_pull_default>;
  264. };
  265. };
  266.  
  267. uart2 {
  268. uart2_xfer: uart2-xfer {
  269. rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
  270. <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
  271. /*rockchip,config = <&pcfg_pull_default>; */
  272. };
  273. /* no rts / cts for uart2 */
  274. };
  275.  
  276. uart3 {
  277. uart3_xfer: uart3-xfer {
  278. rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
  279. <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
  280. rockchip,config = <&pcfg_pull_default>;
  281. };
  282.  
  283. uart3_cts: uart3-cts {
  284. rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
  285. rockchip,config = <&pcfg_pull_default>;
  286. };
  287.  
  288. uart3_rts: uart3-rts {
  289. rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
  290. rockchip,config = <&pcfg_pull_default>;
  291. };
  292. };
  293.  
  294. sd0 {
  295. sd0_clk: sd0-clk {
  296. rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
  297. rockchip,config = <&pcfg_pull_default>;
  298. };
  299.  
  300. sd0_cmd: sd0-cmd {
  301. rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
  302. rockchip,config = <&pcfg_pull_default>;
  303. };
  304.  
  305. sd0_cd: sd0-cd {
  306. rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
  307. rockchip,config = <&pcfg_pull_default>;
  308. };
  309.  
  310. sd0_wp: sd0-wp {
  311. rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
  312. rockchip,config = <&pcfg_pull_default>;
  313. };
  314.  
  315. sd0_bus1: sd0-bus-width1 {
  316. rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
  317. rockchip,config = <&pcfg_pull_default>;
  318. };
  319.  
  320. sd0_bus4: sd0-bus-width4 {
  321. rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
  322. <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
  323. <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
  324. <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
  325. rockchip,config = <&pcfg_pull_default>;
  326. };
  327. };
  328.  
  329. sd1 {
  330. sd1_clk: sd1-clk {
  331. rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
  332. rockchip,config = <&pcfg_pull_default>;
  333. };
  334.  
  335. sd1_cmd: sd1-cmd {
  336. rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
  337. rockchip,config = <&pcfg_pull_default>;
  338. };
  339.  
  340. sd1_cd: sd1-cd {
  341. rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
  342. rockchip,config = <&pcfg_pull_default>;
  343. };
  344.  
  345. sd1_wp: sd1-wp {
  346. rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
  347. rockchip,config = <&pcfg_pull_default>;
  348. };
  349.  
  350. sd1_bus1: sd1-bus-width1 {
  351. rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
  352. rockchip,config = <&pcfg_pull_default>;
  353. };
  354.  
  355. sd1_bus4: sd1-bus-width4 {
  356. rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
  357. <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
  358. <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
  359. <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
  360. rockchip,config = <&pcfg_pull_default>;
  361. };
  362. };
  363. };
  364.  
  365. uart0: serial@10124000 {
  366. compatible = "snps,dw-apb-uart";
  367. reg = <0x10124000 0x400>;
  368. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  369. reg-shift = <2>;
  370. reg-io-width = <1>;
  371. clocks = <&clk_gates1 8> /*<&mux_uart0> */;
  372. };
  373.  
  374. uart1: serial@10126000 {
  375. compatible = "snps,dw-apb-uart";
  376. reg = <0x10126000 0x400>;
  377. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  378. reg-shift = <2>;
  379. reg-io-width = <1>;
  380. clocks = <&clk_gates1 10> /* <&mux_uart1> */;
  381. status = "disabled";
  382. };
  383.  
  384. uart2: serial@20064000 {
  385. compatible = "snps,dw-apb-uart";
  386. reg = <0x20064000 0x400>;
  387. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  388. reg-shift = <2>;
  389. reg-io-width = <1>;
  390. clocks = <&clk_gates1 12> /* <&mux_uart2> */;
  391. status = "disabled";
  392. };
  393.  
  394. uart3: serial@20068000 {
  395. compatible = "snps,dw-apb-uart";
  396. reg = <0x20068000 0x400>;
  397. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  398. reg-shift = <2>;
  399. reg-io-width = <1>;
  400. clocks = <&clk_gates1 14> /* <&mux_uart3> */;
  401. status = "disabled";
  402. };
  403.  
  404. dwmmc@10214000 {
  405. compatible = "rockchip,rk2928-dw-mshc";
  406. reg = <0x10214000 0x1000>;
  407. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  408. #address-cells = <1>;
  409. #size-cells = <0>;
  410.  
  411. clocks = <&clk_gates5 10>, <&clk_gates2 11>;
  412. clock-names = "biu", "ciu";
  413.  
  414. status = "disabled";
  415. };
  416.  
  417. dwmmc@10218000 {
  418. compatible = "rockchip,rk2928-dw-mshc";
  419. reg = <0x10218000 0x1000>;
  420. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  421. #address-cells = <1>;
  422. #size-cells = <0>;
  423.  
  424. clocks = <&clk_gates5 11>, <&clk_gates2 13>;
  425. clock-names = "biu", "ciu";
  426.  
  427. status = "disabled";
  428. };
  429. };
  430. };
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