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Mar 13th, 2021
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  1. `timescale 1ns / 1ps
  2.  
  3. `define IDX64(x) ((x) << 6)+:64
  4.  
  5. // Testbench for the Skein block process implementation
  6. module Skein1024Block_tb;
  7.  
  8. localparam STARTING_WORK = 2'b00, MIDDLE_SECTION = 2'b01, WAITING_ON_RESULTS = 2'b10;
  9. genvar x;
  10.  
  11. // Reg
  12. reg clk = 1'b0, DataValid = 1'b0;
  13.  
  14. // Inputs
  15. reg [1023:0] TestInput;
  16. reg [1087:0] TestKey;
  17. reg [191:0] TestType;
  18.  
  19. always #1 clk = ~clk;
  20. wire [1023:0] Output;
  21. wire CompletedSig;
  22.  
  23. initial
  24. begin
  25.  
  26. $dumpfile("SimOutput.lxt2");
  27. $dumpvars(0, Skein1024Block_tb);
  28.  
  29. #2;
  30.  
  31. // Initialize input
  32. TestInput <= 1024'hA6D8A0A61291CD34F4546149C74CC22E2649339EB37B6519AED442CA29B94FB21BFFD5B90DE16C135743D3A68ED874A160F27B8D098A828BF98FACDB647C0355371E5F0A3B9E81B7F7F78C1BAD4B1DF441B07D5909BE1F3FA16C4845892B8E46A34B94CDB69DFAF73D6E858FC504E56DFD6B3533D9D8B3B11BCECBB3A446FA31;
  33. TestKey <= 1088'h11409CDB9691AEBB5663952F715D1DDD53D6E4F52E19A6D1FC46DE35C4E2A0860D339D5DAADEE3DC9828030DA0A6388CCC1A9CAFA494DBD30914A20D3DFEA9E49D2599730EF7AB6BB2F6675FA17F0FD23304ACFCA83009983FDBFB11D4A46A3E583A8BFCCE34EB6C6C23C39667038BCAFFCBFE9CA1A2CE265F6E8B1A72F001CA5A4352BE62092156;
  34. TestType <= 192'h700000000000008070000000000000000000000000000080;
  35.  
  36. #2
  37.  
  38. // Hold the valid data signal high for one clock cycle
  39. DataValid <= 1'b1;
  40.  
  41. #2;
  42.  
  43. DataValid <= 1'b0;
  44.  
  45. #2
  46.  
  47. while(~CompletedSig) #2;
  48.  
  49. if(Output == 1024'h9078411822E49AAE5512449E8F4ED59107B079C9DF2BCE3971614DDE843E901CBE4AD1BA2E0A2BA8FA2961C972F775C5C6B995F0D482AC8854FC2D17112F99D406C04D28B82118E3852A1A7B236C6C36A6492DF609BD61FC0D6FD0C2F85CB45CD52EBE0DD72D398BFF9AEE231C289271817284E6DBCA4063D96FCEBB0D5AF404)
  50. $display("PASS.");
  51. else
  52. $display("FAIL. 0x%h", Output);
  53.  
  54. $finish;
  55. end
  56.  
  57. Skein1024Block BlockProcessTest(Output, CompletedSig, clk, DataValid, TestInput, TestKey, TestType);
  58. endmodule
  59.  
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