LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.ITCE211Project_library.ALL;

ENTITY MEengine IS

    PORT (
        eni, reset, clk : IN STD_LOGIC;
        numberinin : INOUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
        mv : OUT STD_LOGIC_VECTOR (data_output - 1 DOWNTO 0)

    );
END MEengine;

ARCHITECTURE Behavioral OF MEengine IS
    COMPONENT pe IS
        PORT (
            numberin : INOUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            numberout, number : INOUT STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
            clk, eni, reset : IN STD_LOGIC;
            eno : OUT STD_LOGIC
        );

    END COMPONENT;
    ----------------------Signals-------------------------------------
    SIGNAL numberout, number : vector_array(number_of_pe - 1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));

    SIGNAL enablesig : my_array := (OTHERS => '0');
BEGIN
    ----------------------Generate component-------------------------------------
    Gen_PE : FOR i IN 0 TO number_of_PE - 1 GENERATE
        Gen_PE0 : IF i = 0 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => numberinin,
                numberout => numberout(1),
                number => number(i),
                eno => enablesig(1),
                clk => clk,
                reset => reset,
                eni => eni);

        END GENERATE Gen_PE0;
        Gen_PE1 : IF i > 0 AND i < number_of_PE - 1 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => numberout(i),
                eni => enablesig(i),
                numberout => numberout(i + 1),
                eno => enablesig(i + 1),
                number => number(i),
                clk => clk,
                reset => reset);
        END GENERATE Gen_PE1;
        Gen_PE2 : IF i = number_of_PE - 1 GENERATE
            Processing_Element : pe PORT MAP(
                numberin => numberout(i),
                eni => enablesig(i),
                numberout => OPEN,
                number => number(i),
                eno => OPEN,
                clk => clk,
                reset => reset
            );
        END GENERATE Gen_PE2;

    END GENERATE Gen_PE;
    PROCESS (clk) IS

    BEGIN GENERATE

            FOR i IN 0 TO number_of_PE - 1 LOOP
                mv <= numberout(i) & numberout(i + 1);
            END LOOP;
        END PROCESS;

    END behavioral;