library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blink is
    Port ( clk : in STD_LOGIC;
	        reset : in STD_LOGIC;
	        o : out  STD_LOGIC);
end blink;

architecture Behavioral of blink is

	signal aux : std_logic;
	signal trigger_aux : std_logic;
	signal q_aux : std_logic_vector(3 downto 0);

	component counter
	   generic(size: integer := 4;
		        trigger_value: integer);
		port(clk, reset, enable : in std_logic;
		     q : out std_logic_vector(size-1 downto 0);
			  trigger: out std_logic );
	end component;

begin

	count : counter
	   generic map(size => 26, trigger_value => 50000000)
		port map(clk => clk, enable => '1', reset => reset, trigger => trigger_aux);

	toggle: process(clk, reset)
	begin
	   if reset = '0' then
		   aux <= '0';
		elsif clk'event and clk = '1' then
		   if trigger_aux = '1' then
			   aux <= not aux;
			else
			   aux <= aux;
			end if;
		end if;
	end process;
	o <= aux;

end Behavioral;