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L1 kernel boot hvc calls V2 + dummy hyp call

jintack
Feb 14th, 2016
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  1. init: plymouth-upstart-bridge main process ended, respawning
  2. PC: 00000000400826d0, LR: 0000000040081008 -------Switch to Lowvisor--------
  3. MRS REG EL2 SP: SCTLR_EL2 IMM/REG: 0, VAL: 8
  4. PC: 00000000400826d8, LR: 0000000040081008 MSR REG EL2 SP: SCTLR_EL2 IMM/REG: 0, VAL: 0
  5. PC: 00000000400826fc, LR: 0000000040081008 MSR REG EL2 SP: HCR_EL2 IMM/REG: 0, VAL: 80000000
  6. PC: 0000000040082700, LR: 0000000040081008 MRS REG EL2 SP: CNTHCTL_EL2 IMM/REG: 0, VAL: 80000000
  7. PC: 0000000040082708, LR: 0000000040081008 MSR REG EL2 SP: CNTHCTL_EL2 IMM/REG: 0, VAL: 3
  8. PC: 000000004008270c, LR: 0000000040081008 MSR REG EL2 SP: CNTVOFF_EL2 IMM/REG: 31, VAL: 0
  9. PC: 0000000040082744, LR: 0000000040081008 MRS REG EL1 SP: 1 IMM/REG: 1, VAL: 40882080
  10. PC: 0000000040082748, LR: 0000000040081008 MSR REG EL2 SP: VPIDR_EL2 IMM/REG: 0, VAL: 500f0001
  11. PC: 000000004008274c, LR: 0000000040081008 MSR REG EL2 SP: VMPIDR_EL2 IMM/REG: 1, VAL: 80000000
  12. PC: 0000000040082758, LR: 0000000040081008 MSR REG EL1 SP: 3 IMM/REG: 0, VAL: 30d00800
  13. PC: 0000000040082760, LR: 0000000040081008 MSR REG EL2 SP: CPTR_EL2 IMM/REG: 0, VAL: 33ff
  14. PC: 0000000040082764, LR: 0000000040081008 MSR REG EL2 SP: HSTR_EL2 IMM/REG: 31, VAL: 0
  15. PC: 0000000040082768, LR: 0000000040081008 DEBUG: imm: 7000, x0: 33ff
  16. kvm_handle_sys_reg MRS
  17. PC: 0000000040082770, LR: 0000000040081008 DEBUG: imm: 7001, x0: 0
  18. PC: 0000000040082778, LR: 0000000040081008 DEBUG: imm: 7002, x0: 0
  19. PC: 000000004008277c, LR: 0000000040081008 MSR REG EL2 SP: MDCR_EL2 IMM/REG: 0, VAL: 0
  20. PC: 0000000040082780, LR: 0000000040081008 MSR REG EL2 SP: VTTBR_EL2 IMM/REG: 31, VAL: 0
  21. PC: 000000004008278c, LR: 0000000040081008 MSR REG EL2 SP: VBAR_EL2 IMM/REG: 0, VAL: 4008a800
  22. PC: 0000000040082794, LR: 0000000040081008 MSR REG EL2 SP: SPSR_EL2 IMM/REG: 0, VAL: 3c5
  23. PC: 0000000040082798, LR: 0000000040081008 MSR REG EL2 SP: ELR_EL2 IMM/REG: 30, VAL: 40081008
  24. PC: 00000000400827a0, LR: 0000000040081008 -------Switch to Kernel--------
  25. ERET: target pc: 40081008 lr: 40081008
  26. kvm_handle_sys_reg MSR
  27. kvm_handle_sys_reg MSR
  28. kvm_handle_sys_reg MSR
  29. kvm_handle_sys_reg MSR
  30. kvm_handle_sys_reg MSR
  31. kvm_handle_sys_reg MSR
  32. PC: 0000000040616040, LR: 0000000040616000 DEBUG: imm: 7081, x0: ffff800000081190
  33. PC: ffff8000008255e4, LR: 0000000040616000 DEBUG: imm: 7082, x0: ffff800000081190
  34. L0 HVC
  35. L0 HVC
  36. kvm_handle_sys_reg MSR
  37. kvm_handle_sys_reg MSR
  38. PC: ffff8000000a07e4, LR: ffff800000099c80 DEBUG: imm: 7080, x0: 0
  39. PC: ffff8000000a084c, LR: ffff8000000a0848 DEBUG: imm: 7081, x0: ffff8003700d8000
  40. PC: ffff8000000a085c, LR: ffff8000000a0850 DEBUG: imm: 7070, x0: 0
  41. PC: ffff80000008b064, LR: ffff8000000a0880 -------Switch to Lowvisor--------
  42. INJECT to L1: target pc: ffff80000008ac00
  43. PC: ffff80000008b004, LR: ffff8000000a0880 MRS REG EL2 SP: ESR_EL2 IMM/REG: 1, VAL: 0
  44. PC: ffff80000008b020, LR: ffff8000000a0880 MRS REG EL2 SP: VBAR_EL2 IMM/REG: 0, VAL: 0
  45. PC: ffff80000008b024, LR: ffff8000000a0880 DEBUG: imm: 7091, x0: 4008a800
  46. PC: ffff80000008b028, LR: ffff8000000a0880 -------Switch to Kernel--------
  47. ERET: target pc: ffff80000008b064 lr: ffff8000000a0880
  48. PC: ffff80000008b068, LR: ffff8000000a0880 DEBUG: imm: 7001, x0: 4008a800
  49. PC: ffff8000000a0a40, LR: ffff8000000a0a3c DEBUG: imm: 7010, x0: 21
  50. PC: ffff80000009f720, LR: ffff80000009f71c DEBUG: imm: 7020, x0: 18
  51. PC: ffff8000000a3544, LR: ffff80000009f724 DEBUG: imm: 7030, x0: 40612000
  52. PC: ffff80000008b064, LR: ffff80000009f728 -------Switch to Lowvisor--------
  53. INJECT to L1: target pc: ffff80000008ac00
  54. PC: ffff80000008b004, LR: ffff80000009f728 MRS REG EL2 SP: ESR_EL2 IMM/REG: 1, VAL: 40612000
  55. PC: ffff80000008b018, LR: ffff80000009f728 MSR REG EL2 SP: VBAR_EL2 IMM/REG: 0, VAL: 40612000
  56. PC: ffff80000008b024, LR: ffff80000009f728 DEBUG: imm: 7091, x0: 40612000
  57. PC: ffff80000008b028, LR: ffff80000009f728 -------Switch to Kernel--------
  58. ERET: target pc: ffff80000008b064 lr: ffff80000009f728
  59. PC: ffff80000008b068, LR: ffff80000009f728 DEBUG: imm: 7001, x0: 40612000
  60. PC: ffff80000009f72c, LR: ffff80000009f728 DEBUG: imm: 7021, x0: 40612000
  61. PC: ffff8000000a48b4, LR: ffff80000009f760 -------Switch to Lowvisor--------
  62. INJECT to L1: target pc: ffff800000612400
  63. PC: ffff80000061278c, LR: ffff80000009f760 DEBUG: imm: 7111, x0: 3af87c000
  64. PC: ffff800000612790, LR: ffff80000009f760 MSR REG EL2 SP: TTBR0_EL2 IMM/REG: 0, VAL: 3af87c000
  65. Switch TTBR
  66. PC: ffff800000612794, LR: ffff80000009f760 MRS REG EL1 SP: 8 IMM/REG: 4, VAL: 0
  67. PC: ffff8000006127a8, LR: ffff80000009f760 MSR REG EL2 SP: TCR_EL2 IMM/REG: 4, VAL: 80823510
  68. PC: ffff8000006127c8, LR: ffff80000009f760 MSR REG EL2 SP: VTCR_EL2 IMM/REG: 4, VAL: 80033558
  69. PC: ffff8000006127cc, LR: ffff80000009f760 MRS REG EL1 SP: 13 IMM/REG: 4, VAL: 80033558
  70. PC: ffff8000006127d0, LR: ffff80000009f760 MSR REG EL2 SP: MAIR_EL2 IMM/REG: 4, VAL: bbff440c0400
  71. PC: ffff8000006127d8, LR: ffff80000009f760 TLBI
  72. PC: ffff8000006127e0, LR: ffff80000009f760 MRS REG EL2 SP: SCTLR_EL2 IMM/REG: 4, VAL: bbff440c0400
  73. PC: ffff8000006127f0, LR: ffff80000009f760 MSR REG EL2 SP: SCTLR_EL2 IMM/REG: 4, VAL: 100f
  74. PC: ffff8000006127f8, LR: ffff80000009f760 DEBUG: imm: 7001, x0: 3af87c000
  75. PC: ffff800000612800, LR: ffff80000009f760 DEBUG: imm: 7002, x0: 3af87c000
  76. PC: ffff800000612808, LR: ffff80000009f760 DEBUG: imm: 7003, x0: 3af87c000
  77. PC: ffff800000612814, LR: ffff80000009f760 DEBUG: imm: 7004, x0: fffffffff000
  78. PC: ffff80000061281c, LR: ffff80000009f760 DEBUG: imm: 7005, x0: fffffffff000
  79. PC: ffff800000612828, LR: ffff80000009f760 DEBUG: imm: 7006, x0: fffffffff830
  80. PC: 0000fffffffff834, LR: ffff80000009f760 DEBUG: imm: 7008, x0: fffffffff830
  81. PC: 0000fffffffff838, LR: ffff80000009f760 MSR REG EL2 SP: TTBR0_EL2 IMM/REG: 1, VAL: 3af879000
  82. Switch TTBR
  83. PC: 0000fffffffff840, LR: ffff80000009f760 TLBI
  84. PC: 0000fffffffff848, LR: ffff80000009f760 DEBUG: imm: 7009, x0: fffffffff830
  85. PC: 0000fffffffff850, LR: ffff80000009f760 MSR REG EL2 SP: SP_EL2 IMM/REG: 2, VAL: 800370367000
  86. Switch SP
  87. PC: 0000fffffffff858, LR: ffff80000009f760 MSR REG EL2 SP: VBAR_EL2 IMM/REG: 3, VAL: 800000615000
  88. PC: 0000fffffffff85c, LR: ffff80000009f760 -------Switch to Kernel--------
  89. Switch SP
  90. Switch TTBR
  91. ERET: target pc: ffff8000000a48b4 lr: ffff80000009f760
  92. PC: ffff80000009f764, LR: ffff80000009f760 DEBUG: imm: 7720, x0: fffffffff830
  93. L0 HVC
  94. PC: ffff8000000a0a58, LR: ffff8000000a0a54 DEBUG: imm: 7999, x0: 0
  95. PC: ffff8000000a0a78, LR: ffff8000000a0a74 DEBUG: imm: 7012, x0: 20
  96. PC: ffff8000000a0aa4, LR: ffff8000000a0a84 DEBUG: imm: 7013, x0: ffff800000883000
  97. PC: ffff8000000a0ae0, LR: ffff8000000a0adc DEBUG: imm: 7085, x0: 2a
  98.  
  99. random: nonblocking pool is initialized
  100. PC: ffff8000000d39ac, LR: ffff8000000d39a4 -------Switch to Lowvisor--------
  101. Switch SP
  102. Switch TTBR
  103. INJECT to L1: target pc: 800000615400
  104. PC: 0000800000614804, LR: ffff8000000d39a4 DEBUG: imm: 7333, x0: 0
  105. PC: 0000800000614808, LR: ffff8000000d39a4 -------Switch to Kernel--------
  106. Switch SP
  107. Switch TTBR
  108. ERET: target pc: ffff8000000d39ac lr: ffff8000000d39a4
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