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-- Company:
-- Engineer:
--
-- Create Date: 03/16/2019 06:27:39 PM
-- Design Name:
-- Module Name: mpg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mpg is
    Port( CLK : in  std_logic;
          BTN : in  std_logic;
          EN  : out std_logic);
end mpg;

architecture Behavioral of mpg is

signal q1,q2,q3 : std_logic := '0';
signal count : std_logic_vector (15 downto 0) := x"0000";

begin

    en <= Q2 AND (not Q3);

    process (clk)
    begin
        if rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;


    process (count, btn, clk)
    begin
        if rising_edge(clk) then
            if count = x"FFFF" then
                Q1 <= btn;
            end if;
        end if;
    end process;

    process (clk)
    begin
        if rising_edge(clk) then
            Q2 <= Q1;
            Q3 <= Q2;
        end if;
    end process;

end Behavioral;