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redmi ax6000 serial log

hardc0der
Mar 6th, 2023
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  1.  
  2. 03:06:50.216 ->
  3. F0: 102B 0000
  4. 03:06:50.216 ->
  5. FA: 1040 0000
  6. 03:06:50.216 ->
  7. FA: 1040 0000 [0200]
  8. 03:06:50.216 ->
  9. F9: 0000 0000
  10. 03:06:50.216 ->
  11. V0: 0000 0000 [0001]
  12. 03:06:50.216 ->
  13. 00: 0000 0000
  14. 03:06:50.216 ->
  15. BP: 2400 0041 [0000]
  16. 03:06:50.216 ->
  17. G0: 1190 0000
  18. 03:06:50.216 ->
  19. EC: 0000 0000 [1000]
  20. 03:06:50.216 ->
  21. T0: 0000 022F [010F]
  22. 03:06:50.216 ->
  23. Jump to BL
  24. 03:06:50.216 ->
  25. 03:06:50.216 ->
  26. NOTICE: BL2: v2.6(release):82a3fbe10a-dirty
  27. 03:06:50.254 -> NOTICE: BL2: Built : 16:56:29, Mar 29 2022
  28. 03:06:50.254 -> INFO: BL2: Doing platform setup
  29. 03:06:50.254 -> NOTICE: WDT: disabled
  30. 03:06:50.394 -> NOTICE: CPU: MT7986 (2000MHz)
  31. 03:06:50.394 -> NOTICE: EMI: Using DDR4 settings
  32. 03:06:50.394 -> before ctrl3 = 0x0
  33. 03:06:50.394 -> clear request & ack
  34. 03:06:50.394 -> after ctrl3 = 0x0
  35. 03:06:50.394 -> DVFSRC_SUCCESS 0
  36. 03:06:50.432 -> dump drm registers data:
  37. 03:06:50.432 -> 1001d000 | 00000000 00000000 00000000 00000000
  38. 03:06:50.432 -> 1001d010 | 00000000 00000000 00000000 00000000
  39. 03:06:50.432 -> 1001d020 | 00000000 00000000 00000000 00000000
  40. 03:06:50.432 -> 1001d030 | 00a083f1 000003ff 00100000 00000000
  41. 03:06:50.432 -> 1001d040 | 00000000 00000000 00020303 000000ff
  42. 03:06:50.432 -> 1001d050 | 00000000 00000000 00000000 00000000
  43. 03:06:50.432 -> 1001d060 | 00000002 00000000 00000000 00000000
  44. 03:06:50.432 -> drm: 500 = 0x8
  45. 03:06:50.432 -> toprgu: 80 = 0x0
  46. 03:06:50.432 -> [DDR Reserve] ddr reserve mode not be enabled yet
  47. 03:06:50.469 -> Save DRM_DEBUG_CTL(0xa083f1)
  48. 03:06:50.469 -> DRM_LATCH_CTL : 0x27e71
  49. 03:06:50.469 -> DRM_LATCH_CTL2: 0x200a0
  50. 03:06:50.469 -> drm_update_reg: 1, bits: 0x8000, addr: 0x1001d030, val: 0xa083f1
  51. 03:06:50.469 -> drm_update_reg: 0, bits: 0x80000, addr: 0x1001d030, val: 0xa083f1
  52. 03:06:50.469 -> drm_update_reg: 0, bits: 0x200, addr: 0x1001d034, val: 0x1ff
  53. 03:06:50.469 -> drm_update_reg: 0, bits: 0x200000, addr: 0x1001d034, val: 0x1ff
  54. 03:06:50.469 -> drm_update_reg: 0, bits: 0x100, addr: 0x1001d034, val: 0xff
  55. 03:06:50.507 -> MTK_DRM_DEBUG_CTL : 0xa083f1
  56. 03:06:50.507 -> MTK_DRM_DEBUG_CTL2: 0xff
  57. 03:06:50.507 -> drm_update_reg: 0, bits: 0x4000, addr: 0x1001d030, val: 0xa083f1
  58. 03:06:50.507 -> DRM DDR reserve mode FAIL! a083f1
  59. 03:06:50.507 -> DDR RESERVE Success 0
  60. 03:06:50.507 -> drm_update_reg: 0, bits: 0x2000, addr: 0x1001d030, val: 0xa083f1
  61. 03:06:50.507 -> drm_update_reg: 0, bits: 0x1000, addr: 0x1001d030, val: 0xa083f1
  62. 03:06:50.507 -> [DRAM] into mt_set_emi
  63. 03:06:50.507 -> [EMI] ComboMCP not ready, using default setting
  64. 03:06:50.507 ->
  65. 03:06:50.507 -> Init_DRAM:2139: init PCDDR4 dram Start
  66. 03:06:50.543 -> [MD32_INIT] in c code >>>>>>
  67. 03:06:50.543 -> [MD32_INIT] 3
  68. 03:06:50.543 -> [MD32_INIT] 4
  69. 03:06:50.543 -> [MD32_INIT] 5
  70. 03:06:50.543 -> [MD32_INIT] 6
  71. 03:06:50.543 -> [MD32_INIT] V22 add 1
  72. 03:06:50.543 -> [MD32_INIT] V22 add 1 end
  73. 03:06:50.543 -> [MD32_INIT] 7
  74. 03:06:50.543 -> [MD32_INIT] 8
  75. 03:06:50.543 -> [MD32_INIT] 9
  76. 03:06:50.543 -> [MD32_INIT] 10
  77. 03:06:50.543 -> [MD32_INIT] 11
  78. 03:06:50.543 -> [MD32_INIT] 12
  79. 03:06:50.543 -> [MD32_INIT] 13
  80. 03:06:50.543 -> [MD32_INIT] 14
  81. 03:06:50.543 -> [MD32_INIT] 15
  82. 03:06:50.543 -> [MD32_INIT] 16
  83. 03:06:50.543 -> [MD32_INIT] 17
  84. 03:06:50.543 -> [MD32_INIT] 18
  85. 03:06:50.543 -> [MD32_INIT] 19
  86. 03:06:50.543 -> [MD32_INIT] 20
  87. 03:06:50.581 -> [MD32_INIT] 21
  88. 03:06:50.581 -> [MD32_INIT] 22
  89. 03:06:50.581 -> [MD32_INIT] 23
  90. 03:06:50.581 -> [MD32_INIT] 28
  91. 03:06:50.581 -> [MD32_INIT] 29
  92. 03:06:50.581 -> [MD32_INIT] 30 for RTMRW, if have
  93. 03:06:50.581 -> [MD32_INIT] in c code <<<<<<
  94. 03:06:50.581 -> [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
  95. 03:06:50.581 ->
  96. 03:06:50.581 ->
  97. 03:06:50.581 -> [Bian_co] ETT version 0.0.0.1
  98. 03:06:50.581 -> dram_type 4, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=136
  99. 03:06:50.581 ->
  100. 03:06:50.581 -> Read voltage for 1600, 0
  101. 03:06:50.581 -> Vio18 = 0
  102. 03:06:50.581 -> Vcore = 0
  103. 03:06:50.581 -> Vdram = 0
  104. 03:06:50.581 -> Vddq = 0
  105. 03:06:50.581 -> Vmddr = 0
  106. 03:06:50.581 -> == DRAMC_CTX_T ==
  107. 03:06:50.581 -> support_channel_num: 1
  108. 03:06:50.581 -> channel: 0
  109. 03:06:50.615 -> support_rank_num: 1
  110. 03:06:50.615 -> rank: 0
  111. 03:06:50.615 -> freq_sel: 22
  112. 03:06:50.615 -> shu_type: 0
  113. 03:06:50.615 -> dram_type: 4
  114. 03:06:50.615 -> dram_fsp: 0
  115. 03:06:50.615 -> odt_onoff: 1
  116. 03:06:50.615 -> DBI_R_onoff: 0, 0
  117. 03:06:50.615 -> DBI_W_onoff: 0, 0
  118. 03:06:50.615 -> data_width: 16
  119. 03:06:50.615 -> test2_1: 0x55000000
  120. 03:06:50.615 -> test2_2: 0xaa000100
  121. 03:06:50.615 -> frequency: 1600
  122. 03:06:50.615 -> freqGroup: 1600
  123. 03:06:50.653 -> u1PLLMode: 0
  124. 03:06:50.653 -> dram type 6
  125. 03:06:50.653 -> ===============================================================================
  126. 03:06:50.653 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  127. 03:06:50.653 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  128. 03:06:50.653 -> ===============================================================================
  129. 03:06:50.653 -> OCD DRVP=0 ,CALOUT=0
  130. 03:06:50.653 -> OCD DRVP=1 ,CALOUT=0
  131. 03:06:50.653 -> OCD DRVP=2 ,CALOUT=0
  132. 03:06:50.653 -> OCD DRVP=3 ,CALOUT=0
  133. 03:06:50.653 -> OCD DRVP=4 ,CALOUT=0
  134. 03:06:50.653 -> OCD DRVP=5 ,CALOUT=0
  135. 03:06:50.653 -> OCD DRVP=6 ,CALOUT=0
  136. 03:06:50.698 -> OCD DRVP=7 ,CALOUT=0
  137. 03:06:50.698 -> OCD DRVP=8 ,CALOUT=0
  138. 03:06:50.698 -> OCD DRVP=9 ,CALOUT=1
  139. 03:06:50.698 ->
  140. 03:06:50.698 -> OCD DRVP calibration OK! DRVP=9
  141. 03:06:50.698 ->
  142. 03:06:50.698 -> OCD DRVN=0 ,CALOUT=1
  143. 03:06:50.698 -> OCD DRVN=1 ,CALOUT=1
  144. 03:06:50.698 -> OCD DRVN=2 ,CALOUT=1
  145. 03:06:50.698 -> OCD DRVN=3 ,CALOUT=1
  146. 03:06:50.698 -> OCD DRVN=4 ,CALOUT=1
  147. 03:06:50.698 -> OCD DRVN=5 ,CALOUT=1
  148. 03:06:50.698 -> OCD DRVN=6 ,CALOUT=0
  149. 03:06:50.698 ->
  150. 03:06:50.698 -> OCD DRVN calibration OK! DRVN=6
  151. 03:06:50.698 ->
  152. 03:06:50.698 -> [SwImpedanceCal] DRVP=9, DRVN=6
  153. 03:06:50.698 -> freq_region=0, Reg: DRVP=11, DRVN=8, ODTP=6
  154. 03:06:50.698 -> MEM_TYPE=6, freq_sel=22
  155. 03:06:50.698 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  156. 03:06:50.764 -> PCDDR4 DRAM CONFIGURATION
  157. 03:06:50.764 -> ===================================
  158. 03:06:50.764 -> CWL = 0x7
  159. 03:06:50.764 -> RTT_NORM = 0x6
  160. 03:06:50.764 -> CL = 0xb
  161. 03:06:50.764 -> AL = 0x0
  162. 03:06:50.764 -> BL = 0x0
  163. 03:06:50.764 -> RBT = 0x0
  164. 03:06:50.764 -> WR = 0x8
  165. 03:06:50.764 -> ===================================
  166. 03:06:50.764 -> ===================================
  167. 03:06:50.764 -> ANA top config
  168. 03:06:50.764 -> ===================================
  169. 03:06:50.764 -> ASYNC_MODE = 3
  170. 03:06:50.764 -> DLL_ASYNC_EN = 1
  171. 03:06:50.764 -> ALL_SLAVE_EN = 0
  172. 03:06:50.764 -> NEW_RANK_MODE = 0
  173. 03:06:50.764 -> DLL_IDLE_MODE = 1
  174. 03:06:50.764 -> LP45_APHY_COMB_EN = 1
  175. 03:06:50.764 -> TX_ODT_DIS = 0
  176. 03:06:50.764 -> NEW_8X_MODE = 0
  177. 03:06:50.764 -> ===================================
  178. 03:06:50.764 -> ===================================
  179. 03:06:50.764 -> data_rate = 3200
  180. 03:06:50.764 -> CKR = 1
  181. 03:06:50.764 -> DQ_P2S_RATIO = 8
  182. 03:06:50.811 -> ===================================
  183. 03:06:50.811 -> CA_P2S_RATIO = 8
  184. 03:06:50.811 -> DQ_CA_OPEN = 0
  185. 03:06:50.811 -> DQ_SEMI_OPEN = 0
  186. 03:06:50.811 -> CA_SEMI_OPEN = 0
  187. 03:06:50.811 -> CA_FULL_RATE = 0
  188. 03:06:50.811 -> DQ_CKDIV4_EN = 0
  189. 03:06:50.811 -> CA_CKDIV4_EN = 0
  190. 03:06:50.811 -> CA_PREDIV_EN = 0
  191. 03:06:50.811 -> PH8_DLY = 31
  192. 03:06:50.811 -> SEMI_OPEN_CA_PICK_MCK_RATIO= 0
  193. 03:06:50.811 -> DQ_AAMCK_DIV = 4
  194. 03:06:50.811 -> CA_AAMCK_DIV = 4
  195. 03:06:50.811 -> CA_ADMCK_DIV = 4
  196. 03:06:50.811 -> DQ_TRACK_CA_EN = 0
  197. 03:06:50.866 -> CA_PICK = 1600
  198. 03:06:50.866 -> CA_MCKIO = 1600
  199. 03:06:50.866 -> MCKIO_SEMI = 0
  200. 03:06:50.866 -> PLL_FREQ = 3200
  201. 03:06:50.866 -> DQ_UI_PI_RATIO = 32
  202. 03:06:50.866 -> CA_UI_PI_RATIO = 0
  203. 03:06:50.866 -> ===================================
  204. 03:06:50.866 -> ===================================
  205. 03:06:50.866 -> memory_type:PCDDR4
  206. 03:06:50.866 -> GP_NUM : 1
  207. 03:06:50.866 -> SRAM_EN : 1
  208. 03:06:50.866 -> MD32_EN : 0
  209. 03:06:50.866 -> ===================================
  210. 03:06:50.866 -> ===========================================
  211. 03:06:50.866 -> HW_ZQCAL_config
  212. 03:06:50.866 -> ===========================================
  213. 03:06:50.866 -> ZQCALL is 0
  214. 03:06:50.866 -> TZQLAT is 27
  215. 03:06:50.866 -> ZQCSDUAL is 0
  216. 03:06:50.866 -> ZQCSCNT is 511
  217. 03:06:50.866 -> ===========================================
  218. 03:06:50.952 -> [ANA_INIT] >>>>>>>>>>>>>>
  219. 03:06:50.952 -> [ANA_ClockOff_Sequence] flow start
  220. 03:06:50.952 -> WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns start
  221. 03:06:50.952 -> WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns end
  222. 03:06:50.952 -> [ANA_ClockOff_Sequence] flow end
  223. 03:06:50.952 -> ============ PULL DRAM RESETB DOWN ============
  224. 03:06:50.952 -> ========== PULL DRAM RESETB DOWN end =========
  225. 03:06:50.952 -> ============ SUSPEND_ON ============
  226. 03:06:50.952 -> ============ SUSPEND_ON end ============
  227. 03:06:50.952 -> ============ SPM_control ============
  228. 03:06:50.952 -> ============ SPM_control end ============
  229. 03:06:50.952 -> <<<<<< [CONFIGURE PHASE]: ANA_TX
  230. 03:06:50.952 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
  231. 03:06:50.952 -> ===================================
  232. 03:06:50.952 -> data_rate = 3200,PCW = 0X7800
  233. 03:06:50.952 -> ===================================
  234. 03:06:50.952 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
  235. 03:06:50.952 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  236. 03:06:50.952 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  237. 03:06:50.952 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  238. 03:06:50.952 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  239. 03:06:50.952 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  240. 03:06:50.952 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  241. 03:06:50.952 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x0
  242. 03:06:51.009 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  243. 03:06:51.009 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  244. 03:06:51.009 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  245. 03:06:51.009 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  246. 03:06:51.009 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  247. 03:06:51.009 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  248. 03:06:51.009 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  249. 03:06:51.009 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  250. 03:06:51.009 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  251. 03:06:51.009 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60 PH8_DLY= 0x1f
  252. 03:06:51.009 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  253. 03:06:51.009 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
  254. 03:06:51.009 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  255. 03:06:51.009 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x61
  256. 03:06:51.009 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
  257. 03:06:51.057 -> [ANA_INIT] flow start
  258. 03:06:51.057 -> [ANA_INIT] PLL >>>>>>>>
  259. 03:06:51.057 -> [ANA_INIT] PLL <<<<<<<<
  260. 03:06:51.057 -> [ANA_INIT] MIDPI >>>>>>>>
  261. 03:06:51.057 -> [ANA_INIT] MIDPI <<<<<<<<
  262. 03:06:51.057 -> [ANA_INIT] DLL >>>>>>>>
  263. 03:06:51.057 -> [ANA_INIT] DLL <<<<<<<<
  264. 03:06:51.057 -> [ANA_INIT] flow end
  265. 03:06:51.057 -> [ANA_INIT] <<<<<<<<<<<<<
  266. 03:06:51.057 -> [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  267. 03:06:51.057 -> [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  268. 03:06:51.057 -> [Flow] Enable top DCM control >>>>>
  269. 03:06:51.057 -> [Flow] Enable top DCM control <<<<<
  270. 03:06:51.057 -> Enable DLL master slave shuffle
  271. 03:06:51.057 -> ==============================================================
  272. 03:06:51.131 -> Gating Mode config
  273. 03:06:51.131 -> ==============================================================
  274. 03:06:51.131 -> Config description:
  275. 03:06:51.131 -> RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
  276. 03:06:51.131 -> RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (Jade-like) 2: FIFO mode
  277. 03:06:51.131 -> SELPH_MODE 0: By rank 1: By Phase
  278. 03:06:51.131 -> ==============================================================
  279. 03:06:51.131 -> GAT_TRACK_EN = 1
  280. 03:06:51.131 -> RX_GATING_MODE = 2
  281. 03:06:51.131 -> RX_GATING_TRACK_MODE = 2
  282. 03:06:51.131 -> SELPH_MODE = 1
  283. 03:06:51.131 -> PICG_EARLY_EN = 1
  284. 03:06:51.131 -> VALID_LAT_VALUE = 0
  285. 03:06:51.131 -> ==============================================================
  286. 03:06:51.131 -> Enter into Gating configuration >>>>
  287. 03:06:51.131 -> Exit from Gating configuration <<<<
  288. 03:06:51.131 -> [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  289. 03:06:51.131 -> [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  290. 03:06:51.193 -> [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  291. 03:06:51.193 -> [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  292. 03:06:51.193 -> Enter into PICG configuration >>>>
  293. 03:06:51.193 -> Exit from PICG configuration <<<<
  294. 03:06:51.193 -> [DIG_SHUF_CONFIG] DCM_FUNCTION >>>>>>, group_id=0
  295. 03:06:51.193 -> [DIG_SHUF_CONFIG] DCM_FUNCTION <<<<<<, group_id=0
  296. 03:06:51.193 -> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 >>>>>
  297. 03:06:51.193 -> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 <<<<<
  298. 03:06:51.193 -> [DIG_HW_SHUF_ZQCAL_CFG] Group:0, Configuration Enter
  299. 03:06:51.193 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  300. 03:06:51.193 -> PCDDR4 DRAM CONFIGURATION
  301. 03:06:51.193 -> ===================================
  302. 03:06:51.193 -> CWL = 0x7
  303. 03:06:51.193 -> RTT_NORM = 0x6
  304. 03:06:51.268 -> CL = 0xb
  305. 03:06:51.268 -> AL = 0x0
  306. 03:06:51.268 -> BL = 0x0
  307. 03:06:51.268 -> RBT = 0x0
  308. 03:06:51.268 -> WR = 0x8
  309. 03:06:51.268 -> ===================================
  310. 03:06:51.268 -> [ReadLatency GET] MR_CL:[ReadLatency GET] MR_CL:UI_MCK_least is 1
  311. 03:06:51.268 -> RX_GW_selph_by_ps[0] is 12464
  312. 03:06:51.268 -> RX_GW_selph_by_ps[1] is 12464
  313. 03:06:51.268 -> RX_GW_selph_by_ps[2] is 12464
  314. 03:06:51.268 -> RX_GW_selph_by_ps[3] is 12464
  315. 03:06:51.268 -> ===================================
  316. 03:06:51.268 -> RX_path CONFIGURATION
  317. 03:06:51.268 -> ===================================
  318. 03:06:51.268 -> data_rate is 3200
  319. 03:06:51.268 -> dq_p2s_ratio is 8
  320. 03:06:51.268 -> ca_default_delay is 1
  321. 03:06:51.268 -> ca_ser_latency is 7
  322. 03:06:51.268 -> cs2RL_start is 1
  323. 03:06:51.268 -> byte_num is 2
  324. 03:06:51.268 -> rank_num is 2
  325. 03:06:51.268 -> RL[0] is 24
  326. 03:06:51.268 -> RL[1] is 24
  327. 03:06:51.268 -> RL_min is 24
  328. 03:06:51.268 -> RL_max is 24
  329. 03:06:51.268 -> TDQSCK[0] is 0
  330. 03:06:51.268 -> TDQSCK[1] is 0
  331. 03:06:51.268 -> TDQSCK[2] is 0
  332. 03:06:51.323 -> TDQSCK[3] is 0
  333. 03:06:51.323 -> dqsien_default_delay is 0
  334. 03:06:51.323 -> dqsien_ser_latency is 7
  335. 03:06:51.323 -> oe_ser_latency is 4
  336. 03:06:51.323 -> gating_window_ahead_dqs is 2
  337. 03:06:51.323 -> aphy_slice_delay is 11
  338. 03:06:51.323 -> aphy_dtc_delay is 100
  339. 03:06:51.323 -> aphy_lead_lag_margin is 16
  340. 03:06:51.323 -> dram_ui_ratio is 2
  341. 03:06:51.323 -> dq_ui_unit is 312
  342. 03:06:51.323 -> ca_ui_unit is 312
  343. 03:06:51.323 -> MCK_unit is 2496
  344. 03:06:51.323 -> dramc_dram_ratio is 4
  345. 03:06:51.323 -> CKR is 1
  346. 03:06:51.323 -> tRPRE_toggle is 0
  347. 03:06:51.323 -> tRPRE_static is 2
  348. 03:06:51.323 -> tRPST is 0
  349. 03:06:51.323 -> DQSIENMODE is 1
  350. 03:06:51.323 -> BL is 16
  351. 03:06:51.323 -> FAKE_1TO16_MODE is 0
  352. 03:06:51.323 -> SVA_1_10_t2_SPEC is 11
  353. 03:06:51.413 -> read_cmd_out is 1
  354. 03:06:51.413 -> ca_MCKIO_ui_unit is 312
  355. 03:06:51.413 -> ca_p2s_ratio is 8
  356. 03:06:51.413 -> TDQSCK_min_SPEC is 0
  357. 03:06:51.413 -> TDQSCK_max_SPEC is 360
  358. 03:06:51.413 -> TX_pipeline is 1
  359. 03:06:51.413 -> RX_pipeline is 1
  360. 03:06:51.413 -> NEW_RANK_MODE is 0
  361. 03:06:51.413 -> close_loop_mode is 1
  362. 03:06:51.413 -> ===================================
  363. 03:06:51.413 -> ===================================
  364. 03:06:51.413 -> RX_path RG value
  365. 03:06:51.413 -> ===================================
  366. 03:06:51.413 -> RX_UI_P0[0] is 15
  367. 03:06:51.413 -> RX_UI_P0[1] is 15
  368. 03:06:51.413 -> RX_UI_P0[2] is 15
  369. 03:06:51.413 -> RX_UI_P0[3] is 15
  370. 03:06:51.413 -> RX_UI_P1[0] is 19
  371. 03:06:51.413 -> RX_UI_P1[1] is 19
  372. 03:06:51.413 -> RX_UI_P1[2] is 19
  373. 03:06:51.413 -> RX_UI_P1[3] is 19
  374. 03:06:51.413 -> RX_PI[0] is 31
  375. 03:06:51.413 -> RX_PI[1] is 31
  376. 03:06:51.413 -> RX_PI[2] is 31
  377. 03:06:51.413 -> RX_PI[3] is 31
  378. 03:06:51.413 -> DQSINCTL is 3
  379. 03:06:51.413 -> DATLAT_DSEL is 11
  380. 03:06:51.413 -> DATLAT is 12
  381. 03:06:51.413 -> DATLAT_DSEL_PHY is 12
  382. 03:06:51.413 -> DLE_EXTEND is 1
  383. 03:06:51.413 -> RX_IN_GATE_EN_HEAD is 0
  384. 03:06:51.413 -> RX_IN_GATE_EN_TAIL is 0
  385. 03:06:51.455 -> RX_IN_BUFF_EN_HEAD is 2
  386. 03:06:51.455 -> RX_IN_BUFF_EN_TAIL is 0
  387. 03:06:51.455 -> RX_IN_GATE_EN_PRE_OFFSET is 2
  388. 03:06:51.455 -> RANKINCTL_ROOT1 is 1
  389. 03:06:51.455 -> RANKINCTL is 1
  390. 03:06:51.455 -> RANKINCTL_STB is 2
  391. 03:06:51.455 -> RANKINCTL_RXDLY is 0
  392. 03:06:51.455 -> SHU_GW_THRD_POS is 42
  393. 03:06:51.455 -> SHU_GW_THRD_NEG is 0
  394. 03:06:51.455 -> RDSEL_TRACK_EN is 0
  395. 03:06:51.455 -> RDSEL_HWSAVE_MSK is 1
  396. 03:06:51.455 -> DMDATLAT_i is 12
  397. 03:06:51.455 -> RODTEN is 0
  398. 03:06:51.455 -> RODT is 488601885
  399. 03:06:51.531 -> RODTE is 1
  400. 03:06:51.531 -> RODTE2 is 1
  401. 03:06:51.531 -> ODTEN_MCK_P0[4] is 0
  402. 03:06:51.531 -> ODTEN_MCK_P1[4] is 0
  403. 03:06:51.531 -> ODTEN_UI_P0[4] is 0
  404. 03:06:51.531 -> ODTEN_UI_P1[4] is 0
  405. 03:06:51.531 -> RX_RANK_DQS_LAT is 0
  406. 03:06:51.531 -> RX_RANK_DQ_LAT is 1
  407. 03:06:51.531 -> RANKINCTL_PHY is 5
  408. 03:06:51.531 -> RANK_SEL_LAT_CA is 0
  409. 03:06:51.531 -> RANK_SEL_LAT_B0 is 0
  410. 03:06:51.531 -> RANK_SEL_LAT_B1 is 0
  411. 03:06:51.531 -> RANK_SEL_STB_EN is 0
  412. 03:06:51.531 -> RANK_SEL_RXDLY_TRACK is 0
  413. 03:06:51.531 -> RANK_SEL_STB_TRACK is 1
  414. 03:06:51.531 -> RANK_SEL_STB_PHASE_EN is 1
  415. 03:06:51.531 -> RANK_SEL_PHSINCTL is 2
  416. 03:06:51.531 -> RANK_SEL_STB_UI_MINUS is 2
  417. 03:06:51.531 -> RANK_SEL_STB_UI_PLUS is 0
  418. 03:06:51.531 -> RANK_SEL_MCK_P0 is 0
  419. 03:06:51.531 -> RANK_SEL_UI_P0 is 0
  420. 03:06:51.531 -> RANK_SEL_MCK_P1 is 1
  421. 03:06:51.531 -> RANK_SEL_UI_P1 is 0
  422. 03:06:51.531 -> R0DQSIENLLMTEN is 1
  423. 03:06:51.531 -> R0DQSIENLLMT is 96
  424. 03:06:51.531 -> R0DQSIENHLMTEN is 1
  425. 03:06:51.531 -> R0DQSIENHLMT is 63
  426. 03:06:51.531 -> R1DQSIENLLMTEN is 1
  427. 03:06:51.531 -> R1DQSIENLLMT is 96
  428. 03:06:51.597 -> R1DQSIENHLMTEN is 1
  429. 03:06:51.597 -> R1DQSIENHLMT is 63
  430. 03:06:51.597 -> DQSIEN_FIFO_DEPTH_HALF is 1
  431. 03:06:51.597 -> ===================================
  432. 03:06:51.597 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  433. 03:06:51.597 -> PCDDR4 DRAM CONFIGURATION
  434. 03:06:51.597 -> ===================================
  435. 03:06:51.597 -> CWL = 0x7
  436. 03:06:51.597 -> RTT_NORM = 0x6
  437. 03:06:51.597 -> CL = 0xb
  438. 03:06:51.597 -> AL = 0x0
  439. 03:06:51.597 -> BL = 0x0
  440. 03:06:51.597 -> RBT = 0x0
  441. 03:06:51.597 -> WR = 0x8
  442. 03:06:51.597 -> ===================================
  443. 03:06:51.597 -> [WriteLatency GET] MR_CWL:[WriteLatency GET] MR_CWL:=====================================
  444. 03:06:51.597 -> print TX_path_config
  445. 03:06:51.597 -> =====================================
  446. 03:06:51.597 -> data_ratio is 3200
  447. 03:06:51.597 -> dq_p2s_ratio is 8
  448. 03:06:51.597 -> cs2WL_start is 1
  449. 03:06:51.670 -> byte_num is 2
  450. 03:06:51.670 -> rank_num is 2
  451. 03:06:51.670 -> CKR is 1
  452. 03:06:51.670 -> DBI_WR is 0
  453. 03:06:51.670 -> dly_1T_by_FDIV2 is 0
  454. 03:06:51.670 -> WL[0] is 20
  455. 03:06:51.670 -> WL[1] is 20
  456. 03:06:51.670 -> TDQSS[0][0] is 156
  457. 03:06:51.670 -> TDQSS[0][1] is 156
  458. 03:06:51.670 -> TDQSS[1][0] is 156
  459. 03:06:51.670 -> TDQSS[1][1] is 156
  460. 03:06:51.670 -> TDQS2DQ[0][0] is 0
  461. 03:06:51.670 -> TDQS2DQ[0][1] is 0
  462. 03:06:51.670 -> TDQS2DQ[1][0] is 0
  463. 03:06:51.670 -> TDQS2DQ[1][1] is 0
  464. 03:06:51.670 -> ca_p2s_ratio is 8
  465. 03:06:51.670 -> ca_default_dly is 1
  466. 03:06:51.670 -> ca_default_pi is 0
  467. 03:06:51.670 -> ca_ser_latency is 7
  468. 03:06:51.670 -> dqs_ser_laterncy is 7
  469. 03:06:51.670 -> dqs_default_dly is 5
  470. 03:06:51.670 -> dqs_oe_default_dly is 2
  471. 03:06:51.670 -> dq_ser_laterncy is 7
  472. 03:06:51.670 -> MCK_unit is 2496
  473. 03:06:51.670 -> dq_ui_unit is 312
  474. 03:06:51.727 -> ca_unit is 312
  475. 03:06:51.727 -> ca_MCKIO_unit is 312
  476. 03:06:51.727 -> ca_frate is 0
  477. 03:06:51.727 -> TX_ECC is 0
  478. 03:06:51.727 -> TWPRE is 4
  479. 03:06:51.727 -> OE_pre_margin is 400
  480. 03:06:51.727 -> OE_pst_margin is 500
  481. 03:06:51.727 -> OE_downgrade is 1
  482. 03:06:51.727 -> aphy_slice_dly is 11
  483. 03:06:51.727 -> aphy_dtc_dly is 100
  484. 03:06:51.727 -> aphy_tx_dly is 16
  485. 03:06:51.727 -> DDRPHY_CLK_EN_COMB_TX_OPT is 1
  486. 03:06:51.727 -> NEW_RANK_MODE is 0
  487. 03:06:51.727 -> close_loop_mode is 1
  488. 03:06:51.727 -> TXP_WORKAROUND_OPT is 0
  489. 03:06:51.727 -> ui2pi_ratio is 32
  490. 03:06:51.727 -> XRTW2W_PI_mute_time is 7
  491. 03:06:51.727 -> fake_mode is 0
  492. 03:06:51.727 -> ===========================================
  493. 03:06:51.727 -> TX_DQ_UI_OE_pre is 2
  494. 03:06:51.775 -> TX_DQS_UI_OE_pre is 1
  495. 03:06:51.775 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  496. 03:06:51.775 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  497. 03:06:51.775 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  498. 03:06:51.775 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  499. 03:06:51.775 -> ===========================================
  500. 03:06:51.775 -> print TX_path_attribution
  501. 03:06:51.775 -> ===========================================
  502. 03:06:51.775 -> TX_DQ_MCK_OE[0][0] is 2
  503. 03:06:51.775 -> TX_DQ_MCK_OE[0][1] is 2
  504. 03:06:51.775 -> TX_DQ_MCK_OE[1][0] is 2
  505. 03:06:51.775 -> TX_DQ_MCK_OE[1][1] is 2
  506. 03:06:51.840 -> TX_DQ_UI_OE[0][0] is 6
  507. 03:06:51.840 -> TX_DQ_UI_OE[0][1] is 6
  508. 03:06:51.840 -> TX_DQ_UI_OE[1][0] is 6
  509. 03:06:51.840 -> TX_DQ_UI_OE[1][1] is 6
  510. 03:06:51.840 -> TX_DQ_MCK[0][0] is 3
  511. 03:06:51.840 -> TX_DQ_MCK[0][1] is 3
  512. 03:06:51.840 -> TX_DQ_MCK[1][0] is 3
  513. 03:06:51.840 -> TX_DQ_MCK[1][1] is 3
  514. 03:06:51.840 -> TX_DQ_UI[0][0] is 2
  515. 03:06:51.840 -> TX_DQ_UI[0][1] is 2
  516. 03:06:51.840 -> TX_DQ_UI[1][0] is 2
  517. 03:06:51.840 -> TX_DQ_UI[1][1] is 2
  518. 03:06:51.840 -> TX_DQ_PI[0][0] is 0
  519. 03:06:51.840 -> TX_DQ_PI[0][1] is 0
  520. 03:06:51.840 -> TX_DQ_PI[1][0] is 0
  521. 03:06:51.840 -> TX_DQ_PI[1][1] is 0
  522. 03:06:51.840 -> TX_DQ_UIPI_all[0][0] is 0
  523. 03:06:51.905 -> TX_DQ_UIPI_all[0][1] is 0
  524. 03:06:51.905 -> TX_DQ_UIPI_all[1][0] is 0
  525. 03:06:51.905 -> TX_DQ_UIPI_all[1][1] is 0
  526. 03:06:51.905 -> TX_DQ_dlyline[0][0] is 0
  527. 03:06:51.905 -> TX_DQ_dlyline[0][1] is 0
  528. 03:06:51.905 -> TX_DQ_dlyline[1][0] is 0
  529. 03:06:51.905 -> TX_DQ_dlyline[1][1] is 0
  530. 03:06:51.905 -> TX_DQS_MCK_OE[0][0] is 2
  531. 03:06:51.905 -> TX_DQS_MCK_OE[0][1] is 2
  532. 03:06:51.905 -> TX_DQS_MCK_OE[1][0] is 2
  533. 03:06:51.905 -> TX_DQS_MCK_OE[1][1] is 2
  534. 03:06:51.905 -> TX_DQS_UI_OE[0][0] is 6
  535. 03:06:51.905 -> TX_DQS_UI_OE[0][1] is 6
  536. 03:06:51.905 -> TX_DQS_UI_OE[1][0] is 6
  537. 03:06:51.905 -> TX_DQS_UI_OE[1][1] is 6
  538. 03:06:51.905 -> TX_DQS_MCK[0][0] is 3
  539. 03:06:51.905 -> TX_DQS_MCK[0][1] is 3
  540. 03:06:51.905 -> TX_DQS_MCK[1][0] is 3
  541. 03:06:51.978 -> TX_DQS_MCK[1][1] is 3
  542. 03:06:51.978 -> TX_DQS_UI[0][0] is 1
  543. 03:06:51.978 -> TX_DQS_UI[0][1] is 1
  544. 03:06:51.978 -> TX_DQS_UI[1][0] is 1
  545. 03:06:51.978 -> TX_DQS_UI[1][1] is 1
  546. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_OPT is 1
  547. 03:06:51.978 -> TX_DQS_PI[0][0] is 16
  548. 03:06:51.978 -> TX_DQS_PI[0][1] is 16
  549. 03:06:51.978 -> TX_DQS_PI[1][0] is 16
  550. 03:06:51.978 -> TX_DQS_PI[1][1] is 16
  551. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_PICG_CNT is 2
  552. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 is 3
  553. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 is 4
  554. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0 is 3
  555. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1 is 4
  556. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P0 is 3
  557. 03:06:51.978 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P1 is 4
  558. 03:06:51.978 -> DPHY_TX_DCM_EXTCNT is 0
  559. 03:06:51.978 -> TX_PI_UPD_MODE is 1
  560. 03:06:51.978 -> TX_PI_UPDCTL_B0 is 0
  561. 03:06:52.034 -> TX_PI_UPDCTL_B1 is 0
  562. 03:06:52.034 -> TX_RANKINCTL_ROOT is 0
  563. 03:06:52.034 -> TX_RANKINCTL is 1
  564. 03:06:52.034 -> TX_RANKINCTL_TXDLY is 2
  565. 03:06:52.034 -> DDRPHY_CLK_DYN_GATING_SEL is 5
  566. 03:06:52.034 -> DDRPHY_CLK_EN_OPT is 1
  567. 03:06:52.034 -> ARPI_CMD is 0
  568. 03:06:52.034 -> TDMY is 9
  569. 03:06:52.034 -> TXOEN_AUTOSET_DQ_OFFSET is 3
  570. 03:06:52.034 -> TXOEN_AUTOSET_DQS_OFFSET is 3
  571. 03:06:52.034 -> TXOEN_AUTOSET_EN is 1
  572. 03:06:52.034 -> TXPICG_AUTOSET_OPT is 0
  573. 03:06:52.034 -> TXPICG_AUTOSET_EN is 1
  574. 03:06:52.034 -> TXPICG_DQ_MCK_OFFSET_LAG is 0
  575. 03:06:52.034 -> TXPICG_DQS_MCK_OFFSET_LAG is 0
  576. 03:06:52.134 -> TXPICG_DQ_UI_OFFSET_LEAD is 0
  577. 03:06:52.134 -> TXPICG_DQ_UI_OFFSET_LAG is 1
  578. 03:06:52.134 -> TXPICG_DQS_UI_OFFSET_LEAD is 1
  579. 03:06:52.134 -> TXPICG_DQS_UI_OFFSET_LAG is 0
  580. 03:06:52.134 -> ===========================================
  581. 03:06:52.134 -> set APHY_PI_CKCGH_CNT is 4 when not fake_mode, cur data_rate is 3200
  582. 03:06:52.134 -> [DIG_SHUF_CONFIG] MISC >>>>>, group_id=0
  583. 03:06:52.134 -> [DIG_SHUF_CONFIG] MISC <<<<<<, group_id=0
  584. 03:06:52.134 -> [DIG_SHUF_CONFIG] DBI >>>>>>, group_id=0
  585. 03:06:52.134 -> [DIG_SHUF_CONFIG] DBI <<<<<<, group_id=0
  586. 03:06:52.134 -> dramc_dram_ratio: 4
  587. 03:06:52.134 -> DDR4_DivMode: 1
  588. 03:06:52.134 -> freq_index: 1600
  589. 03:06:52.134 -> match AC timing 1
  590. 03:06:52.134 -> [DDR4_ac_timing_setting]start
  591. 03:06:52.134 -> [PC4 WR preamble settings]>>>>>>>> group_id = 0.
  592. 03:06:52.134 -> [PC4 WR preamble settings]<<<<<<<< group_id = 0.
  593. 03:06:52.134 -> clk_dramc_ref_sel FREQ=16
  594. 03:06:52.134 -> fmem_ck_bfe_dcm_ch0 FREQ=253
  595. 03:06:52.134 -> fmem_ck_aft_dcm_ch0 FREQ=253
  596. 03:06:52.134 -> SetClkFreeRun enter => DRAM clock free run mode = ON.
  597. 03:06:52.134 -> [DDR4] Pull Down reset.
  598. 03:06:52.134 -> [DDR4] cke fix low 10ns at least.
  599. 03:06:52.134 -> [DDR4] Delay 200 us.
  600. 03:06:52.134 -> [DDR4] Pull Up reset.
  601. 03:06:52.134 -> [DDR4] Delay 500 us.
  602. 03:06:52.134 -> [DDR4] DRAM initilization RK:0 Enter >>>>>>>>
  603. 03:06:52.134 -> [DDR4] Delay TXPR TRFC+10ns - 350ns(8Gb density)+10ns
  604. 03:06:52.134 -> [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:3-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:4-OP:0x[DDR4_MRS] RK:0-MA:5-OP:0x[DDR4] DQ Vref calibration>>>>>>>
  605. 03:06:52.190 -> [DDR4] DQ Vref Enable DQ vref calibration.
  606. 03:06:52.190 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQE-150ns
  607. 03:06:52.190 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] DQ Vref modify range and value
  608. 03:06:52.190 -> [DDR4] DQ Vref Exit DQ vref calibration.
  609. 03:06:52.190 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQx-150ns
  610. 03:06:52.190 -> [DDR4] DQ Vref calibration<<<<<<<
  611. 03:06:52.190 -> [DDR4_MRS] RK:0-MA:0-OP:0x[DDR4_ZQ] RK:0 Enter >>>>>>>>
  612. 03:06:52.190 -> [DDR4_ZQ] RK:0 Exit <<<<<<<<
  613. 03:06:52.190 -> [DDR4] Delay ZQinit - 718ns for 1333 at least max(512Mck,640ns)
  614. 03:06:52.190 -> [DDR4] DRAM initilization RK:0 Exit <<<<<<<
  615. 03:06:52.190 -> [DDR4] Enable refresh.....All bank refresh only
  616. 03:06:52.190 -> SetClkFreeRun enter => DRAM clock free run mode = OFF.
  617. 03:06:52.240 -> [DIG_HW_NONSHUF_ZQCAL_SWITCH],Configuration Enter
  618. 03:06:52.240 -> [DIG_HW_NONSHUF_DQSG_SWITCH],Configuration Enter
  619. 03:06:52.240 -> SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
  620. 03:06:52.240 -> [MiockJmeterHQA]
  621. 03:06:52.240 -> ===============================================================================
  622. 03:06:52.240 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  623. 03:06:52.240 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  624. 03:06:52.240 -> ===============================================================================
  625. 03:06:52.240 ->
  626. 03:06:52.240 -> [DramcMiockJmeter] u1RxGatingPI = 0
  627. 03:06:52.240 -> 0 : 2282, 2282
  628. 03:06:52.240 -> 1 : 2276, 2276
  629. 03:06:52.240 -> 2 : 2272, 2272
  630. 03:06:52.240 -> 3 : 2271, 2271
  631. 03:06:52.240 -> 4 : 2271, 2271
  632. 03:06:52.240 -> 5 : 2271, 2271
  633. 03:06:52.305 -> 6 : 2271, 2271
  634. 03:06:52.305 -> 7 : 2272, 2272
  635. 03:06:52.305 -> 8 : 2272, 2272
  636. 03:06:52.305 -> 9 : 2272, 2272
  637. 03:06:52.305 -> 10 : 2271, 2271
  638. 03:06:52.305 -> 11 : 2272, 2272
  639. 03:06:52.305 -> 12 : 2272, 2272
  640. 03:06:52.305 -> 13 : 2271, 2271
  641. 03:06:52.305 -> 14 : 2271, 2271
  642. 03:06:52.305 -> 15 : 2272, 2272
  643. 03:06:52.305 -> 16 : 2271, 2271
  644. 03:06:52.305 -> 17 : 2276, 2276
  645. 03:06:52.305 -> 18 : 2272, 2272
  646. 03:06:52.305 -> 19 : 2272, 2272
  647. 03:06:52.305 -> 20 : 2271, 2271
  648. 03:06:52.305 -> 21 : 2276, 2276
  649. 03:06:52.305 -> 22 : 2272, 2272
  650. 03:06:52.305 -> 23 : 2272, 2272
  651. 03:06:52.305 -> 24 : 2271, 2271
  652. 03:06:52.305 -> 25 : 2272, 2272
  653. 03:06:52.305 -> 26 : 2271, 2271
  654. 03:06:52.305 -> 27 : 2271, 2271
  655. 03:06:52.305 -> 28 : 2272, 2272
  656. 03:06:52.305 -> 29 : 2271, 2271
  657. 03:06:52.305 -> 30 : 2272, 2272
  658. 03:06:52.305 -> 31 : 2272, 2272
  659. 03:06:52.305 -> 32 : 2271, 2271
  660. 03:06:52.305 -> 33 : 2271, 2271
  661. 03:06:52.305 -> 34 : 2272, 2272
  662. 03:06:52.305 -> 35 : 2272, 2268
  663. 03:06:52.305 -> 36 : 2271, 214
  664. 03:06:52.305 -> 37 : 2271, 0
  665. 03:06:52.305 -> 38 : 2272, 0
  666. 03:06:52.305 -> 39 : 2272, 0
  667. 03:06:52.305 -> 40 : 2272, 0
  668. 03:06:52.305 -> 41 : 2272, 0
  669. 03:06:52.305 -> 42 : 2272, 0
  670. 03:06:52.305 -> 43 : 2272, 0
  671. 03:06:52.305 -> 44 : 2271, 0
  672. 03:06:52.305 -> 45 : 2267, 0
  673. 03:06:52.305 -> 46 : 2271, 0
  674. 03:06:52.305 -> 47 : 2272, 0
  675. 03:06:52.305 -> 48 : 2271, 0
  676. 03:06:52.305 -> 49 : 2276, 0
  677. 03:06:52.369 -> 50 : 2272, 0
  678. 03:06:52.369 -> 51 : 2276, 0
  679. 03:06:52.369 -> 52 : 2271, 0
  680. 03:06:52.369 -> 53 : 2272, 0
  681. 03:06:52.369 -> 54 : 2271, 0
  682. 03:06:52.369 -> 55 : 2271, 0
  683. 03:06:52.369 -> 56 : 2272, 0
  684. 03:06:52.369 -> 57 : 2271, 0
  685. 03:06:52.369 -> 58 : 2272, 0
  686. 03:06:52.369 -> 59 : 2272, 0
  687. 03:06:52.369 -> 60 : 2271, 0
  688. 03:06:52.369 -> 61 : 2272, 0
  689. 03:06:52.369 -> 62 : 2271, 0
  690. 03:06:52.369 -> 63 : 2272, 0
  691. 03:06:52.369 -> 64 : 2271, 0
  692. 03:06:52.369 -> 65 : 2272, 0
  693. 03:06:52.369 -> 66 : 2272, 0
  694. 03:06:52.369 -> 67 : 2271, 0
  695. 03:06:52.369 -> 68 : 2271, 0
  696. 03:06:52.369 -> 69 : 2272, 0
  697. 03:06:52.369 -> 70 : 2271, 0
  698. 03:06:52.369 -> 71 : 2272, 0
  699. 03:06:52.369 -> 72 : 2271, 0
  700. 03:06:52.369 -> 73 : 2272, 0
  701. 03:06:52.369 -> 74 : 2276, 0
  702. 03:06:52.369 -> 75 : 2271, 0
  703. 03:06:52.369 -> 76 : 2271, 0
  704. 03:06:52.369 -> 77 : 2271, 0
  705. 03:06:52.369 -> 78 : 2276, 0
  706. 03:06:52.369 -> 79 : 2271, 0
  707. 03:06:52.369 -> 80 : 2272, 0
  708. 03:06:52.369 -> 81 : 2271, 0
  709. 03:06:52.369 -> 82 : 2271, 0
  710. 03:06:52.369 -> 83 : 2276, 0
  711. 03:06:52.369 -> 84 : 2271, 0
  712. 03:06:52.369 -> 85 : 2272, 41
  713. 03:06:52.369 -> 86 : 2271, 2122
  714. 03:06:52.369 -> 87 : 2271, 2271
  715. 03:06:52.369 -> 88 : 2267, 2267
  716. 03:06:52.369 -> 89 : 2271, 2271
  717. 03:06:52.369 -> 90 : 2271, 2271
  718. 03:06:52.369 -> 91 : 2272, 2272
  719. 03:06:52.369 -> 92 : 2271, 2271
  720. 03:06:52.369 -> 93 : 2272, 2272
  721. 03:06:52.369 -> 94 : 2271, 2271
  722. 03:06:52.369 -> 95 : 2271, 2271
  723. 03:06:52.369 -> 96 : 2272, 2272
  724. 03:06:52.369 -> 97 : 2272, 2272
  725. 03:06:52.369 -> 98 : 2271, 2271
  726. 03:06:52.369 -> 99 : 2271, 2271
  727. 03:06:52.369 -> 100 : 2276, 2276
  728. 03:06:52.369 -> 101 : 2272, 2272
  729. 03:06:52.435 -> 102 : 2272, 2272
  730. 03:06:52.435 -> 103 : 2272, 2272
  731. 03:06:52.435 -> 104 : 2271, 2271
  732. 03:06:52.435 -> 105 : 2271, 2271
  733. 03:06:52.435 -> 106 : 2271, 2271
  734. 03:06:52.435 -> 107 : 2271, 2271
  735. 03:06:52.435 -> 108 : 2276, 2276
  736. 03:06:52.435 -> 109 : 2276, 2276
  737. 03:06:52.435 -> 110 : 2272, 2272
  738. 03:06:52.435 -> 111 : 2272, 2272
  739. 03:06:52.435 -> 112 : 2271, 2271
  740. 03:06:52.435 -> 113 : 2271, 2271
  741. 03:06:52.435 -> 114 : 2271, 2271
  742. 03:06:52.435 -> 115 : 2271, 2271
  743. 03:06:52.435 -> 116 : 2266, 2266
  744. 03:06:52.435 -> 117 : 2276, 2276
  745. 03:06:52.435 -> 118 : 2272, 2272
  746. 03:06:52.435 -> 119 : 2271, 2271
  747. 03:06:52.435 -> 120 : 2271, 2271
  748. 03:06:52.435 -> 121 : 2271, 2271
  749. 03:06:52.435 -> 122 : 2271, 2271
  750. 03:06:52.435 -> 123 : 2271, 2271
  751. 03:06:52.435 -> 124 : 2271, 2271
  752. 03:06:52.435 -> 125 : 2271, 2271
  753. 03:06:52.435 -> 126 : 2271, 2256
  754. 03:06:52.435 -> 127 : 2272, 218
  755. 03:06:52.435 ->
  756. 03:06:52.435 -> MIOCK jitter meter ch=0
  757. 03:06:52.435 ->
  758. 03:06:52.435 -> 1T = (127-36) = 91 dly cells
  759. 03:06:52.435 -> Clock freq = 1560 MHz, period = 641 ps, 1 dly cell = 704/100 ps
  760. 03:06:52.435 ->
  761. 03:06:52.435 -> ----->DramcWriteLeveling(PI) begin...
  762. 03:06:52.435 -> ===============================================================================
  763. 03:06:52.435 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  764. 03:06:52.498 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  765. 03:06:52.498 -> ===============================================================================
  766. 03:06:52.498 -> Begin: 0, End: 63, Step: 1, Bound: 64
  767. 03:06:52.498 -> [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[Write Leveling]
  768. 03:06:52.498 -> delay byte0 byte1 byte2 byte3
  769. 03:06:52.498 ->
  770. 03:06:52.498 -> 0 O1( 1 1
  771. 03:06:52.498 -> 1 O1( 1 1
  772. 03:06:52.498 -> 2 O1( 1 1
  773. 03:06:52.498 -> 3 O1( 1 1
  774. 03:06:52.498 -> 4 O1( 1 1
  775. 03:06:52.498 -> 5 O1( 1 1
  776. 03:06:52.498 -> 6 O1( 1 1
  777. 03:06:52.498 -> 7 O1( 1 1
  778. 03:06:52.498 -> 8 O1( 1 1
  779. 03:06:52.498 -> 9 O1( 1 1
  780. 03:06:52.498 -> 10 O1( 1 0
  781. 03:06:52.498 -> 11 O1( 1 1
  782. 03:06:52.498 -> 12 O1( 1 0
  783. 03:06:52.498 -> 13 O1( 1 0
  784. 03:06:52.498 -> 14 O1( 1 0
  785. 03:06:52.498 -> 15 O1( 0 0
  786. 03:06:52.498 -> 16 O1( 0 0
  787. 03:06:52.566 -> 17 O1( 0 0
  788. 03:06:52.566 -> 18 O1( 0 0
  789. 03:06:52.566 -> 19 O1( 0 0
  790. 03:06:52.566 -> 20 O1( 0 0
  791. 03:06:52.566 -> 21 O1( 0 0
  792. 03:06:52.566 -> 22 O1( 0 0
  793. 03:06:52.566 -> 23 O1( 0 0
  794. 03:06:52.566 -> 24 O1( 0 0
  795. 03:06:52.566 -> 25 O1( 0 0
  796. 03:06:52.566 -> 26 O1( 0 0
  797. 03:06:52.566 -> 27 O1( 0 0
  798. 03:06:52.566 -> 28 O1( 0 0
  799. 03:06:52.566 -> 29 O1( 0 0
  800. 03:06:52.566 -> 30 O1( 0 0
  801. 03:06:52.566 -> 31 O1( 0 0
  802. 03:06:52.566 -> 32 O1( 0 0
  803. 03:06:52.566 -> 33 O1( 0 0
  804. 03:06:52.566 -> 34 O1( 0 0
  805. 03:06:52.566 -> 35 O1( 0 0
  806. 03:06:52.566 -> 36 O1( 0 0
  807. 03:06:52.566 -> 37 O1( 0 0
  808. 03:06:52.566 -> 38 O1( 0 0
  809. 03:06:52.566 -> 39 O1( 0 0
  810. 03:06:52.566 -> 40 O1( 0 0
  811. 03:06:52.566 -> 41 O1( 0 1
  812. 03:06:52.566 -> 42 O1( 0 1
  813. 03:06:52.566 -> 43 O1( 1 1
  814. 03:06:52.566 -> 44 O1( 1 1
  815. 03:06:52.629 -> 45 O1( 1 1
  816. 03:06:52.629 -> 46 O1( 1 1
  817. 03:06:52.629 -> 47 O1( 1 1
  818. 03:06:52.629 -> 48 O1( 1 1
  819. 03:06:52.629 -> 49 O1( 1 1
  820. 03:06:52.629 -> Early breakpass bytecount = 0xff (0xff: all bytes pass)
  821. 03:06:52.629 ->
  822. 03:06:52.629 -> [DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:2-OP:0xWrite leveling (Byte 0): 43 => 43
  823. 03:06:52.629 -> Write leveling (Byte 1): 41 => 41
  824. 03:06:52.629 -> DramcWriteLeveling(PI) end<-----
  825. 03:06:52.629 ->
  826. 03:06:52.629 -> ===============================================================================
  827. 03:06:52.629 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  828. 03:06:52.629 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  829. 03:06:52.629 -> ===============================================================================
  830. 03:06:52.629 -> [Gating] SW mode calibration
  831. 03:06:52.629 -> [get_gating_start_pos] calculated gating ui = 15
  832. 03:06:52.629 -> 12 0 | B1->B0 | 0 1212 | 0 0 | (0 0) (0 0)
  833. 03:06:52.629 -> 12 4 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  834. 03:06:52.677 -> 12 8 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  835. 03:06:52.677 -> 12 12 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  836. 03:06:52.677 -> 12 16 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 1)
  837. 03:06:52.677 -> 12 20 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  838. 03:06:52.677 -> 12 24 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  839. 03:06:52.677 -> 12 28 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  840. 03:06:52.677 -> 13 0 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  841. 03:06:52.677 -> 13 4 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  842. 03:06:52.677 -> 13 8 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  843. 03:06:52.677 -> 13 12 | B1->B0 | 1111 1616 | 1 1 | (0 0) (1 1)
  844. 03:06:52.677 -> 13 16 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  845. 03:06:52.677 -> 13 20 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  846. 03:06:52.744 -> 13 24 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  847. 03:06:52.744 -> 13 28 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  848. 03:06:52.744 -> 14 0 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  849. 03:06:52.744 -> 14 4 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  850. 03:06:52.744 -> 14 8 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  851. 03:06:52.744 -> 14 12 | B1->B0 | 1111 2323 | 1 1 | (0 1) (0 0)
  852. 03:06:52.744 -> 14 16 | B1->B0 | 1111 2323 | 1 1 | (1 1) (0 1)
  853. 03:06:52.744 -> 14 20 | B1->B0 | 1111 2323 | 1 1 | (1 1) (1 1)
  854. 03:06:52.744 -> 14 24 | B1->B0 | 1111 2323 | 1 1 | (1 1) (1 1)
  855. 03:06:52.744 -> 14 28 | B1->B0 | 1111 2323 | 1 1 | (1 1) (1 1)
  856. 03:06:52.744 -> 15 0 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  857. 03:06:52.744 -> 15 4 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  858. 03:06:52.744 -> 15 8 | B1->B0 | 1212 2222 | 0 0 | (1 1) (1 1)
  859. 03:06:52.744 -> 15 12 | B1->B0 | 2323 2222 | 0 0 | (0 0) (1 1)
  860. 03:06:52.744 -> 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  861. 03:06:52.744 -> 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  862. 03:06:52.806 -> 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  863. 03:06:52.806 -> 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  864. 03:06:52.806 -> 16 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  865. 03:06:52.806 -> 16 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  866. 03:06:52.806 -> 16 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  867. 03:06:52.806 -> 16 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
  868. 03:06:52.806 -> 16 16 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
  869. 03:06:52.806 -> 16 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  870. 03:06:52.806 -> 16 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  871. 03:06:52.806 -> 16 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  872. 03:06:52.806 -> 17 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  873. 03:06:52.806 -> 17 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  874. 03:06:52.806 -> 17 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  875. 03:06:52.806 -> 17 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  876. 03:06:52.870 -> 17 16 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  877. 03:06:52.870 -> 17 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  878. 03:06:52.870 -> 17 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  879. 03:06:52.870 -> 17 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  880. 03:06:52.870 -> 18 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  881. 03:06:52.870 -> 18 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  882. 03:06:52.870 -> 18 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  883. 03:06:52.870 -> 18 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
  884. 03:06:52.870 -> 18 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
  885. 03:06:52.870 -> 18 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  886. 03:06:52.870 -> 18 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  887. 03:06:52.870 -> 18 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  888. 03:06:52.870 -> 19 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  889. 03:06:52.870 -> 19 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  890. 03:06:52.870 -> 19 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  891. 03:06:52.870 -> 19 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  892. 03:06:52.870 -> 19 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  893. 03:06:52.941 -> best dqsien dly found for B1: (18, 12)
  894. 03:06:52.941 -> 19 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  895. 03:06:52.941 -> best dqsien dly found for B0: (18, 14)
  896. 03:06:52.941 -> best DQS0 dly(UI, PI) = (18, 14)
  897. 03:06:52.941 -> best DQS1 dly(UI, PI) = (18, 12)
  898. 03:06:52.941 ->
  899. 03:06:52.941 -> [Gating] SW calibration Done
  900. 03:06:52.941 -> [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  901. 03:06:52.941 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  902. 03:06:52.941 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  903. 03:06:52.941 -> ===============================================================================
  904. 03:06:52.941 -> Start DQ dly to find pass range UseTestEngine =0
  905. 03:06:52.941 -> UseTestEngine: 0
  906. 03:06:52.941 -> RX Vref Scan: 0
  907. 03:06:52.941 ->
  908. 03:06:52.941 -> RX Vref 0 -> 0, step: 1
  909. 03:06:52.941 ->
  910. 03:06:52.941 -> RX Delay -48 -> 63, step: 4
  911. 03:06:52.941 -> -48, [0] xxxxxxxx xxxxxxxx [MSB]
  912. 03:06:52.941 -> -44, [0] xxxxxxxx xxxxxxxx [MSB]
  913. 03:06:52.941 -> -40, [0] xxxxxxxx xxxxxxxx [MSB]
  914. 03:06:52.996 -> -36, [0] xxxxxxxx xxxxxxxx [MSB]
  915. 03:06:52.996 -> -32, [0] xxxxxxxx xxxxxxxx [MSB]
  916. 03:06:52.996 -> -28, [0] xxxxxxxx xxxxxxxx [MSB]
  917. 03:06:52.996 -> -24, [0] xxxxxxxx xxxxxxxx [MSB]
  918. 03:06:52.996 -> -20, [0] xxxxxxxx xxxxxxxx [MSB]
  919. 03:06:52.996 -> -16, [0] xxxxxxxx xxxxxxxx [MSB]
  920. 03:06:52.996 -> -12, [0] xxxxxxxx xxxxxxxx [MSB]
  921. 03:06:52.996 -> -8, [0] xxxxxxxx xxxxxxxx [MSB]
  922. 03:06:52.996 -> -4, [0] xxxxxxox xxxxxxxx [MSB]
  923. 03:06:52.996 -> 0, [0] xxoxoxox xxoxxxxx [MSB]
  924. 03:06:52.996 -> 4, [0] oxoooooo oxoxoooo [MSB]
  925. 03:06:52.996 -> 8, [0] oooooooo oooooooo [MSB]
  926. 03:06:52.996 -> 12, [0] oooooooo oooooooo [MSB]
  927. 03:06:52.996 -> 16, [0] oooooooo oooooooo [MSB]
  928. 03:06:52.996 -> 20, [0] oooooooo oooooooo [MSB]
  929. 03:06:52.996 -> 24, [0] oooooooo oooooooo [MSB]
  930. 03:06:52.996 -> 28, [0] oooooooo oooooooo [MSB]
  931. 03:06:52.996 -> 32, [0] oooooooo oooooooo [MSB]
  932. 03:06:52.996 -> 36, [0] ooooooxo oooooooo [MSB]
  933. 03:06:53.060 -> 40, [0] ooxoxoxo ooooooxo [MSB]
  934. 03:06:53.060 -> 44, [0] xxxxxxxx xxxxxxxx [MSB]
  935. 03:06:53.060 -> RX Vref B0= 0, Window Sum 316, worse bit 1, min window 36
  936. 03:06:53.060 -> iDelay=44, Bit 0, Center 23 (4 ~ 43) 40
  937. 03:06:53.060 -> iDelay=44, Bit 1, Center 25 (8 ~ 43) 36
  938. 03:06:53.060 -> iDelay=44, Bit 2, Center 19 (0 ~ 39) 40
  939. 03:06:53.060 -> iDelay=44, Bit 3, Center 23 (4 ~ 43) 40
  940. 03:06:53.060 -> iDelay=44, Bit 4, Center 19 (0 ~ 39) 40
  941. 03:06:53.060 -> iDelay=44, Bit 5, Center 23 (4 ~ 43) 40
  942. 03:06:53.060 -> iDelay=44, Bit 6, Center 15 (-4 ~ 35) 40
  943. 03:06:53.060 -> iDelay=44, Bit 7, Center 23 (4 ~ 43) 40
  944. 03:06:53.060 -> RX Vref B1= 0, Window Sum 312, worse bit 9, min window 36
  945. 03:06:53.060 -> iDelay=44, Bit 8, Center 23 (4 ~ 43) 40
  946. 03:06:53.060 -> iDelay=44, Bit 9, Center 25 (8 ~ 43) 36
  947. 03:06:53.060 -> iDelay=44, Bit 10, Center 21 (0 ~ 43) 44
  948. 03:06:53.060 -> iDelay=44, Bit 11, Center 25 (8 ~ 43) 36
  949. 03:06:53.060 -> iDelay=44, Bit 12, Center 23 (4 ~ 43) 40
  950. 03:06:53.060 -> iDelay=44, Bit 13, Center 23 (4 ~ 43) 40
  951. 03:06:53.123 -> iDelay=44, Bit 14, Center 21 (4 ~ 39) 36
  952. 03:06:53.123 -> iDelay=44, Bit 15, Center 23 (4 ~ 43) 40
  953. 03:06:53.123 -> [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  954. 03:06:53.123 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  955. 03:06:53.123 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  956. 03:06:53.123 -> ===============================================================================
  957. 03:06:53.123 -> DQS Delay:
  958. 03:06:53.123 -> DQS0 = 0, DQS1 = 0
  959. 03:06:53.123 -> DQM Delay:
  960. 03:06:53.123 -> DQM0 = 21, DQM1 = 23
  961. 03:06:53.123 -> DQ Delay:
  962. 03:06:53.123 -> DQ0 =23, DQ1 =25, DQ2 =19, DQ3 =23
  963. 03:06:53.123 -> DQ4 =19, DQ5 =23, DQ6 =15, DQ7 =23
  964. 03:06:53.123 -> DQ8 =23, DQ9 =25, DQ10 =21, DQ11 =25
  965. 03:06:53.123 -> DQ12 =23, DQ13 =23, DQ14 =21, DQ15 =23
  966. 03:06:53.123 ->
  967. 03:06:53.123 ->
  968. 03:06:53.123 -> ===============================================================================
  969. 03:06:53.123 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  970. 03:06:53.170 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  971. 03:06:53.170 -> ===============================================================================
  972. 03:06:53.170 -> [TxWindowPerbitCal] caltype:2 Autok:0
  973. 03:06:53.170 ->
  974. 03:06:53.170 ->
  975. 03:06:53.170 -> TX Vref Scan disable
  976. 03:06:53.170 -> 809 |3 0 41|[0] xxxxxxxx xxxxxxxx [MSB]
  977. 03:06:53.170 -> 811 |3 0 43|[0] xxoxxxox xxxxoxxx [MSB]
  978. 03:06:53.170 -> 813 |3 0 45|[0] xxoxxxox xxxxoxxo [MSB]
  979. 03:06:53.170 -> 815 |3 0 47|[0] xxoxxxox oxooooxo [MSB]
  980. 03:06:53.170 -> 817 |3 0 49|[0] oxoxoxoo oooooooo [MSB]
  981. 03:06:53.170 -> 829 |3 0 61|[0] oooooooo ooxoooxo [MSB]
  982. 03:06:53.170 -> 831 |3 0 63|[0] ooooooxo ooxoooxo [MSB]
  983. 03:06:53.170 -> 833 |3 2 1|[0] ooooooxo xoxxxoxo [MSB]
  984. 03:06:53.170 -> 835 |3 2 3|[0] xoxxxoxo xoxxxxxx [MSB]
  985. 03:06:53.241 -> 837 |3 2 5|[0] xxxxxoxo xxxxxxxx [MSB]
  986. 03:06:53.241 -> 839 |3 2 7|[0] xxxxxxxx xxxxxxxx [MSB]
  987. 03:06:53.241 -> TX Bit0 (817~833) 18 825, Bit8 (815~831) 18 823,
  988. 03:06:53.241 -> TX Bit1 (819~835) 18 827, Bit9 (817~835) 20 826,
  989. 03:06:53.241 -> TX Bit2 (811~833) 24 822, Bit10 (815~827) 14 821,
  990. 03:06:53.241 -> TX Bit3 (819~833) 16 826, Bit11 (815~831) 18 823,
  991. 03:06:53.241 -> TX Bit4 (817~833) 18 825, Bit12 (811~831) 22 821,
  992. 03:06:53.241 -> TX Bit5 (819~837) 20 828, Bit13 (815~833) 20 824,
  993. 03:06:53.241 -> TX Bit6 (811~829) 20 820, Bit14 (817~827) 12 822,
  994. 03:06:53.241 -> TX Bit7 (817~837) 22 827, Bit15 (813~833) 22 823,
  995. 03:06:53.241 ->
  996. 03:06:53.241 -> == TX Byte 0 ==
  997. 03:06:53.241 -> Update DQ dly =824 (3 ,0, 56) DQ OEN =(2 ,5)
  998. 03:06:53.241 -> Update DQM dly =824 (3 ,0, 56) DQM OEN =(2 ,5)
  999. 03:06:53.241 ->
  1000. 03:06:53.241 -> == TX Byte 1 ==
  1001. 03:06:53.241 -> Update DQ dly =823 (3 ,0, 55) DQ OEN =(2 ,5)
  1002. 03:06:53.241 -> Update DQM dly =823 (3 ,0, 55) DQM OEN =(2 ,5)
  1003. 03:06:53.241 ->
  1004. 03:06:53.241 -> ===============================================================================
  1005. 03:06:53.295 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1006. 03:06:53.295 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1007. 03:06:53.295 -> ===============================================================================
  1008. 03:06:53.295 -> [TxWindowPerbitCal] caltype:0 Autok:0
  1009. 03:06:53.295 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 3
  1010. 03:06:53.295 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 5
  1011. 03:06:53.295 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 7
  1012. 03:06:53.356 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 9
  1013. 03:06:53.356 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 11
  1014. 03:06:53.356 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 13
  1015. 03:06:53.356 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 15
  1016. 03:06:53.414 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 17
  1017. 03:06:53.414 -> TX Vref=3, minBit 14, minWin=13, winSum=270
  1018. 03:06:53.414 -> TX Vref=5, minBit 14, minWin=13, winSum=278
  1019. 03:06:53.414 -> TX Vref=7, minBit 14, minWin=14, winSum=288
  1020. 03:06:53.414 -> TX Vref=9, minBit 14, minWin=14, winSum=294
  1021. 03:06:53.414 -> TX Vref=11, minBit 14, minWin=16, winSum=307
  1022. 03:06:53.414 -> TX Vref=13, minBit 14, minWin=16, winSum=316
  1023. 03:06:53.414 -> TX Vref=15, minBit 10, minWin=16, winSum=321
  1024. 03:06:53.414 -> TX Vref=17, minBit 3, minWin=18, winSum=334
  1025. 03:06:53.414 -> [TxChooseVref] Worse bit 3, Min win 18, Win sum 334, Final Vref 17
  1026. 03:06:53.414 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 17
  1027. 03:06:53.468 ->
  1028. 03:06:53.468 -> Final TX Range 1 Vref 17
  1029. 03:06:53.468 ->
  1030. 03:06:53.468 -> ===============================================================================
  1031. 03:06:53.468 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1032. 03:06:53.468 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1033. 03:06:53.468 -> ===============================================================================
  1034. 03:06:53.468 -> [TxWindowPerbitCal] caltype:0 Autok:0
  1035. 03:06:53.468 ->
  1036. 03:06:53.468 ->
  1037. 03:06:53.468 -> TX Vref Scan disable
  1038. 03:06:53.468 -> 809 |3 0 41|[0] xxxxxxxx xxxxxxxx [MSB]
  1039. 03:06:53.468 -> 810 |3 0 42|[0] xxxxxxxx xxxxoxxx [MSB]
  1040. 03:06:53.468 -> 811 |3 0 43|[0] xxxxxxxx xxxxoxxo [MSB]
  1041. 03:06:53.468 -> 812 |3 0 44|[0] xxoxxxox xxoxoxxo [MSB]
  1042. 03:06:53.468 -> 813 |3 0 45|[0] xxoxxxox oxoooxxo [MSB]
  1043. 03:06:53.468 -> 814 |3 0 46|[0] xxoxxxox oxooooxo [MSB]
  1044. 03:06:53.538 -> 815 |3 0 47|[0] oxoxxxox oooooooo [MSB]
  1045. 03:06:53.538 -> 816 |3 0 48|[0] oxoxoxoo oooooooo [MSB]
  1046. 03:06:53.538 -> 817 |3 0 49|[0] oxoxoooo oooooooo [MSB]
  1047. 03:06:53.538 -> 832 |3 2 0|[0] oooooooo ooxooooo [MSB]
  1048. 03:06:53.538 -> 833 |3 2 1|[0] oooooooo ooxoooxo [MSB]
  1049. 03:06:53.538 -> 834 |3 2 2|[0] ooxoxoxo xoxxxoxo [MSB]
  1050. 03:06:53.538 -> 835 |3 2 3|[0] xoxoxoxo xoxxxxxx [MSB]
  1051. 03:06:53.538 -> 836 |3 2 4|[0] xoxxxoxo xxxxxxxx [MSB]
  1052. 03:06:53.538 -> 837 |3 2 5|[0] xoxxxoxo xxxxxxxx [MSB]
  1053. 03:06:53.538 -> 838 |3 2 6|[0] xxxxxxxx xxxxxxxx [MSB]
  1054. 03:06:53.538 -> TX Bit0 (815~834) 20 824, Bit8 (813~833) 21 823,
  1055. 03:06:53.538 -> TX Bit1 (818~837) 20 827, Bit9 (815~835) 21 825,
  1056. 03:06:53.538 -> TX Bit2 (812~833) 22 822, Bit10 (812~831) 20 821,
  1057. 03:06:53.538 -> TX Bit3 (818~835) 18 826, Bit11 (813~833) 21 823,
  1058. 03:06:53.538 -> TX Bit4 (816~833) 18 824, Bit12 (810~833) 24 821,
  1059. 03:06:53.538 -> TX Bit5 (817~837) 21 827, Bit13 (814~834) 21 824,
  1060. 03:06:53.538 -> TX Bit6 (812~833) 22 822, Bit14 (815~832) 18 823,
  1061. 03:06:53.538 -> TX Bit7 (816~837) 22 826, Bit15 (811~834) 24 822,
  1062. 03:06:53.538 ->
  1063. 03:06:53.593 -> [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =704/100 ps
  1064. 03:06:53.593 -> == TX Byte 0 ==
  1065. 03:06:53.593 -> u2DelayCellOfst[0]=2 cells (2 PI)
  1066. 03:06:53.593 -> u2DelayCellOfst[1]=6 cells (5 PI)
  1067. 03:06:53.593 -> u2DelayCellOfst[2]=0 cells (0 PI)
  1068. 03:06:53.593 -> u2DelayCellOfst[3]=5 cells (4 PI)
  1069. 03:06:53.593 -> u2DelayCellOfst[4]=2 cells (2 PI)
  1070. 03:06:53.593 -> u2DelayCellOfst[5]=6 cells (5 PI)
  1071. 03:06:53.593 -> u2DelayCellOfst[6]=0 cells (0 PI)
  1072. 03:06:53.593 -> u2DelayCellOfst[7]=5 cells (4 PI)
  1073. 03:06:53.593 -> Update DQ dly =822 (3 ,0, 54) DQ OEN =(2 ,5)
  1074. 03:06:53.593 -> Update DQM dly =824 (3 ,0, 56) DQM OEN =(2 ,5)
  1075. 03:06:53.593 ->
  1076. 03:06:53.593 -> == TX Byte 1 ==
  1077. 03:06:53.593 -> u2DelayCellOfst[8]=2 cells (2 PI)
  1078. 03:06:53.593 -> u2DelayCellOfst[9]=5 cells (4 PI)
  1079. 03:06:53.593 -> u2DelayCellOfst[10]=0 cells (0 PI)
  1080. 03:06:53.656 -> u2DelayCellOfst[11]=2 cells (2 PI)
  1081. 03:06:53.656 -> u2DelayCellOfst[12]=0 cells (0 PI)
  1082. 03:06:53.656 -> u2DelayCellOfst[13]=4 cells (3 PI)
  1083. 03:06:53.656 -> u2DelayCellOfst[14]=2 cells (2 PI)
  1084. 03:06:53.656 -> u2DelayCellOfst[15]=1 cells (1 PI)
  1085. 03:06:53.656 -> Update DQ dly =821 (3 ,0, 53) DQ OEN =(2 ,5)
  1086. 03:06:53.656 -> Update DQM dly =823 (3 ,0, 55) DQM OEN =(2 ,5)
  1087. 03:06:53.656 ->
  1088. 03:06:53.656 -> ===============================================================================
  1089. 03:06:53.656 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1090. 03:06:53.656 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1091. 03:06:53.656 -> ===============================================================================
  1092. 03:06:53.656 -> DATLAT Default: 0xc
  1093. 03:06:53.656 -> 0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0xbest_step = 11
  1094. 03:06:53.656 ->
  1095. 03:06:53.656 -> ===============================================================================
  1096. 03:06:53.656 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1097. 03:06:53.656 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1098. 03:06:53.711 -> ===============================================================================
  1099. 03:06:53.711 -> Start DQ dly to find pass range UseTestEngine =1
  1100. 03:06:53.711 -> UseTestEngine: 1
  1101. 03:06:53.711 -> RX Vref Scan: 1
  1102. 03:06:53.711 ->
  1103. 03:06:53.711 -> Set Vref Range= 9 -> 21
  1104. 03:06:53.711 ->
  1105. 03:06:53.711 -> RX Vref 9 -> 21, step: 1
  1106. 03:06:53.711 ->
  1107. 03:06:53.711 -> RX Delay -14 -> 63, step: 2
  1108. 03:06:53.711 ->
  1109. 03:06:53.711 -> Set Vref, RX VrefLevel [Byte0]: 9 [Byte1]: 9
  1110. 03:06:53.711 -> RX Vref B0= 9, Window Sum 230, worse bit 2, min window 26
  1111. 03:06:53.711 -> RX Vref B1= 9, Window Sum 216, worse bit 10, min window 22
  1112. 03:06:53.711 ->
  1113. 03:06:53.711 -> Set Vref, RX VrefLevel [Byte0]: 10 [Byte1]: 10
  1114. 03:06:53.711 -> RX Vref B0= 10, Window Sum 240, worse bit 2, min window 26
  1115. 03:06:53.711 -> RX Vref B1= 10, Window Sum 220, worse bit 10, min window 24
  1116. 03:06:53.766 ->
  1117. 03:06:53.766 -> Set Vref, RX VrefLevel [Byte0]: 11 [Byte1]: 11
  1118. 03:06:53.766 -> RX Vref B0= 11, Window Sum 246, worse bit 2, min window 28
  1119. 03:06:53.766 -> RX Vref B1= 11, Window Sum 232, worse bit 10, min window 26
  1120. 03:06:53.766 ->
  1121. 03:06:53.766 -> Set Vref, RX VrefLevel [Byte0]: 12 [Byte1]: 12
  1122. 03:06:53.766 -> RX Vref B0= 12, Window Sum 254, worse bit 4, min window 28
  1123. 03:06:53.766 -> RX Vref B1= 12, Window Sum 242, worse bit 10, min window 26
  1124. 03:06:53.766 ->
  1125. 03:06:53.766 -> Set Vref, RX VrefLevel [Byte0]: 13 [Byte1]: 13
  1126. 03:06:53.766 -> RX Vref B0= 13, Window Sum 268, worse bit 2, min window 32
  1127. 03:06:53.766 -> RX Vref B1= 13, Window Sum 252, worse bit 10, min window 28
  1128. 03:06:53.766 ->
  1129. 03:06:53.766 -> Set Vref, RX VrefLevel [Byte0]: 14 [Byte1]: 14
  1130. 03:06:53.837 -> RX Vref B0= 14, Window Sum 272, worse bit 2, min window 32
  1131. 03:06:53.837 -> RX Vref B1= 14, Window Sum 262, worse bit 10, min window 28
  1132. 03:06:53.837 ->
  1133. 03:06:53.837 -> Set Vref, RX VrefLevel [Byte0]: 15 [Byte1]: 15
  1134. 03:06:53.837 -> RX Vref B0= 15, Window Sum 276, worse bit 2, min window 32
  1135. 03:06:53.837 -> RX Vref B1= 15, Window Sum 266, worse bit 10, min window 30
  1136. 03:06:53.837 ->
  1137. 03:06:53.837 -> Set Vref, RX VrefLevel [Byte0]: 16 [Byte1]: 16
  1138. 03:06:53.837 -> RX Vref B0= 16, Window Sum 286, worse bit 2, min window 34
  1139. 03:06:53.837 -> RX Vref B1= 16, Window Sum 268, worse bit 10, min window 30
  1140. 03:06:53.837 ->
  1141. 03:06:53.837 -> Set Vref, RX VrefLevel [Byte0]: 17 [Byte1]: 17
  1142. 03:06:53.837 -> RX Vref B1= 17, Window Sum 280, worse bit 10, min window 32
  1143. 03:06:53.837 ->
  1144. 03:06:53.837 -> Set Vref, RX VrefLevel [Byte0]: 18 [Byte1]: 18
  1145. 03:06:53.900 -> RX Vref B1= 18, Window Sum 280, worse bit 8, min window 34
  1146. 03:06:53.900 ->
  1147. 03:06:53.900 -> Set Vref, RX VrefLevel [Byte0]: 19 [Byte1]: 19
  1148. 03:06:53.900 ->
  1149. 03:06:53.900 -> Set Vref, RX VrefLevel [Byte0]: 20 [Byte1]: 20
  1150. 03:06:53.900 ->
  1151. 03:06:53.900 -> Set Vref, RX VrefLevel [Byte0]: 21 [Byte1]: 21
  1152. 03:06:53.900 ->
  1153. 03:06:53.900 -> Final RX Vref Byte 0 = 16 to rank0 to rank1
  1154. 03:06:53.900 ->
  1155. 03:06:53.900 -> Final RX Vref Byte 1 = 18 to rank0 to rank1
  1156. 03:06:53.900 -> ===============================================================================
  1157. 03:06:53.900 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1158. 03:06:53.900 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1159. 03:06:53.900 -> ===============================================================================
  1160. 03:06:53.900 -> DQS Delay:
  1161. 03:06:53.900 -> DQS0 = 0, DQS1 = 0
  1162. 03:06:53.900 -> DQM Delay:
  1163. 03:06:53.900 -> DQM0 = 21, DQM1 = 24
  1164. 03:06:53.900 -> DQ Delay:
  1165. 03:06:53.900 -> DQ0 =23, DQ1 =25, DQ2 =18, DQ3 =24
  1166. 03:06:53.984 -> DQ4 =20, DQ5 =23, DQ6 =15, DQ7 =23
  1167. 03:06:53.984 -> DQ8 =24, DQ9 =26, DQ10 =22, DQ11 =26
  1168. 03:06:53.984 -> DQ12 =23, DQ13 =25, DQ14 =22, DQ15 =24
  1169. 03:06:53.984 ->
  1170. 03:06:53.984 ->
  1171. 03:06:53.984 -> [DualRankRxdatlatCal] RK0: 11, RK1: 0, Final_Datlat 11
  1172. 03:06:53.984 ->
  1173. 03:06:53.984 ->
  1174. 03:06:53.984 -> [Calibration Summary] Freqency 1600
  1175. 03:06:53.984 -> CH 0, Rank 0
  1176. 03:06:53.984 -> SW Impedance : PASS
  1177. 03:06:53.984 -> DUTY Scan : NO K
  1178. 03:06:53.984 -> ZQ Calibration : PASS
  1179. 03:06:53.984 -> Jitter Meter : NO K
  1180. 03:06:53.984 -> CBT Training : NO K
  1181. 03:06:53.984 -> Write leveling : PASS
  1182. 03:06:53.984 -> RX DQS gating : PASS
  1183. 03:06:53.984 -> RX DQ/DQS(RDDQC) : PASS
  1184. 03:06:53.984 -> TX DQ/DQS : PASS
  1185. 03:06:53.984 -> RX DATLAT : PASS
  1186. 03:06:53.984 -> RX DQ/DQS(Engine): PASS
  1187. 03:06:53.984 -> TX OE : NO K
  1188. 03:06:53.984 -> All Pass.
  1189. 03:06:53.984 ->
  1190. 03:06:53.984 -> TX_TRACKING: OFF
  1191. 03:06:53.984 -> [AUTO] write start address pass, BASE_ADDR : 0x0, OFFSET : 0x3
  1192. 03:06:53.984 -> [AUTO] Detect DramSize: 0x8000000
  1193. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x8000000, OFFSET : 0x3
  1194. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1195. 03:06:53.984 ->
  1196. 03:06:53.984 ->
  1197. 03:06:53.984 -> [AUTO] Detect DramSize: 0x10000000
  1198. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x10000000, OFFSET : 0x3
  1199. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1200. 03:06:53.984 ->
  1201. 03:06:53.984 ->
  1202. 03:06:53.984 -> [AUTO] Detect DramSize: 0x20000000
  1203. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x20000000, OFFSET : 0x3
  1204. 03:06:53.984 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1205. 03:06:54.058 -> [AUTO] TA2 read check fail, u4err_value = 65535, 3
  1206. 03:06:54.058 -> [AUTO] Detect full size
  1207. 03:06:54.058 ->
  1208. 03:06:54.058 ->
  1209. 03:06:54.058 -> u4DramSize 0x20000000
  1210. 03:06:54.058 -> NOTICE: EMI: Detected DRAM size: 512MB
  1211. 03:06:54.058 ->
  1212. 03:06:54.058 -> [MEM_TEST] 02: After DFS, before run time config
  1213. 03:06:54.058 -> [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  1214. 03:06:54.058 ->
  1215. 03:06:54.058 -> [TA2_TEST]
  1216. 03:06:54.058 -> === TA2 HW
  1217. 03:06:54.058 -> === OFFSET:0x200
  1218. 03:06:54.058 -> TA2 PAT: 3
  1219. 03:06:54.058 ->
  1220. 03:06:54.058 -> TA2 Trigger Write
  1221. 03:06:54.058 -> HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
  1222. 03:06:54.058 -> [DramcRunTimeConfig]: ON
  1223. 03:06:54.058 -> PHYPLL
  1224. 03:06:54.058 -> DPM_CONTROL_AFTERK: ON
  1225. 03:06:54.058 -> PER_BANK_REFRESH: OFF
  1226. 03:06:54.058 -> REFRESH_OVERHEAD_REDUCTION: ON
  1227. 03:06:54.058 -> CMD_PICG_NEW_MODE: OFF
  1228. 03:06:54.058 -> TX_TRACKING: OFF
  1229. 03:06:54.058 -> RDSEL_TRACKING: OFF
  1230. 03:06:54.058 -> DQS Precalculation for DVFS: OFF
  1231. 03:06:54.058 -> RX_TRACKING: OFF
  1232. 03:06:54.058 -> DDR_HW_GATING DBG: ON
  1233. 03:06:54.058 -> DDR_ZQCS_ENABLE: ON
  1234. 03:06:54.058 -> RX_PICG_NEW_MODE: ON
  1235. 03:06:54.058 -> TX_PICG_NEW_MODE: ON
  1236. 03:06:54.058 -> ENABLE_RX_DCM_DPHY: ON
  1237. 03:06:54.058 -> LOWPOWER_GOLDEN_SETTINGS(DCM): ON
  1238. 03:06:54.129 -> DUMMY_READ_FOR_TRACKING: OFF
  1239. 03:06:54.129 -> !!! SPM_CONTROL_AFTERK: OFF
  1240. 03:06:54.129 -> !!! SPM could not control APHY
  1241. 03:06:54.129 -> IMPEDANCE_TRACKING: OFF
  1242. 03:06:54.129 -> HW_SAVE_FOR_SR: OFF
  1243. 03:06:54.129 -> CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
  1244. 03:06:54.129 -> PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
  1245. 03:06:54.129 -> Read ODT Tracking: OFF
  1246. 03:06:54.129 -> Refresh Rate DeBounce: OFF
  1247. 03:06:54.129 -> DFS_NO_QUEUE_FLUSH: OFF
  1248. 03:06:54.129 -> DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
  1249. 03:06:54.129 -> ENABLE_DFS_RUNTIME_MRW: OFF
  1250. 03:06:54.129 -> DDR_RESERVE_NEW_MODE: ON
  1251. 03:06:54.129 -> =========================
  1252. 03:06:54.129 ->
  1253. 03:06:54.129 -> [MEM_TEST] 03: After run time config
  1254. 03:06:54.129 -> [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  1255. 03:06:54.129 ->
  1256. 03:06:54.129 -> [TA2_TEST]
  1257. 03:06:54.129 -> === TA2 HW
  1258. 03:06:54.129 -> === OFFSET:0x200
  1259. 03:06:54.129 ->
  1260. 03:06:54.129 -> TA2 Trigger Write
  1261. 03:06:54.129 -> HW channel(0) Rank(0), TA2 pass, pass_cnt:2, err_cnt:0
  1262. 03:06:54.129 ->
  1263. 03:06:54.129 -> Init_DRAM:2480: init PCDDR4 dram End
  1264. 03:06:54.129 -> EMI: complex real chip dram calibration
  1265. 03:06:54.194 -> Verify pattern 1 (0x00~0xff)...
  1266. 03:06:54.194 -> EMI: mem8_base[0] = pattern8 = 0x0
  1267. 03:06:54.194 -> Verify pattern 2 (0x00~0xffff)...
  1268. 03:06:54.194 -> EMI: mem16_base[0] = pattern16 = 0x0
  1269. 03:06:54.194 -> Verify pattern 3 (0x00~0xffffffff)...
  1270. 03:06:54.194 -> EMI: mem32_base[0] = pattern32 = 0x0
  1271. 03:06:54.194 -> NOTICE: EMI: complex R/W mem test passed
  1272. 03:06:54.194 ->
  1273. 03:06:54.194 -> drm_dram_reserved: MTK_DRM_MODE(22000000)
  1274. 03:06:54.194 ->
  1275. 03:06:54.194 -> NOTICE: SPI_NAND parses attributes from parameter page.
  1276. 03:06:54.194 -> NOTICE: SPI_NAND Detected ID 0x0
  1277. 03:06:54.194 -> NOTICE: Page size 2048, Block size 131072, size 134217728
  1278. 03:06:54.194 -> NOTICE: Initializing NMBM ...
  1279. 03:06:54.194 -> NOTICE: Signature found at block 1023 [0x07fe0000]
  1280. 03:06:54.194 -> NOTICE: First info table with writecount 0 found in block 960
  1281. 03:06:54.262 -> NOTICE: Second info table with writecount 0 found in block 963
  1282. 03:06:54.262 -> NOTICE: NMBM has been successfully attached in read-only mode
  1283. 03:06:54.262 -> INFO: BL2: Loading image id 3
  1284. 03:06:54.262 -> INFO: Loading image id=3 at address 0x42000000
  1285. 03:06:54.262 -> INFO: Image id=3 loaded: 0x42000000 - 0x42009061
  1286. 03:06:54.262 -> INFO: BL2: Loading image id 5
  1287. 03:06:54.262 -> INFO: Loading image id=5 at address 0x42000000
  1288. 03:06:54.592 -> INFO: Image id=5 loaded: 0x42000000 - 0x420ae288
  1289. 03:06:54.774 -> NOTICE: BL2: Booting BL31
  1290. 03:06:54.774 -> INFO: Entry point address = 0x43001000
  1291. 03:06:54.774 -> INFO: SPSR = 0x3cd
  1292. 03:06:54.774 -> INFO: Total CPU count: 4
  1293. 03:06:54.774 -> INFO: MCUSYS: Disable 512KB L2C shared SRAM
  1294. 03:06:54.774 -> INFO: check_ver = 0
  1295. 03:06:54.812 -> INFO: Secondary bootloader is AArch64
  1296. 03:06:54.812 -> INFO: GICv3 without legacy support detected.
  1297. 03:06:54.812 -> INFO: ARM GICv3 driver initialized in EL3
  1298. 03:06:54.812 -> INFO: Maximum SPI INTID supported: 671
  1299. 03:06:54.812 -> INFO: SPMC: Changed to SPMC mode
  1300. 03:06:54.812 -> NOTICE: BL31: v2.6(release):82a3fbe10a-dirty
  1301. 03:06:54.812 -> NOTICE: BL31: Built : 16:56:29, Mar 29 2022
  1302. 03:06:54.812 -> INFO: [MPU](Region0)sa:0x0300, ea:0x0302
  1303. 03:06:54.853 -> INFO: [MPU](Region0)apc0:0x80b6db69, apc1:0x00b6db6d
  1304. 03:06:54.853 -> INFO: [MPU](Region1)sa:0x0000, ea:0x0000
  1305. 03:06:54.853 -> INFO: [MPU](Region1)apc0:0x00000000, apc1:0x00000000
  1306. 03:06:54.853 -> INFO: [MPU](Region2)sa:0x0000, ea:0x0000
  1307. 03:06:54.853 -> INFO: [MPU](Region2)apc0:0x00000000, apc1:0x00000000
  1308. 03:06:54.853 -> INFO: [MPU](Region3)sa:0x0000, ea:0x0000
  1309. 03:06:54.853 -> INFO: [MPU](Region3)apc0:0x00000000, apc1:0x00000000
  1310. 03:06:54.853 -> INFO: [DEVAPC] devapc_init done
  1311. 03:06:54.853 -> INFO: BL31: Initializing runtime services
  1312. 03:06:54.853 -> INFO: BL31: Preparing for EL3 exit to normal world
  1313. 03:06:54.918 -> INFO: Entry point address = 0x41e00000
  1314. 03:06:54.918 -> INFO: SPSR = 0x3c9
  1315. 03:06:54.983 -> In: serial@11002000
  1316. 03:06:54.983 -> Out: serial@11002000
  1317. 03:06:54.983 -> Err: serial@11002000
  1318. 03:06:54.983 -> Net: eth0: ethernet@15100000
  1319. 03:06:56.000 -> [?25l *** U-Boot Boot Menu *** Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit 1. Startup system (Default) 2. Startup firmware0 3. Startup firmware1 4. Upgrade firmware 5. Upgrade ATF BL2 6. Upgrade ATF FIP 7. Upgrade single image 8. Load image 0. U-Boot console Hit any key to stop autoboot: 5  4  3  2  1  0 [?25hdetect button reset released!
  1320. 03:07:01.038 -> Reading from 0x0 to 0x5f7fdd8c, size 0x4 ... OK
  1321. 03:07:01.038 -> Boot failure detected on both systems
  1322. 03:07:01.038 -> Reading from 0x0 to 0x5f7fdd8c, size 0x4 ... OK
  1323. 03:07:01.038 -> Saving Environment to MTD... Erasing on MTD device 'nmbm0'... OK
  1324. 03:07:01.074 -> Writing to MTD device 'nmbm0'... OK
  1325. 03:07:01.074 -> OK
  1326. 03:07:01.074 -> Booting System 0
  1327. 03:07:01.074 -> ubi0: attaching mtd9
  1328. 03:07:01.184 -> ubi0: scanning is finished
  1329. 03:07:01.184 -> ubi0: attached mtd9 (name "ubi", size 30 MiB)
  1330. 03:07:01.184 -> ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
  1331. 03:07:01.221 -> ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
  1332. 03:07:01.221 -> ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
  1333. 03:07:01.221 -> ubi0: good PEBs: 240, bad PEBs: 0, corrupted PEBs: 0
  1334. 03:07:01.221 -> ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
  1335. 03:07:01.221 -> ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 1233335465
  1336. 03:07:01.221 -> ubi0: available PEBs: 185, total reserved PEBs: 55, PEBs reserved for bad PEB handling: 19
  1337. 03:07:01.264 -> Reading from volume 'kernel' to 0x46000000, size 0x0 ... OK
  1338. 03:07:01.651 -> ## Loading kernel from FIT Image at 46000000 ...
  1339. 03:07:01.651 -> Using 'config-1' configuration
  1340. 03:07:01.651 -> Trying 'kernel-1' kernel subimage
  1341. 03:07:01.651 -> Description: ARM64 OpenWrt Linux-5.15.98
  1342. 03:07:01.651 -> Type: Kernel Image
  1343. 03:07:01.651 -> Compression: lzma compressed
  1344. 03:07:01.651 -> Data Start: 0x460000e8
  1345. 03:07:01.651 -> Data Size: 3945112 Bytes = 3.8 MiB
  1346. 03:07:01.651 -> Architecture: AArch64
  1347. 03:07:01.651 -> OS: Linux
  1348. 03:07:01.651 -> Load Address: 0x48000000
  1349. 03:07:01.651 -> Entry Point: 0x48000000
  1350. 03:07:01.651 -> Hash algo: crc32
  1351. 03:07:01.689 -> Hash value: 22a5ee1e
  1352. 03:07:01.689 -> Hash algo: sha1
  1353. 03:07:01.689 -> Hash value: c311e964f1140662f74c9eb85f483807f50815da
  1354. 03:07:01.689 -> Verifying Hash Integrity ... crc32+ sha1+ OK
  1355. 03:07:01.728 -> ## Loading fdt from FIT Image at 46000000 ...
  1356. 03:07:01.728 -> Using 'config-1' configuration
  1357. 03:07:01.728 -> Trying 'fdt-1' fdt subimage
  1358. 03:07:01.728 -> Description: ARM64 OpenWrt xiaomi_redmi-router-ax6000-stock device tree blob
  1359. 03:07:01.728 -> Type: Flat Device Tree
  1360. 03:07:01.728 -> Compression: uncompressed
  1361. 03:07:01.775 -> Data Start: 0x463c34d0
  1362. 03:07:01.775 -> Data Size: 32768 Bytes = 32 KiB
  1363. 03:07:01.775 -> Architecture: AArch64
  1364. 03:07:01.775 -> Hash algo: crc32
  1365. 03:07:01.775 -> Hash value: b1b77c32
  1366. 03:07:01.775 -> Hash algo: sha1
  1367. 03:07:01.775 -> Hash value: ab3e4e1eb6d5675b7477266c63401e48abc57c62
  1368. 03:07:01.775 -> Verifying Hash Integrity ... crc32+ sha1+ OK
  1369. 03:07:01.775 -> Booting using the fdt blob at 0x463c34d0
  1370. 03:07:01.775 -> Uncompressing Kernel Image
  1371. 03:07:02.299 -> ERROR: Failed to allocate 0xb000 bytes below 0x6c000000.
  1372. 03:07:02.299 -> Failed using fdt_high value for Device TreeFDT creation failed!
  1373. 03:07:02.406 -> resetting ...
  1374. 03:07:03.235 ->
  1375. 03:07:03.235 ->
  1376. F0: 102B 0000
  1377. 03:07:03.235 ->
  1378. FA: 1040 0000
  1379. 03:07:03.235 ->
  1380. FA: 1040 0000 [0200]
  1381. 03:07:03.235 ->
  1382. F9: 0000 0000
  1383. 03:07:03.235 ->
  1384. V0: 0000 0000 [0001]
  1385. 03:07:03.235 ->
  1386. 00: 0000 0000
  1387. 03:07:03.235 ->
  1388. BP: 2400 0041 [0000]
  1389. 03:07:03.235 ->
  1390. G0: 1190 0000
  1391. 03:07:03.235 ->
  1392. EC: 0000 0000 [1000]
  1393. 03:07:03.235 ->
  1394. T0: 0000 022F [010F]
  1395. 03:07:03.235 ->
  1396. Jump to BL
  1397. 03:07:03.235 ->
  1398. 03:07:03.235 ->
  1399. NOTICE: BL2: v2.6(release):82a3fbe10a-dirty
  1400. 03:07:03.235 -> NOTICE: BL2: Built : 16:56:29, Mar 29 2022
  1401. 03:07:03.271 -> INFO: BL2: Doing platform setup
  1402. 03:07:03.271 -> NOTICE: WDT: disabled
  1403. 03:07:03.411 -> NOTICE: CPU: MT7986 (2000MHz)
  1404. 03:07:03.411 -> NOTICE: EMI: Using DDR4 settings
  1405. 03:07:03.411 -> before ctrl3 = 0x218000
  1406. 03:07:03.411 -> clear request & ack
  1407. 03:07:03.411 -> after ctrl3 = 0x208000
  1408. 03:07:03.411 -> DVFSRC_SUCCESS 0
  1409. 03:07:03.411 -> dump drm registers data:
  1410. 03:07:03.411 -> 1001d000 | 00000000 00000000 00000000 00000000
  1411. 03:07:03.444 -> 1001d010 | 00000000 00000000 00000000 00000000
  1412. 03:07:03.444 -> 1001d020 | 00000000 00000000 00000000 00000000
  1413. 03:07:03.444 -> 1001d030 | 00a083f1 000000ff 00100000 00000000
  1414. 03:07:03.444 -> 1001d040 | 00027e71 000200a0 00020303 000000ff
  1415. 03:07:03.444 -> 1001d050 | 00000000 00000000 00000000 00000000
  1416. 03:07:03.444 -> 1001d060 | 00000002 00000000 00000000 00000000
  1417. 03:07:03.487 -> drm: 500 = 0xc
  1418. 03:07:03.487 -> toprgu: 80 = 0x0
  1419. 03:07:03.487 -> [DDR Reserve] ddr reserve mode not be enabled yet
  1420. 03:07:03.487 -> Save DRM_DEBUG_CTL(0xa083f1)
  1421. 03:07:03.487 -> DRM_LATCH_CTL : 0x27e71
  1422. 03:07:03.487 -> DRM_LATCH_CTL2: 0x200a0
  1423. 03:07:03.487 -> drm_update_reg: 1, bits: 0x8000, addr: 0x1001d030, val: 0xa083f1
  1424. 03:07:03.487 -> drm_update_reg: 0, bits: 0x80000, addr: 0x1001d030, val: 0xa083f1
  1425. 03:07:03.487 -> drm_update_reg: 0, bits: 0x200, addr: 0x1001d034, val: 0xff
  1426. 03:07:03.487 -> drm_update_reg: 0, bits: 0x200000, addr: 0x1001d034, val: 0xff
  1427. 03:07:03.487 -> drm_update_reg: 0, bits: 0x100, addr: 0x1001d034, val: 0xff
  1428. 03:07:03.487 -> MTK_DRM_DEBUG_CTL : 0xa083f1
  1429. 03:07:03.559 -> MTK_DRM_DEBUG_CTL2: 0xff
  1430. 03:07:03.559 -> drm_update_reg: 0, bits: 0x4000, addr: 0x1001d030, val: 0xa083f1
  1431. 03:07:03.559 -> DRM DDR reserve mode FAIL! a083f1
  1432. 03:07:03.559 -> DDR RESERVE Success 0
  1433. 03:07:03.559 -> drm_update_reg: 0, bits: 0x2000, addr: 0x1001d030, val: 0xa083f1
  1434. 03:07:03.559 -> drm_update_reg: 0, bits: 0x1000, addr: 0x1001d030, val: 0xa083f1
  1435. 03:07:03.559 -> [DRAM] into mt_set_emi
  1436. 03:07:03.559 -> [EMI] ComboMCP not ready, using default setting
  1437. 03:07:03.559 ->
  1438. 03:07:03.559 -> Init_DRAM:2139: init PCDDR4 dram Start
  1439. 03:07:03.559 -> [MD32_INIT] in c code >>>>>>
  1440. 03:07:03.559 -> [MD32_INIT] 3
  1441. 03:07:03.559 -> [MD32_INIT] 4
  1442. 03:07:03.559 -> [MD32_INIT] 5
  1443. 03:07:03.559 -> [MD32_INIT] 6
  1444. 03:07:03.559 -> [MD32_INIT] V22 add 1
  1445. 03:07:03.559 -> [MD32_INIT] V22 add 1 end
  1446. 03:07:03.559 -> [MD32_INIT] 7
  1447. 03:07:03.559 -> [MD32_INIT] 8
  1448. 03:07:03.559 -> [MD32_INIT] 9
  1449. 03:07:03.559 -> [MD32_INIT] 10
  1450. 03:07:03.559 -> [MD32_INIT] 11
  1451. 03:07:03.559 -> [MD32_INIT] 12
  1452. 03:07:03.559 -> [MD32_INIT] 13
  1453. 03:07:03.559 -> [MD32_INIT] 14
  1454. 03:07:03.559 -> [MD32_INIT] 15
  1455. 03:07:03.559 -> [MD32_INIT] 16
  1456. 03:07:03.559 -> [MD32_INIT] 17
  1457. 03:07:03.559 -> [MD32_INIT] 18
  1458. 03:07:03.559 -> [MD32_INIT] 19
  1459. 03:07:03.559 -> [MD32_INIT] 20
  1460. 03:07:03.559 -> [MD32_INIT] 21
  1461. 03:07:03.559 -> [MD32_INIT] 22
  1462. 03:07:03.559 -> [MD32_INIT] 23
  1463. 03:07:03.614 -> [MD32_INIT] 28
  1464. 03:07:03.614 -> [MD32_INIT] 29
  1465. 03:07:03.614 -> [MD32_INIT] 30 for RTMRW, if have
  1466. 03:07:03.614 -> [MD32_INIT] in c code <<<<<<
  1467. 03:07:03.614 -> [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
  1468. 03:07:03.614 ->
  1469. 03:07:03.614 ->
  1470. 03:07:03.614 -> [Bian_co] ETT version 0.0.0.1
  1471. 03:07:03.614 -> dram_type 4, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=136
  1472. 03:07:03.614 ->
  1473. 03:07:03.614 -> Read voltage for 1600, 0
  1474. 03:07:03.614 -> Vio18 = 0
  1475. 03:07:03.614 -> Vcore = 0
  1476. 03:07:03.614 -> Vdram = 0
  1477. 03:07:03.614 -> Vddq = 0
  1478. 03:07:03.614 -> Vmddr = 0
  1479. 03:07:03.614 -> == DRAMC_CTX_T ==
  1480. 03:07:03.614 -> support_channel_num: 1
  1481. 03:07:03.614 -> channel: 0
  1482. 03:07:03.614 -> support_rank_num: 1
  1483. 03:07:03.614 -> rank: 0
  1484. 03:07:03.614 -> freq_sel: 22
  1485. 03:07:03.614 -> shu_type: 0
  1486. 03:07:03.614 -> dram_type: 4
  1487. 03:07:03.614 -> dram_fsp: 0
  1488. 03:07:03.614 -> odt_onoff: 1
  1489. 03:07:03.614 -> DBI_R_onoff: 0, 0
  1490. 03:07:03.614 -> DBI_W_onoff: 0, 0
  1491. 03:07:03.682 -> data_width: 16
  1492. 03:07:03.682 -> test2_1: 0x55000000
  1493. 03:07:03.682 -> test2_2: 0xaa000100
  1494. 03:07:03.682 -> frequency: 1600
  1495. 03:07:03.682 -> freqGroup: 1600
  1496. 03:07:03.682 -> u1PLLMode: 0
  1497. 03:07:03.682 -> dram type 6
  1498. 03:07:03.682 -> ===============================================================================
  1499. 03:07:03.682 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1500. 03:07:03.682 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1501. 03:07:03.682 -> ===============================================================================
  1502. 03:07:03.682 -> OCD DRVP=0 ,CALOUT=0
  1503. 03:07:03.682 -> OCD DRVP=1 ,CALOUT=0
  1504. 03:07:03.682 -> OCD DRVP=2 ,CALOUT=0
  1505. 03:07:03.682 -> OCD DRVP=3 ,CALOUT=0
  1506. 03:07:03.682 -> OCD DRVP=4 ,CALOUT=0
  1507. 03:07:03.682 -> OCD DRVP=5 ,CALOUT=0
  1508. 03:07:03.682 -> OCD DRVP=6 ,CALOUT=0
  1509. 03:07:03.682 -> OCD DRVP=7 ,CALOUT=0
  1510. 03:07:03.682 -> OCD DRVP=8 ,CALOUT=0
  1511. 03:07:03.682 -> OCD DRVP=9 ,CALOUT=1
  1512. 03:07:03.682 ->
  1513. 03:07:03.682 -> OCD DRVP calibration OK! DRVP=9
  1514. 03:07:03.682 ->
  1515. 03:07:03.682 -> OCD DRVN=0 ,CALOUT=1
  1516. 03:07:03.682 -> OCD DRVN=1 ,CALOUT=1
  1517. 03:07:03.682 -> OCD DRVN=2 ,CALOUT=1
  1518. 03:07:03.745 -> OCD DRVN=3 ,CALOUT=1
  1519. 03:07:03.745 -> OCD DRVN=4 ,CALOUT=1
  1520. 03:07:03.745 -> OCD DRVN=5 ,CALOUT=1
  1521. 03:07:03.745 -> OCD DRVN=6 ,CALOUT=0
  1522. 03:07:03.745 ->
  1523. 03:07:03.745 -> OCD DRVN calibration OK! DRVN=6
  1524. 03:07:03.745 ->
  1525. 03:07:03.745 -> [SwImpedanceCal] DRVP=9, DRVN=6
  1526. 03:07:03.745 -> freq_region=0, Reg: DRVP=11, DRVN=8, ODTP=6
  1527. 03:07:03.745 -> MEM_TYPE=6, freq_sel=22
  1528. 03:07:03.745 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  1529. 03:07:03.745 -> PCDDR4 DRAM CONFIGURATION
  1530. 03:07:03.745 -> ===================================
  1531. 03:07:03.745 -> CWL = 0x7
  1532. 03:07:03.745 -> RTT_NORM = 0x6
  1533. 03:07:03.745 -> CL = 0xb
  1534. 03:07:03.745 -> AL = 0x0
  1535. 03:07:03.745 -> BL = 0x0
  1536. 03:07:03.745 -> RBT = 0x0
  1537. 03:07:03.745 -> WR = 0x8
  1538. 03:07:03.745 -> ===================================
  1539. 03:07:03.745 -> ===================================
  1540. 03:07:03.745 -> ANA top config
  1541. 03:07:03.745 -> ===================================
  1542. 03:07:03.791 -> ASYNC_MODE = 3
  1543. 03:07:03.791 -> DLL_ASYNC_EN = 1
  1544. 03:07:03.791 -> ALL_SLAVE_EN = 0
  1545. 03:07:03.791 -> NEW_RANK_MODE = 0
  1546. 03:07:03.791 -> DLL_IDLE_MODE = 1
  1547. 03:07:03.791 -> LP45_APHY_COMB_EN = 1
  1548. 03:07:03.791 -> TX_ODT_DIS = 0
  1549. 03:07:03.791 -> NEW_8X_MODE = 0
  1550. 03:07:03.791 -> ===================================
  1551. 03:07:03.791 -> ===================================
  1552. 03:07:03.791 -> data_rate = 3200
  1553. 03:07:03.791 -> CKR = 1
  1554. 03:07:03.791 -> DQ_P2S_RATIO = 8
  1555. 03:07:03.791 -> ===================================
  1556. 03:07:03.791 -> CA_P2S_RATIO = 8
  1557. 03:07:03.791 -> DQ_CA_OPEN = 0
  1558. 03:07:03.791 -> DQ_SEMI_OPEN = 0
  1559. 03:07:03.791 -> CA_SEMI_OPEN = 0
  1560. 03:07:03.854 -> CA_FULL_RATE = 0
  1561. 03:07:03.854 -> DQ_CKDIV4_EN = 0
  1562. 03:07:03.854 -> CA_CKDIV4_EN = 0
  1563. 03:07:03.854 -> CA_PREDIV_EN = 0
  1564. 03:07:03.854 -> PH8_DLY = 31
  1565. 03:07:03.854 -> SEMI_OPEN_CA_PICK_MCK_RATIO= 0
  1566. 03:07:03.854 -> DQ_AAMCK_DIV = 4
  1567. 03:07:03.854 -> CA_AAMCK_DIV = 4
  1568. 03:07:03.854 -> CA_ADMCK_DIV = 4
  1569. 03:07:03.854 -> DQ_TRACK_CA_EN = 0
  1570. 03:07:03.854 -> CA_PICK = 1600
  1571. 03:07:03.854 -> CA_MCKIO = 1600
  1572. 03:07:03.854 -> MCKIO_SEMI = 0
  1573. 03:07:03.854 -> PLL_FREQ = 3200
  1574. 03:07:03.854 -> DQ_UI_PI_RATIO = 32
  1575. 03:07:03.854 -> CA_UI_PI_RATIO = 0
  1576. 03:07:03.854 -> ===================================
  1577. 03:07:03.854 -> ===================================
  1578. 03:07:03.854 -> memory_type:PCDDR4
  1579. 03:07:03.854 -> GP_NUM : 1
  1580. 03:07:03.854 -> SRAM_EN : 1
  1581. 03:07:03.854 -> MD32_EN : 0
  1582. 03:07:03.933 -> ===================================
  1583. 03:07:03.933 -> ===========================================
  1584. 03:07:03.933 -> HW_ZQCAL_config
  1585. 03:07:03.933 -> ===========================================
  1586. 03:07:03.933 -> ZQCALL is 0
  1587. 03:07:03.933 -> TZQLAT is 27
  1588. 03:07:03.933 -> ZQCSDUAL is 0
  1589. 03:07:03.933 -> ZQCSCNT is 511
  1590. 03:07:03.933 -> ===========================================
  1591. 03:07:03.933 -> [ANA_INIT] >>>>>>>>>>>>>>
  1592. 03:07:03.933 -> [ANA_ClockOff_Sequence] flow start
  1593. 03:07:03.933 -> WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns start
  1594. 03:07:03.933 -> WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns end
  1595. 03:07:03.933 -> [ANA_ClockOff_Sequence] flow end
  1596. 03:07:03.933 -> ============ PULL DRAM RESETB DOWN ============
  1597. 03:07:03.933 -> ========== PULL DRAM RESETB DOWN end =========
  1598. 03:07:03.933 -> ============ SUSPEND_ON ============
  1599. 03:07:03.933 -> ============ SUSPEND_ON end ============
  1600. 03:07:03.933 -> ============ SPM_control ============
  1601. 03:07:03.933 -> ============ SPM_control end ============
  1602. 03:07:03.933 -> <<<<<< [CONFIGURE PHASE]: ANA_TX
  1603. 03:07:03.933 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
  1604. 03:07:03.933 -> ===================================
  1605. 03:07:03.933 -> data_rate = 3200,PCW = 0X7800
  1606. 03:07:03.995 -> ===================================
  1607. 03:07:03.995 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
  1608. 03:07:03.995 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  1609. 03:07:03.995 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  1610. 03:07:03.995 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  1611. 03:07:03.995 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  1612. 03:07:03.995 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  1613. 03:07:03.995 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  1614. 03:07:03.995 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x0
  1615. 03:07:03.995 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  1616. 03:07:03.995 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  1617. 03:07:03.995 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  1618. 03:07:03.995 -> INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  1619. 03:07:03.995 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  1620. 03:07:03.995 -> INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  1621. 03:07:03.995 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  1622. 03:07:03.995 -> INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  1623. 03:07:04.042 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  1624. 03:07:04.042 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60 PH8_DLY= 0x1f
  1625. 03:07:04.042 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  1626. 03:07:04.042 -> >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
  1627. 03:07:04.042 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  1628. 03:07:04.042 -> INFO: RG_ARCMD_REV_TEMP_VALUE= 0x61
  1629. 03:07:04.042 -> <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
  1630. 03:07:04.042 -> [ANA_INIT] flow start
  1631. 03:07:04.042 -> [ANA_INIT] PLL >>>>>>>>
  1632. 03:07:04.042 -> [ANA_INIT] PLL <<<<<<<<
  1633. 03:07:04.042 -> [ANA_INIT] MIDPI >>>>>>>>
  1634. 03:07:04.042 -> [ANA_INIT] MIDPI <<<<<<<<
  1635. 03:07:04.042 -> [ANA_INIT] DLL >>>>>>>>
  1636. 03:07:04.042 -> [ANA_INIT] DLL <<<<<<<<
  1637. 03:07:04.106 -> [ANA_INIT] flow end
  1638. 03:07:04.106 -> [ANA_INIT] <<<<<<<<<<<<<
  1639. 03:07:04.106 -> [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  1640. 03:07:04.106 -> [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  1641. 03:07:04.106 -> [Flow] Enable top DCM control >>>>>
  1642. 03:07:04.106 -> [Flow] Enable top DCM control <<<<<
  1643. 03:07:04.106 -> Enable DLL master slave shuffle
  1644. 03:07:04.106 -> ==============================================================
  1645. 03:07:04.106 -> Gating Mode config
  1646. 03:07:04.106 -> ==============================================================
  1647. 03:07:04.106 -> Config description:
  1648. 03:07:04.106 -> RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
  1649. 03:07:04.106 -> RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (Jade-like) 2: FIFO mode
  1650. 03:07:04.106 -> SELPH_MODE 0: By rank 1: By Phase
  1651. 03:07:04.106 -> ==============================================================
  1652. 03:07:04.106 -> GAT_TRACK_EN = 1
  1653. 03:07:04.169 -> RX_GATING_MODE = 2
  1654. 03:07:04.169 -> RX_GATING_TRACK_MODE = 2
  1655. 03:07:04.169 -> SELPH_MODE = 1
  1656. 03:07:04.169 -> PICG_EARLY_EN = 1
  1657. 03:07:04.169 -> VALID_LAT_VALUE = 0
  1658. 03:07:04.169 -> ==============================================================
  1659. 03:07:04.169 -> Enter into Gating configuration >>>>
  1660. 03:07:04.169 -> Exit from Gating configuration <<<<
  1661. 03:07:04.169 -> [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  1662. 03:07:04.169 -> [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  1663. 03:07:04.169 -> [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  1664. 03:07:04.169 -> [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  1665. 03:07:04.169 -> Enter into PICG configuration >>>>
  1666. 03:07:04.169 -> Exit from PICG configuration <<<<
  1667. 03:07:04.169 -> [DIG_SHUF_CONFIG] DCM_FUNCTION >>>>>>, group_id=0
  1668. 03:07:04.169 -> [DIG_SHUF_CONFIG] DCM_FUNCTION <<<<<<, group_id=0
  1669. 03:07:04.231 -> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 >>>>>
  1670. 03:07:04.231 -> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 <<<<<
  1671. 03:07:04.231 -> [DIG_HW_SHUF_ZQCAL_CFG] Group:0, Configuration Enter
  1672. 03:07:04.231 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  1673. 03:07:04.231 -> PCDDR4 DRAM CONFIGURATION
  1674. 03:07:04.231 -> ===================================
  1675. 03:07:04.231 -> CWL = 0x7
  1676. 03:07:04.231 -> RTT_NORM = 0x6
  1677. 03:07:04.231 -> CL = 0xb
  1678. 03:07:04.231 -> AL = 0x0
  1679. 03:07:04.231 -> BL = 0x0
  1680. 03:07:04.231 -> RBT = 0x0
  1681. 03:07:04.231 -> WR = 0x8
  1682. 03:07:04.231 -> ===================================
  1683. 03:07:04.231 -> [ReadLatency GET] MR_CL:[ReadLatency GET] MR_CL:UI_MCK_least is 1
  1684. 03:07:04.231 -> RX_GW_selph_by_ps[0] is 12464
  1685. 03:07:04.231 -> RX_GW_selph_by_ps[1] is 12464
  1686. 03:07:04.296 -> RX_GW_selph_by_ps[2] is 12464
  1687. 03:07:04.296 -> RX_GW_selph_by_ps[3] is 12464
  1688. 03:07:04.296 -> ===================================
  1689. 03:07:04.296 -> RX_path CONFIGURATION
  1690. 03:07:04.296 -> ===================================
  1691. 03:07:04.296 -> data_rate is 3200
  1692. 03:07:04.296 -> dq_p2s_ratio is 8
  1693. 03:07:04.296 -> ca_default_delay is 1
  1694. 03:07:04.296 -> ca_ser_latency is 7
  1695. 03:07:04.296 -> cs2RL_start is 1
  1696. 03:07:04.296 -> byte_num is 2
  1697. 03:07:04.296 -> rank_num is 2
  1698. 03:07:04.296 -> RL[0] is 24
  1699. 03:07:04.296 -> RL[1] is 24
  1700. 03:07:04.296 -> RL_min is 24
  1701. 03:07:04.296 -> RL_max is 24
  1702. 03:07:04.296 -> TDQSCK[0] is 0
  1703. 03:07:04.296 -> TDQSCK[1] is 0
  1704. 03:07:04.296 -> TDQSCK[2] is 0
  1705. 03:07:04.296 -> TDQSCK[3] is 0
  1706. 03:07:04.296 -> dqsien_default_delay is 0
  1707. 03:07:04.296 -> dqsien_ser_latency is 7
  1708. 03:07:04.296 -> oe_ser_latency is 4
  1709. 03:07:04.296 -> gating_window_ahead_dqs is 2
  1710. 03:07:04.296 -> aphy_slice_delay is 11
  1711. 03:07:04.357 -> aphy_dtc_delay is 100
  1712. 03:07:04.357 -> aphy_lead_lag_margin is 16
  1713. 03:07:04.357 -> dram_ui_ratio is 2
  1714. 03:07:04.357 -> dq_ui_unit is 312
  1715. 03:07:04.357 -> ca_ui_unit is 312
  1716. 03:07:04.357 -> MCK_unit is 2496
  1717. 03:07:04.357 -> dramc_dram_ratio is 4
  1718. 03:07:04.357 -> CKR is 1
  1719. 03:07:04.357 -> tRPRE_toggle is 0
  1720. 03:07:04.357 -> tRPRE_static is 2
  1721. 03:07:04.357 -> tRPST is 0
  1722. 03:07:04.357 -> DQSIENMODE is 1
  1723. 03:07:04.357 -> BL is 16
  1724. 03:07:04.357 -> FAKE_1TO16_MODE is 0
  1725. 03:07:04.357 -> SVA_1_10_t2_SPEC is 11
  1726. 03:07:04.357 -> read_cmd_out is 1
  1727. 03:07:04.357 -> ca_MCKIO_ui_unit is 312
  1728. 03:07:04.357 -> ca_p2s_ratio is 8
  1729. 03:07:04.357 -> TDQSCK_min_SPEC is 0
  1730. 03:07:04.357 -> TDQSCK_max_SPEC is 360
  1731. 03:07:04.357 -> TX_pipeline is 1
  1732. 03:07:04.357 -> RX_pipeline is 1
  1733. 03:07:04.357 -> NEW_RANK_MODE is 0
  1734. 03:07:04.406 -> close_loop_mode is 1
  1735. 03:07:04.406 -> ===================================
  1736. 03:07:04.406 -> ===================================
  1737. 03:07:04.406 -> RX_path RG value
  1738. 03:07:04.406 -> ===================================
  1739. 03:07:04.406 -> RX_UI_P0[0] is 15
  1740. 03:07:04.406 -> RX_UI_P0[1] is 15
  1741. 03:07:04.406 -> RX_UI_P0[2] is 15
  1742. 03:07:04.406 -> RX_UI_P0[3] is 15
  1743. 03:07:04.406 -> RX_UI_P1[0] is 19
  1744. 03:07:04.406 -> RX_UI_P1[1] is 19
  1745. 03:07:04.406 -> RX_UI_P1[2] is 19
  1746. 03:07:04.406 -> RX_UI_P1[3] is 19
  1747. 03:07:04.406 -> RX_PI[0] is 31
  1748. 03:07:04.406 -> RX_PI[1] is 31
  1749. 03:07:04.406 -> RX_PI[2] is 31
  1750. 03:07:04.406 -> RX_PI[3] is 31
  1751. 03:07:04.406 -> DQSINCTL is 3
  1752. 03:07:04.469 -> DATLAT_DSEL is 11
  1753. 03:07:04.469 -> DATLAT is 12
  1754. 03:07:04.469 -> DATLAT_DSEL_PHY is 12
  1755. 03:07:04.469 -> DLE_EXTEND is 1
  1756. 03:07:04.469 -> RX_IN_GATE_EN_HEAD is 0
  1757. 03:07:04.469 -> RX_IN_GATE_EN_TAIL is 0
  1758. 03:07:04.469 -> RX_IN_BUFF_EN_HEAD is 2
  1759. 03:07:04.469 -> RX_IN_BUFF_EN_TAIL is 0
  1760. 03:07:04.469 -> RX_IN_GATE_EN_PRE_OFFSET is 2
  1761. 03:07:04.469 -> RANKINCTL_ROOT1 is 1
  1762. 03:07:04.469 -> RANKINCTL is 1
  1763. 03:07:04.469 -> RANKINCTL_STB is 2
  1764. 03:07:04.469 -> RANKINCTL_RXDLY is 0
  1765. 03:07:04.469 -> SHU_GW_THRD_POS is 42
  1766. 03:07:04.469 -> SHU_GW_THRD_NEG is 0
  1767. 03:07:04.469 -> RDSEL_TRACK_EN is 0
  1768. 03:07:04.469 -> RDSEL_HWSAVE_MSK is 1
  1769. 03:07:04.469 -> DMDATLAT_i is 12
  1770. 03:07:04.469 -> RODTEN is 0
  1771. 03:07:04.469 -> RODT is 0
  1772. 03:07:04.469 -> RODTE is 1
  1773. 03:07:04.469 -> RODTE2 is 1
  1774. 03:07:04.542 -> ODTEN_MCK_P0[4] is 0
  1775. 03:07:04.542 -> ODTEN_MCK_P1[4] is 0
  1776. 03:07:04.542 -> ODTEN_UI_P0[4] is 0
  1777. 03:07:04.542 -> ODTEN_UI_P1[4] is 0
  1778. 03:07:04.542 -> RX_RANK_DQS_LAT is 0
  1779. 03:07:04.542 -> RX_RANK_DQ_LAT is 1
  1780. 03:07:04.542 -> RANKINCTL_PHY is 5
  1781. 03:07:04.542 -> RANK_SEL_LAT_CA is 0
  1782. 03:07:04.542 -> RANK_SEL_LAT_B0 is 0
  1783. 03:07:04.542 -> RANK_SEL_LAT_B1 is 0
  1784. 03:07:04.542 -> RANK_SEL_STB_EN is 0
  1785. 03:07:04.542 -> RANK_SEL_RXDLY_TRACK is 0
  1786. 03:07:04.542 -> RANK_SEL_STB_TRACK is 1
  1787. 03:07:04.542 -> RANK_SEL_STB_PHASE_EN is 1
  1788. 03:07:04.542 -> RANK_SEL_PHSINCTL is 2
  1789. 03:07:04.542 -> RANK_SEL_STB_UI_MINUS is 2
  1790. 03:07:04.542 -> RANK_SEL_STB_UI_PLUS is 0
  1791. 03:07:04.542 -> RANK_SEL_MCK_P0 is 0
  1792. 03:07:04.542 -> RANK_SEL_UI_P0 is 0
  1793. 03:07:04.542 -> RANK_SEL_MCK_P1 is 1
  1794. 03:07:04.542 -> RANK_SEL_UI_P1 is 0
  1795. 03:07:04.542 -> R0DQSIENLLMTEN is 1
  1796. 03:07:04.542 -> R0DQSIENLLMT is 96
  1797. 03:07:04.542 -> R0DQSIENHLMTEN is 1
  1798. 03:07:04.542 -> R0DQSIENHLMT is 63
  1799. 03:07:04.542 -> R1DQSIENLLMTEN is 1
  1800. 03:07:04.542 -> R1DQSIENLLMT is 96
  1801. 03:07:04.589 -> R1DQSIENHLMTEN is 1
  1802. 03:07:04.589 -> R1DQSIENHLMT is 63
  1803. 03:07:04.589 -> DQSIEN_FIFO_DEPTH_HALF is 1
  1804. 03:07:04.589 -> ===================================
  1805. 03:07:04.589 -> [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  1806. 03:07:04.589 -> PCDDR4 DRAM CONFIGURATION
  1807. 03:07:04.589 -> ===================================
  1808. 03:07:04.589 -> CWL = 0x7
  1809. 03:07:04.589 -> RTT_NORM = 0x6
  1810. 03:07:04.589 -> CL = 0xb
  1811. 03:07:04.589 -> AL = 0x0
  1812. 03:07:04.589 -> BL = 0x0
  1813. 03:07:04.589 -> RBT = 0x0
  1814. 03:07:04.589 -> WR = 0x8
  1815. 03:07:04.589 -> ===================================
  1816. 03:07:04.651 -> [WriteLatency GET] MR_CWL:[WriteLatency GET] MR_CWL:=====================================
  1817. 03:07:04.651 -> print TX_path_config
  1818. 03:07:04.651 -> =====================================
  1819. 03:07:04.651 -> data_ratio is 3200
  1820. 03:07:04.651 -> dq_p2s_ratio is 8
  1821. 03:07:04.651 -> cs2WL_start is 1
  1822. 03:07:04.651 -> byte_num is 2
  1823. 03:07:04.651 -> rank_num is 2
  1824. 03:07:04.651 -> CKR is 1
  1825. 03:07:04.651 -> DBI_WR is 0
  1826. 03:07:04.651 -> dly_1T_by_FDIV2 is 0
  1827. 03:07:04.651 -> WL[0] is 20
  1828. 03:07:04.651 -> WL[1] is 20
  1829. 03:07:04.651 -> TDQSS[0][0] is 156
  1830. 03:07:04.651 -> TDQSS[0][1] is 156
  1831. 03:07:04.651 -> TDQSS[1][0] is 156
  1832. 03:07:04.651 -> TDQSS[1][1] is 156
  1833. 03:07:04.651 -> TDQS2DQ[0][0] is 0
  1834. 03:07:04.651 -> TDQS2DQ[0][1] is 0
  1835. 03:07:04.651 -> TDQS2DQ[1][0] is 0
  1836. 03:07:04.714 -> TDQS2DQ[1][1] is 0
  1837. 03:07:04.714 -> ca_p2s_ratio is 8
  1838. 03:07:04.714 -> ca_default_dly is 1
  1839. 03:07:04.714 -> ca_default_pi is 0
  1840. 03:07:04.714 -> ca_ser_latency is 7
  1841. 03:07:04.714 -> dqs_ser_laterncy is 7
  1842. 03:07:04.714 -> dqs_default_dly is 5
  1843. 03:07:04.714 -> dqs_oe_default_dly is 2
  1844. 03:07:04.714 -> dq_ser_laterncy is 7
  1845. 03:07:04.714 -> MCK_unit is 2496
  1846. 03:07:04.714 -> dq_ui_unit is 312
  1847. 03:07:04.714 -> ca_unit is 312
  1848. 03:07:04.714 -> ca_MCKIO_unit is 312
  1849. 03:07:04.714 -> ca_frate is 0
  1850. 03:07:04.714 -> TX_ECC is 0
  1851. 03:07:04.714 -> TWPRE is 4
  1852. 03:07:04.714 -> OE_pre_margin is 400
  1853. 03:07:04.714 -> OE_pst_margin is 500
  1854. 03:07:04.714 -> OE_downgrade is 1
  1855. 03:07:04.714 -> aphy_slice_dly is 11
  1856. 03:07:04.714 -> aphy_dtc_dly is 100
  1857. 03:07:04.776 -> aphy_tx_dly is 16
  1858. 03:07:04.776 -> DDRPHY_CLK_EN_COMB_TX_OPT is 1
  1859. 03:07:04.776 -> NEW_RANK_MODE is 0
  1860. 03:07:04.776 -> close_loop_mode is 1
  1861. 03:07:04.776 -> TXP_WORKAROUND_OPT is 0
  1862. 03:07:04.776 -> ui2pi_ratio is 32
  1863. 03:07:04.776 -> XRTW2W_PI_mute_time is 7
  1864. 03:07:04.776 -> fake_mode is 0
  1865. 03:07:04.776 -> ===========================================
  1866. 03:07:04.776 -> TX_DQ_UI_OE_pre is 2
  1867. 03:07:04.776 -> TX_DQS_UI_OE_pre is 1
  1868. 03:07:04.776 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  1869. 03:07:04.776 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  1870. 03:07:04.776 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  1871. 03:07:04.776 -> data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  1872. 03:07:04.776 -> ===========================================
  1873. 03:07:04.776 -> print TX_path_attribution
  1874. 03:07:04.823 -> ===========================================
  1875. 03:07:04.823 -> TX_DQ_MCK_OE[0][0] is 2
  1876. 03:07:04.823 -> TX_DQ_MCK_OE[0][1] is 2
  1877. 03:07:04.823 -> TX_DQ_MCK_OE[1][0] is 2
  1878. 03:07:04.823 -> TX_DQ_MCK_OE[1][1] is 2
  1879. 03:07:04.823 -> TX_DQ_UI_OE[0][0] is 6
  1880. 03:07:04.823 -> TX_DQ_UI_OE[0][1] is 6
  1881. 03:07:04.823 -> TX_DQ_UI_OE[1][0] is 6
  1882. 03:07:04.823 -> TX_DQ_UI_OE[1][1] is 6
  1883. 03:07:04.823 -> TX_DQ_MCK[0][0] is 3
  1884. 03:07:04.823 -> TX_DQ_MCK[0][1] is 3
  1885. 03:07:04.823 -> TX_DQ_MCK[1][0] is 3
  1886. 03:07:04.823 -> TX_DQ_MCK[1][1] is 3
  1887. 03:07:04.823 -> TX_DQ_UI[0][0] is 2
  1888. 03:07:04.886 -> TX_DQ_UI[0][1] is 2
  1889. 03:07:04.886 -> TX_DQ_UI[1][0] is 2
  1890. 03:07:04.886 -> TX_DQ_UI[1][1] is 2
  1891. 03:07:04.886 -> TX_DQ_PI[0][0] is 0
  1892. 03:07:04.886 -> TX_DQ_PI[0][1] is 0
  1893. 03:07:04.886 -> TX_DQ_PI[1][0] is 0
  1894. 03:07:04.886 -> TX_DQ_PI[1][1] is 0
  1895. 03:07:04.886 -> TX_DQ_UIPI_all[0][0] is 0
  1896. 03:07:04.886 -> TX_DQ_UIPI_all[0][1] is 0
  1897. 03:07:04.886 -> TX_DQ_UIPI_all[1][0] is 0
  1898. 03:07:04.886 -> TX_DQ_UIPI_all[1][1] is 0
  1899. 03:07:04.886 -> TX_DQ_dlyline[0][0] is 0
  1900. 03:07:04.886 -> TX_DQ_dlyline[0][1] is 0
  1901. 03:07:04.886 -> TX_DQ_dlyline[1][0] is 0
  1902. 03:07:04.886 -> TX_DQ_dlyline[1][1] is 0
  1903. 03:07:04.886 -> TX_DQS_MCK_OE[0][0] is 2
  1904. 03:07:04.886 -> TX_DQS_MCK_OE[0][1] is 2
  1905. 03:07:04.948 -> TX_DQS_MCK_OE[1][0] is 2
  1906. 03:07:04.948 -> TX_DQS_MCK_OE[1][1] is 2
  1907. 03:07:04.948 -> TX_DQS_UI_OE[0][0] is 6
  1908. 03:07:04.948 -> TX_DQS_UI_OE[0][1] is 6
  1909. 03:07:04.948 -> TX_DQS_UI_OE[1][0] is 6
  1910. 03:07:04.948 -> TX_DQS_UI_OE[1][1] is 6
  1911. 03:07:04.948 -> TX_DQS_MCK[0][0] is 3
  1912. 03:07:04.948 -> TX_DQS_MCK[0][1] is 3
  1913. 03:07:04.948 -> TX_DQS_MCK[1][0] is 3
  1914. 03:07:04.948 -> TX_DQS_MCK[1][1] is 3
  1915. 03:07:04.948 -> TX_DQS_UI[0][0] is 1
  1916. 03:07:04.948 -> TX_DQS_UI[0][1] is 1
  1917. 03:07:04.948 -> TX_DQS_UI[1][0] is 1
  1918. 03:07:04.948 -> TX_DQS_UI[1][1] is 1
  1919. 03:07:04.948 -> DDRPHY_CLK_EN_COMB_TX_OPT is 1
  1920. 03:07:04.948 -> TX_DQS_PI[0][0] is 16
  1921. 03:07:04.948 -> TX_DQS_PI[0][1] is 16
  1922. 03:07:05.011 -> TX_DQS_PI[1][0] is 16
  1923. 03:07:05.011 -> TX_DQS_PI[1][1] is 16
  1924. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_PICG_CNT is 2
  1925. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 is 3
  1926. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 is 4
  1927. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0 is 3
  1928. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1 is 4
  1929. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P0 is 3
  1930. 03:07:05.011 -> DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P1 is 4
  1931. 03:07:05.011 -> DPHY_TX_DCM_EXTCNT is 0
  1932. 03:07:05.011 -> TX_PI_UPD_MODE is 1
  1933. 03:07:05.011 -> TX_PI_UPDCTL_B0 is 0
  1934. 03:07:05.011 -> TX_PI_UPDCTL_B1 is 0
  1935. 03:07:05.011 -> TX_RANKINCTL_ROOT is 0
  1936. 03:07:05.011 -> TX_RANKINCTL is 1
  1937. 03:07:05.011 -> TX_RANKINCTL_TXDLY is 2
  1938. 03:07:05.011 -> DDRPHY_CLK_DYN_GATING_SEL is 5
  1939. 03:07:05.011 -> DDRPHY_CLK_EN_OPT is 1
  1940. 03:07:05.072 -> ARPI_CMD is 0
  1941. 03:07:05.072 -> TDMY is 9
  1942. 03:07:05.072 -> TXOEN_AUTOSET_DQ_OFFSET is 3
  1943. 03:07:05.072 -> TXOEN_AUTOSET_DQS_OFFSET is 3
  1944. 03:07:05.072 -> TXOEN_AUTOSET_EN is 1
  1945. 03:07:05.072 -> TXPICG_AUTOSET_OPT is 0
  1946. 03:07:05.072 -> TXPICG_AUTOSET_EN is 1
  1947. 03:07:05.072 -> TXPICG_DQ_MCK_OFFSET_LAG is 0
  1948. 03:07:05.072 -> TXPICG_DQS_MCK_OFFSET_LAG is 0
  1949. 03:07:05.072 -> TXPICG_DQ_UI_OFFSET_LEAD is 0
  1950. 03:07:05.072 -> TXPICG_DQ_UI_OFFSET_LAG is 1
  1951. 03:07:05.072 -> TXPICG_DQS_UI_OFFSET_LEAD is 1
  1952. 03:07:05.072 -> TXPICG_DQS_UI_OFFSET_LAG is 0
  1953. 03:07:05.072 -> ===========================================
  1954. 03:07:05.072 -> set APHY_PI_CKCGH_CNT is 4 when not fake_mode, cur data_rate is 3200
  1955. 03:07:05.142 -> [DIG_SHUF_CONFIG] MISC >>>>>, group_id=0
  1956. 03:07:05.142 -> [DIG_SHUF_CONFIG] MISC <<<<<<, group_id=0
  1957. 03:07:05.142 -> [DIG_SHUF_CONFIG] DBI >>>>>>, group_id=0
  1958. 03:07:05.142 -> [DIG_SHUF_CONFIG] DBI <<<<<<, group_id=0
  1959. 03:07:05.142 -> dramc_dram_ratio: 4
  1960. 03:07:05.142 -> DDR4_DivMode: 1
  1961. 03:07:05.142 -> freq_index: 1600
  1962. 03:07:05.142 -> match AC timing 1
  1963. 03:07:05.142 -> [DDR4_ac_timing_setting]start
  1964. 03:07:05.142 -> [PC4 WR preamble settings]>>>>>>>> group_id = 0.
  1965. 03:07:05.142 -> [PC4 WR preamble settings]<<<<<<<< group_id = 0.
  1966. 03:07:05.142 -> clk_dramc_ref_sel FREQ=16
  1967. 03:07:05.142 -> fmem_ck_bfe_dcm_ch0 FREQ=253
  1968. 03:07:05.142 -> fmem_ck_aft_dcm_ch0 FREQ=253
  1969. 03:07:05.142 -> SetClkFreeRun enter => DRAM clock free run mode = ON.
  1970. 03:07:05.142 -> [DDR4] Pull Down reset.
  1971. 03:07:05.142 -> [DDR4] cke fix low 10ns at least.
  1972. 03:07:05.142 -> [DDR4] Delay 200 us.
  1973. 03:07:05.142 -> [DDR4] Pull Up reset.
  1974. 03:07:05.142 -> [DDR4] Delay 500 us.
  1975. 03:07:05.142 -> [DDR4] DRAM initilization RK:0 Enter >>>>>>>>
  1976. 03:07:05.142 -> [DDR4] Delay TXPR TRFC+10ns - 350ns(8Gb density)+10ns
  1977. 03:07:05.142 -> [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:3-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:4-OP:0x[DDR4_MRS] RK:0-MA:5-OP:0x[DDR4] DQ Vref calibration>>>>>>>
  1978. 03:07:05.216 -> [DDR4] DQ Vref Enable DQ vref calibration.
  1979. 03:07:05.216 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQE-150ns
  1980. 03:07:05.216 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] DQ Vref modify range and value
  1981. 03:07:05.216 -> [DDR4] DQ Vref Exit DQ vref calibration.
  1982. 03:07:05.216 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQx-150ns
  1983. 03:07:05.216 -> [DDR4] DQ Vref calibration<<<<<<<
  1984. 03:07:05.216 -> [DDR4_MRS] RK:0-MA:0-OP:0x[DDR4_ZQ] RK:0 Enter >>>>>>>>
  1985. 03:07:05.216 -> [DDR4_ZQ] RK:0 Exit <<<<<<<<
  1986. 03:07:05.216 -> [DDR4] Delay ZQinit - 718ns for 1333 at least max(512Mck,640ns)
  1987. 03:07:05.216 -> [DDR4] DRAM initilization RK:0 Exit <<<<<<<
  1988. 03:07:05.216 -> [DDR4] Enable refresh.....All bank refresh only
  1989. 03:07:05.216 -> SetClkFreeRun enter => DRAM clock free run mode = OFF.
  1990. 03:07:05.216 -> [DIG_HW_NONSHUF_ZQCAL_SWITCH],Configuration Enter
  1991. 03:07:05.216 -> [DIG_HW_NONSHUF_DQSG_SWITCH],Configuration Enter
  1992. 03:07:05.216 -> SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
  1993. 03:07:05.216 -> [MiockJmeterHQA]
  1994. 03:07:05.298 -> ===============================================================================
  1995. 03:07:05.298 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  1996. 03:07:05.298 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1997. 03:07:05.298 -> ===============================================================================
  1998. 03:07:05.298 ->
  1999. 03:07:05.298 -> [DramcMiockJmeter] u1RxGatingPI = 0
  2000. 03:07:05.298 -> 0 : 2282, 2282
  2001. 03:07:05.298 -> 1 : 2271, 2271
  2002. 03:07:05.298 -> 2 : 2271, 2271
  2003. 03:07:05.298 -> 3 : 2271, 2271
  2004. 03:07:05.298 -> 4 : 2271, 2271
  2005. 03:07:05.298 -> 5 : 2271, 2271
  2006. 03:07:05.298 -> 6 : 2271, 2271
  2007. 03:07:05.298 -> 7 : 2271, 2271
  2008. 03:07:05.298 -> 8 : 2271, 2271
  2009. 03:07:05.298 -> 9 : 2271, 2271
  2010. 03:07:05.298 -> 10 : 2271, 2271
  2011. 03:07:05.298 -> 11 : 2272, 2272
  2012. 03:07:05.298 -> 12 : 2276, 2276
  2013. 03:07:05.298 -> 13 : 2272, 2272
  2014. 03:07:05.298 -> 14 : 2271, 2271
  2015. 03:07:05.298 -> 15 : 2276, 2276
  2016. 03:07:05.298 -> 16 : 2271, 2271
  2017. 03:07:05.298 -> 17 : 2271, 2271
  2018. 03:07:05.298 -> 18 : 2271, 2271
  2019. 03:07:05.298 -> 19 : 2271, 2271
  2020. 03:07:05.298 -> 20 : 2272, 2272
  2021. 03:07:05.298 -> 21 : 2271, 2271
  2022. 03:07:05.298 -> 22 : 2271, 2271
  2023. 03:07:05.298 -> 23 : 2266, 2266
  2024. 03:07:05.298 -> 24 : 2271, 2271
  2025. 03:07:05.298 -> 25 : 2272, 2272
  2026. 03:07:05.298 -> 26 : 2272, 2272
  2027. 03:07:05.298 -> 27 : 2271, 2271
  2028. 03:07:05.298 -> 28 : 2271, 2271
  2029. 03:07:05.298 -> 29 : 2276, 2276
  2030. 03:07:05.298 -> 30 : 2272, 2272
  2031. 03:07:05.298 -> 31 : 2271, 2271
  2032. 03:07:05.298 -> 32 : 2272, 2272
  2033. 03:07:05.298 -> 33 : 2271, 2271
  2034. 03:07:05.298 -> 34 : 2271, 2271
  2035. 03:07:05.298 -> 35 : 2272, 2269
  2036. 03:07:05.298 -> 36 : 2272, 227
  2037. 03:07:05.374 -> 37 : 2271, 0
  2038. 03:07:05.374 -> 38 : 2272, 0
  2039. 03:07:05.374 -> 39 : 2272, 0
  2040. 03:07:05.374 -> 40 : 2276, 0
  2041. 03:07:05.374 -> 41 : 2272, 0
  2042. 03:07:05.374 -> 42 : 2271, 0
  2043. 03:07:05.374 -> 43 : 2277, 0
  2044. 03:07:05.374 -> 44 : 2271, 0
  2045. 03:07:05.374 -> 45 : 2271, 0
  2046. 03:07:05.374 -> 46 : 2272, 0
  2047. 03:07:05.374 -> 47 : 2272, 0
  2048. 03:07:05.374 -> 48 : 2277, 0
  2049. 03:07:05.374 -> 49 : 2272, 0
  2050. 03:07:05.374 -> 50 : 2271, 0
  2051. 03:07:05.374 -> 51 : 2271, 0
  2052. 03:07:05.374 -> 52 : 2272, 0
  2053. 03:07:05.374 -> 53 : 2272, 0
  2054. 03:07:05.374 -> 54 : 2271, 0
  2055. 03:07:05.374 -> 55 : 2271, 0
  2056. 03:07:05.374 -> 56 : 2272, 0
  2057. 03:07:05.374 -> 57 : 2271, 0
  2058. 03:07:05.374 -> 58 : 2271, 0
  2059. 03:07:05.374 -> 59 : 2271, 0
  2060. 03:07:05.374 -> 60 : 2272, 0
  2061. 03:07:05.374 -> 61 : 2276, 0
  2062. 03:07:05.374 -> 62 : 2276, 0
  2063. 03:07:05.374 -> 63 : 2272, 0
  2064. 03:07:05.374 -> 64 : 2271, 0
  2065. 03:07:05.374 -> 65 : 2271, 0
  2066. 03:07:05.374 -> 66 : 2272, 0
  2067. 03:07:05.374 -> 67 : 2272, 0
  2068. 03:07:05.374 -> 68 : 2266, 0
  2069. 03:07:05.374 -> 69 : 2272, 0
  2070. 03:07:05.374 -> 70 : 2276, 0
  2071. 03:07:05.374 -> 71 : 2271, 0
  2072. 03:07:05.374 -> 72 : 2271, 0
  2073. 03:07:05.374 -> 73 : 2272, 0
  2074. 03:07:05.374 -> 74 : 2271, 0
  2075. 03:07:05.374 -> 75 : 2272, 0
  2076. 03:07:05.374 -> 76 : 2271, 0
  2077. 03:07:05.374 -> 77 : 2271, 0
  2078. 03:07:05.374 -> 78 : 2276, 0
  2079. 03:07:05.374 -> 79 : 2276, 0
  2080. 03:07:05.374 -> 80 : 2272, 0
  2081. 03:07:05.374 -> 81 : 2271, 0
  2082. 03:07:05.374 -> 82 : 2272, 0
  2083. 03:07:05.374 -> 83 : 2271, 0
  2084. 03:07:05.374 -> 84 : 2272, 0
  2085. 03:07:05.374 -> 85 : 2271, 49
  2086. 03:07:05.374 -> 86 : 2272, 2169
  2087. 03:07:05.374 -> 87 : 2277, 2277
  2088. 03:07:05.374 -> 88 : 2271, 2271
  2089. 03:07:05.374 -> 89 : 2272, 2272
  2090. 03:07:05.374 -> 90 : 2271, 2271
  2091. 03:07:05.374 -> 91 : 2272, 2272
  2092. 03:07:05.374 -> 92 : 2271, 2271
  2093. 03:07:05.374 -> 93 : 2276, 2276
  2094. 03:07:05.432 -> 94 : 2271, 2271
  2095. 03:07:05.432 -> 95 : 2271, 2271
  2096. 03:07:05.432 -> 96 : 2272, 2272
  2097. 03:07:05.432 -> 97 : 2277, 2277
  2098. 03:07:05.432 -> 98 : 2271, 2271
  2099. 03:07:05.432 -> 99 : 2276, 2276
  2100. 03:07:05.432 -> 100 : 2272, 2272
  2101. 03:07:05.432 -> 101 : 2271, 2271
  2102. 03:07:05.432 -> 102 : 2271, 2271
  2103. 03:07:05.432 -> 103 : 2271, 2271
  2104. 03:07:05.432 -> 104 : 2271, 2271
  2105. 03:07:05.432 -> 105 : 2276, 2276
  2106. 03:07:05.432 -> 106 : 2276, 2276
  2107. 03:07:05.432 -> 107 : 2272, 2272
  2108. 03:07:05.432 -> 108 : 2272, 2272
  2109. 03:07:05.432 -> 109 : 2276, 2276
  2110. 03:07:05.432 -> 110 : 2272, 2272
  2111. 03:07:05.432 -> 111 : 2272, 2272
  2112. 03:07:05.432 -> 112 : 2272, 2272
  2113. 03:07:05.432 -> 113 : 2272, 2272
  2114. 03:07:05.432 -> 114 : 2271, 2271
  2115. 03:07:05.432 -> 115 : 2271, 2271
  2116. 03:07:05.432 -> 116 : 2267, 2267
  2117. 03:07:05.432 -> 117 : 2272, 2272
  2118. 03:07:05.432 -> 118 : 2272, 2272
  2119. 03:07:05.432 -> 119 : 2271, 2271
  2120. 03:07:05.432 -> 120 : 2272, 2272
  2121. 03:07:05.432 -> 121 : 2272, 2272
  2122. 03:07:05.432 -> 122 : 2272, 2272
  2123. 03:07:05.432 -> 123 : 2272, 2272
  2124. 03:07:05.432 -> 124 : 2271, 2271
  2125. 03:07:05.432 -> 125 : 2271, 2271
  2126. 03:07:05.432 -> 126 : 2271, 2224
  2127. 03:07:05.432 -> 127 : 2272, 216
  2128. 03:07:05.432 ->
  2129. 03:07:05.432 -> MIOCK jitter meter ch=0
  2130. 03:07:05.432 ->
  2131. 03:07:05.432 -> 1T = (127-36) = 91 dly cells
  2132. 03:07:05.432 -> Clock freq = 1560 MHz, period = 641 ps, 1 dly cell = 704/100 ps
  2133. 03:07:05.503 ->
  2134. 03:07:05.503 -> ----->DramcWriteLeveling(PI) begin...
  2135. 03:07:05.503 -> ===============================================================================
  2136. 03:07:05.503 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2137. 03:07:05.503 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2138. 03:07:05.503 -> ===============================================================================
  2139. 03:07:05.503 -> Begin: 0, End: 63, Step: 1, Bound: 64
  2140. 03:07:05.503 -> [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[Write Leveling]
  2141. 03:07:05.503 -> delay byte0 byte1 byte2 byte3
  2142. 03:07:05.503 ->
  2143. 03:07:05.503 -> 0 O1( 1 1
  2144. 03:07:05.503 -> 1 O1( 1 1
  2145. 03:07:05.503 -> 2 O1( 1 1
  2146. 03:07:05.503 -> 3 O1( 1 1
  2147. 03:07:05.503 -> 4 O1( 1 1
  2148. 03:07:05.503 -> 5 O1( 1 1
  2149. 03:07:05.503 -> 6 O1( 1 1
  2150. 03:07:05.503 -> 7 O1( 1 1
  2151. 03:07:05.503 -> 8 O1( 1 1
  2152. 03:07:05.503 -> 9 O1( 1 1
  2153. 03:07:05.503 -> 10 O1( 1 1
  2154. 03:07:05.503 -> 11 O1( 1 0
  2155. 03:07:05.503 -> 12 O1( 1 0
  2156. 03:07:05.503 -> 13 O1( 1 0
  2157. 03:07:05.566 -> 14 O1( 1 0
  2158. 03:07:05.566 -> 15 O1( 0 0
  2159. 03:07:05.566 -> 16 O1( 0 0
  2160. 03:07:05.566 -> 17 O1( 0 0
  2161. 03:07:05.566 -> 18 O1( 0 0
  2162. 03:07:05.566 -> 19 O1( 0 0
  2163. 03:07:05.566 -> 20 O1( 0 0
  2164. 03:07:05.566 -> 21 O1( 0 0
  2165. 03:07:05.566 -> 22 O1( 0 0
  2166. 03:07:05.566 -> 23 O1( 0 0
  2167. 03:07:05.566 -> 24 O1( 0 0
  2168. 03:07:05.566 -> 25 O1( 0 0
  2169. 03:07:05.566 -> 26 O1( 0 0
  2170. 03:07:05.566 -> 27 O1( 0 0
  2171. 03:07:05.566 -> 28 O1( 0 0
  2172. 03:07:05.566 -> 29 O1( 0 0
  2173. 03:07:05.566 -> 30 O1( 0 0
  2174. 03:07:05.566 -> 31 O1( 0 0
  2175. 03:07:05.566 -> 32 O1( 0 0
  2176. 03:07:05.566 -> 33 O1( 0 0
  2177. 03:07:05.566 -> 34 O1( 0 0
  2178. 03:07:05.566 -> 35 O1( 0 0
  2179. 03:07:05.566 -> 36 O1( 0 0
  2180. 03:07:05.566 -> 37 O1( 0 0
  2181. 03:07:05.566 -> 38 O1( 0 0
  2182. 03:07:05.566 -> 39 O1( 0 0
  2183. 03:07:05.630 -> 40 O1( 0 0
  2184. 03:07:05.630 -> 41 O1( 0 0
  2185. 03:07:05.630 -> 42 O1( 0 1
  2186. 03:07:05.630 -> 43 O1( 1 1
  2187. 03:07:05.630 -> 44 O1( 1 1
  2188. 03:07:05.630 -> 45 O1( 1 1
  2189. 03:07:05.630 -> 46 O1( 1 1
  2190. 03:07:05.630 -> 47 O1( 1 1
  2191. 03:07:05.630 -> 48 O1( 1 1
  2192. 03:07:05.630 -> 49 O1( 1 1
  2193. 03:07:05.630 -> Early breakpass bytecount = 0xff (0xff: all bytes pass)
  2194. 03:07:05.630 ->
  2195. 03:07:05.630 -> [DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:2-OP:0xWrite leveling (Byte 0): 43 => 43
  2196. 03:07:05.630 -> Write leveling (Byte 1): 42 => 42
  2197. 03:07:05.630 -> DramcWriteLeveling(PI) end<-----
  2198. 03:07:05.630 ->
  2199. 03:07:05.630 -> ===============================================================================
  2200. 03:07:05.630 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2201. 03:07:05.630 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2202. 03:07:05.630 -> ===============================================================================
  2203. 03:07:05.630 -> [Gating] SW mode calibration
  2204. 03:07:05.695 -> [get_gating_start_pos] calculated gating ui = 15
  2205. 03:07:05.695 -> 12 0 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  2206. 03:07:05.695 -> 12 4 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  2207. 03:07:05.695 -> 12 8 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 0)
  2208. 03:07:05.695 -> 12 12 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 1)
  2209. 03:07:05.695 -> 12 16 | B1->B0 | 0 1111 | 1 1 | (0 0) (0 1)
  2210. 03:07:05.695 -> 12 20 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2211. 03:07:05.695 -> 12 24 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2212. 03:07:05.695 -> 12 28 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2213. 03:07:05.695 -> 13 0 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2214. 03:07:05.695 -> 13 4 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2215. 03:07:05.695 -> 13 8 | B1->B0 | 0 1111 | 1 1 | (0 0) (1 1)
  2216. 03:07:05.695 -> 13 12 | B1->B0 | 1111 1313 | 1 1 | (0 0) (1 1)
  2217. 03:07:05.695 -> 13 16 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2218. 03:07:05.695 -> 13 20 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2219. 03:07:05.695 -> 13 24 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2220. 03:07:05.742 -> 13 28 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2221. 03:07:05.742 -> 14 0 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2222. 03:07:05.742 -> 14 4 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2223. 03:07:05.742 -> 14 8 | B1->B0 | 1111 2323 | 1 1 | (0 0) (0 0)
  2224. 03:07:05.742 -> 14 12 | B1->B0 | 1111 2323 | 1 1 | (0 1) (0 1)
  2225. 03:07:05.742 -> 14 16 | B1->B0 | 1111 2323 | 1 1 | (0 1) (0 1)
  2226. 03:07:05.742 -> 14 20 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  2227. 03:07:05.742 -> 14 24 | B1->B0 | 1111 2323 | 1 1 | (1 1) (1 1)
  2228. 03:07:05.742 -> 14 28 | B1->B0 | 1111 2323 | 1 1 | (1 1) (1 1)
  2229. 03:07:05.742 -> 15 0 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  2230. 03:07:05.742 -> 15 4 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  2231. 03:07:05.742 -> 15 8 | B1->B0 | 1111 2222 | 1 1 | (1 1) (1 1)
  2232. 03:07:05.807 -> 15 12 | B1->B0 | 2323 2222 | 0 0 | (0 0) (1 1)
  2233. 03:07:05.807 -> 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  2234. 03:07:05.807 -> 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  2235. 03:07:05.807 -> 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  2236. 03:07:05.807 -> 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  2237. 03:07:05.807 -> 16 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
  2238. 03:07:05.807 -> 16 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2239. 03:07:05.807 -> 16 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2240. 03:07:05.807 -> 16 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
  2241. 03:07:05.807 -> 16 16 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
  2242. 03:07:05.807 -> 16 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2243. 03:07:05.807 -> 16 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2244. 03:07:05.807 -> 16 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2245. 03:07:05.807 -> 17 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2246. 03:07:05.807 -> 17 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2247. 03:07:05.871 -> 17 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2248. 03:07:05.871 -> 17 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2249. 03:07:05.871 -> 17 16 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2250. 03:07:05.871 -> 17 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2251. 03:07:05.871 -> 17 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2252. 03:07:05.871 -> 17 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2253. 03:07:05.871 -> 18 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2254. 03:07:05.871 -> 18 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2255. 03:07:05.871 -> 18 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  2256. 03:07:05.871 -> 18 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
  2257. 03:07:05.871 -> 18 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
  2258. 03:07:05.871 -> 18 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2259. 03:07:05.871 -> 18 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2260. 03:07:05.871 -> 18 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2261. 03:07:05.871 -> 19 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2262. 03:07:05.871 -> 19 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2263. 03:07:05.936 -> 19 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2264. 03:07:05.936 -> 19 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2265. 03:07:05.936 -> 19 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2266. 03:07:05.936 -> 19 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  2267. 03:07:05.936 -> best dqsien dly found for B0: (18, 14)
  2268. 03:07:05.936 -> best dqsien dly found for B1: (18, 14)
  2269. 03:07:05.936 -> best DQS0 dly(UI, PI) = (18, 14)
  2270. 03:07:05.936 -> best DQS1 dly(UI, PI) = (18, 14)
  2271. 03:07:05.936 ->
  2272. 03:07:05.936 -> [Gating] SW calibration Done
  2273. 03:07:05.936 -> [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  2274. 03:07:05.936 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2275. 03:07:05.936 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2276. 03:07:05.936 -> ===============================================================================
  2277. 03:07:05.936 -> Start DQ dly to find pass range UseTestEngine =0
  2278. 03:07:06.008 -> UseTestEngine: 0
  2279. 03:07:06.008 -> RX Vref Scan: 0
  2280. 03:07:06.008 ->
  2281. 03:07:06.008 -> RX Vref 0 -> 0, step: 1
  2282. 03:07:06.008 ->
  2283. 03:07:06.008 -> RX Delay -48 -> 63, step: 4
  2284. 03:07:06.008 -> -48, [0] xxxxxxxx xxxxxxxx [MSB]
  2285. 03:07:06.008 -> -44, [0] xxxxxxxx xxxxxxxx [MSB]
  2286. 03:07:06.008 -> -40, [0] xxxxxxxx xxxxxxxx [MSB]
  2287. 03:07:06.008 -> -36, [0] xxxxxxxx xxxxxxxx [MSB]
  2288. 03:07:06.008 -> -32, [0] xxxxxxxx xxxxxxxx [MSB]
  2289. 03:07:06.008 -> -28, [0] xxxxxxxx xxxxxxxx [MSB]
  2290. 03:07:06.008 -> -24, [0] xxxxxxxx xxxxxxxx [MSB]
  2291. 03:07:06.008 -> -20, [0] xxxxxxxx xxxxxxxx [MSB]
  2292. 03:07:06.008 -> -16, [0] xxxxxxxx xxxxxxxx [MSB]
  2293. 03:07:06.008 -> -12, [0] xxxxxxxx xxxxxxxx [MSB]
  2294. 03:07:06.008 -> -8, [0] xxxxxxxx xxxxxxxx [MSB]
  2295. 03:07:06.008 -> -4, [0] xxxxxxox xxxxxxxx [MSB]
  2296. 03:07:06.008 -> 0, [0] xxoxoxox xxoxxxxx [MSB]
  2297. 03:07:06.008 -> 4, [0] oxoooooo oxoxoooo [MSB]
  2298. 03:07:06.008 -> 8, [0] oooooooo oooooooo [MSB]
  2299. 03:07:06.008 -> 12, [0] oooooooo oooooooo [MSB]
  2300. 03:07:06.008 -> 16, [0] oooooooo oooooooo [MSB]
  2301. 03:07:06.008 -> 20, [0] oooooooo oooooooo [MSB]
  2302. 03:07:06.008 -> 24, [0] oooooooo oooooooo [MSB]
  2303. 03:07:06.008 -> 28, [0] oooooooo oooooooo [MSB]
  2304. 03:07:06.008 -> 32, [0] oooooooo oooooooo [MSB]
  2305. 03:07:06.008 -> 36, [0] ooooooxo oooooooo [MSB]
  2306. 03:07:06.065 -> 40, [0] ooxoxoxo ooooxoxo [MSB]
  2307. 03:07:06.065 -> 44, [0] xxxxxxxx xxxxxxxx [MSB]
  2308. 03:07:06.065 -> RX Vref B0= 0, Window Sum 316, worse bit 1, min window 36
  2309. 03:07:06.065 -> iDelay=44, Bit 0, Center 23 (4 ~ 43) 40
  2310. 03:07:06.065 -> iDelay=44, Bit 1, Center 25 (8 ~ 43) 36
  2311. 03:07:06.065 -> iDelay=44, Bit 2, Center 19 (0 ~ 39) 40
  2312. 03:07:06.065 -> iDelay=44, Bit 3, Center 23 (4 ~ 43) 40
  2313. 03:07:06.065 -> iDelay=44, Bit 4, Center 19 (0 ~ 39) 40
  2314. 03:07:06.065 -> iDelay=44, Bit 5, Center 23 (4 ~ 43) 40
  2315. 03:07:06.065 -> iDelay=44, Bit 6, Center 15 (-4 ~ 35) 40
  2316. 03:07:06.065 -> iDelay=44, Bit 7, Center 23 (4 ~ 43) 40
  2317. 03:07:06.065 -> RX Vref B1= 0, Window Sum 308, worse bit 9, min window 36
  2318. 03:07:06.065 -> iDelay=44, Bit 8, Center 23 (4 ~ 43) 40
  2319. 03:07:06.065 -> iDelay=44, Bit 9, Center 25 (8 ~ 43) 36
  2320. 03:07:06.065 -> iDelay=44, Bit 10, Center 21 (0 ~ 43) 44
  2321. 03:07:06.133 -> iDelay=44, Bit 11, Center 25 (8 ~ 43) 36
  2322. 03:07:06.133 -> iDelay=44, Bit 12, Center 21 (4 ~ 39) 36
  2323. 03:07:06.133 -> iDelay=44, Bit 13, Center 23 (4 ~ 43) 40
  2324. 03:07:06.133 -> iDelay=44, Bit 14, Center 21 (4 ~ 39) 36
  2325. 03:07:06.133 -> iDelay=44, Bit 15, Center 23 (4 ~ 43) 40
  2326. 03:07:06.133 -> [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  2327. 03:07:06.133 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2328. 03:07:06.133 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2329. 03:07:06.133 -> ===============================================================================
  2330. 03:07:06.133 -> DQS Delay:
  2331. 03:07:06.133 -> DQS0 = 0, DQS1 = 0
  2332. 03:07:06.133 -> DQM Delay:
  2333. 03:07:06.133 -> DQM0 = 21, DQM1 = 22
  2334. 03:07:06.133 -> DQ Delay:
  2335. 03:07:06.133 -> DQ0 =23, DQ1 =25, DQ2 =19, DQ3 =23
  2336. 03:07:06.133 -> DQ4 =19, DQ5 =23, DQ6 =15, DQ7 =23
  2337. 03:07:06.133 -> DQ8 =23, DQ9 =25, DQ10 =21, DQ11 =25
  2338. 03:07:06.133 -> DQ12 =21, DQ13 =23, DQ14 =21, DQ15 =23
  2339. 03:07:06.133 ->
  2340. 03:07:06.133 ->
  2341. 03:07:06.133 -> ===============================================================================
  2342. 03:07:06.195 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2343. 03:07:06.195 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2344. 03:07:06.195 -> ===============================================================================
  2345. 03:07:06.195 -> [TxWindowPerbitCal] caltype:2 Autok:0
  2346. 03:07:06.195 ->
  2347. 03:07:06.195 ->
  2348. 03:07:06.195 -> TX Vref Scan disable
  2349. 03:07:06.195 -> 810 |3 0 42|[0] xxoxxxxx xxxxxxxx [MSB]
  2350. 03:07:06.195 -> 812 |3 0 44|[0] xxoxxxox xxxxoxxx [MSB]
  2351. 03:07:06.195 -> 814 |3 0 46|[0] xxoxxxox xxxxoxxx [MSB]
  2352. 03:07:06.195 -> 816 |3 0 48|[0] xxoxxxox xxxxoxxo [MSB]
  2353. 03:07:06.195 -> 818 |3 0 50|[0] oooooooo oxoooooo [MSB]
  2354. 03:07:06.195 -> 830 |3 0 62|[0] ooooooxo oooooooo [MSB]
  2355. 03:07:06.195 -> 832 |3 2 0|[0] ooooooxo oooooooo [MSB]
  2356. 03:07:06.195 -> 834 |3 2 2|[0] xoxoxoxo oooooooo [MSB]
  2357. 03:07:06.195 -> 836 |3 2 4|[0] xoxxxoxo ooxoooxo [MSB]
  2358. 03:07:06.195 -> 838 |3 2 6|[0] xxxxxxxx xoxxxoxo [MSB]
  2359. 03:07:06.195 -> 840 |3 2 8|[0] xxxxxxxx xoxxxxxx [MSB]
  2360. 03:07:06.195 -> 842 |3 2 10|[0] xxxxxxxx xxxxxxxx [MSB]
  2361. 03:07:06.247 -> TX Bit0 (818~832) 16 825, Bit8 (818~836) 20 827,
  2362. 03:07:06.247 -> TX Bit1 (818~836) 20 827, Bit9 (820~840) 22 830,
  2363. 03:07:06.247 -> TX Bit2 (810~832) 24 821, Bit10 (818~834) 18 826,
  2364. 03:07:06.247 -> TX Bit3 (818~834) 18 826, Bit11 (818~836) 20 827,
  2365. 03:07:06.247 -> TX Bit4 (818~832) 16 825, Bit12 (812~836) 26 824,
  2366. 03:07:06.247 -> TX Bit5 (818~836) 20 827, Bit13 (818~838) 22 828,
  2367. 03:07:06.247 -> TX Bit6 (812~828) 18 820, Bit14 (818~834) 18 826,
  2368. 03:07:06.247 -> TX Bit7 (818~836) 20 827, Bit15 (816~838) 24 827,
  2369. 03:07:06.247 ->
  2370. 03:07:06.247 -> == TX Byte 0 ==
  2371. 03:07:06.247 -> Update DQ dly =823 (3 ,0, 55) DQ OEN =(2 ,5)
  2372. 03:07:06.247 -> Update DQM dly =823 (3 ,0, 55) DQM OEN =(2 ,5)
  2373. 03:07:06.247 ->
  2374. 03:07:06.247 -> == TX Byte 1 ==
  2375. 03:07:06.325 -> Update DQ dly =827 (3 ,0, 59) DQ OEN =(2 ,5)
  2376. 03:07:06.325 -> Update DQM dly =827 (3 ,0, 59) DQM OEN =(2 ,5)
  2377. 03:07:06.325 ->
  2378. 03:07:06.325 -> ===============================================================================
  2379. 03:07:06.325 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2380. 03:07:06.325 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2381. 03:07:06.325 -> ===============================================================================
  2382. 03:07:06.325 -> [TxWindowPerbitCal] caltype:0 Autok:0
  2383. 03:07:06.325 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 3
  2384. 03:07:06.325 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 5
  2385. 03:07:06.325 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 7
  2386. 03:07:06.325 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 9
  2387. 03:07:06.396 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 11
  2388. 03:07:06.396 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 13
  2389. 03:07:06.396 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 15
  2390. 03:07:06.396 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 17
  2391. 03:07:06.396 -> TX Vref=3, minBit 6, minWin=15, winSum=284
  2392. 03:07:06.396 -> TX Vref=5, minBit 6, minWin=15, winSum=291
  2393. 03:07:06.396 -> TX Vref=7, minBit 3, minWin=16, winSum=305
  2394. 03:07:06.434 -> TX Vref=9, minBit 3, minWin=17, winSum=314
  2395. 03:07:06.434 -> TX Vref=11, minBit 3, minWin=17, winSum=324
  2396. 03:07:06.434 -> TX Vref=13, minBit 1, minWin=18, winSum=334
  2397. 03:07:06.434 -> TX Vref=15, minBit 3, minWin=18, winSum=342
  2398. 03:07:06.434 -> TX Vref=17, minBit 3, minWin=18, winSum=350
  2399. 03:07:06.434 -> [TxChooseVref] Worse bit 3, Min win 18, Win sum 350, Final Vref 17
  2400. 03:07:06.434 -> [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 17
  2401. 03:07:06.434 ->
  2402. 03:07:06.434 -> Final TX Range 1 Vref 17
  2403. 03:07:06.496 ->
  2404. 03:07:06.496 -> ===============================================================================
  2405. 03:07:06.496 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2406. 03:07:06.496 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2407. 03:07:06.496 -> ===============================================================================
  2408. 03:07:06.496 -> [TxWindowPerbitCal] caltype:0 Autok:0
  2409. 03:07:06.496 ->
  2410. 03:07:06.496 ->
  2411. 03:07:06.496 -> TX Vref Scan disable
  2412. 03:07:06.496 -> 810 |3 0 42|[0] xxxxxxxx xxxxxxxx [MSB]
  2413. 03:07:06.496 -> 811 |3 0 43|[0] xxxxxxxx xxxxxxxx [MSB]
  2414. 03:07:06.496 -> 812 |3 0 44|[0] xxoxxxox xxxxxxxx [MSB]
  2415. 03:07:06.496 -> 813 |3 0 45|[0] xxoxxxox xxxxoxxx [MSB]
  2416. 03:07:06.496 -> 814 |3 0 46|[0] xxoxxxox xxxxoxxx [MSB]
  2417. 03:07:06.496 -> 815 |3 0 47|[0] oxoxoxox xxxxoxxo [MSB]
  2418. 03:07:06.496 -> 816 |3 0 48|[0] oxoxoxoo xxoooxxo [MSB]
  2419. 03:07:06.496 -> 817 |3 0 49|[0] oxoxoooo oxoooooo [MSB]
  2420. 03:07:06.496 -> 834 |3 2 2|[0] ooxoxoxo oooooooo [MSB]
  2421. 03:07:06.496 -> 835 |3 2 3|[0] xoxoxoxo oooooooo [MSB]
  2422. 03:07:06.559 -> 836 |3 2 4|[0] xoxxxoxo oooooooo [MSB]
  2423. 03:07:06.559 -> 837 |3 2 5|[0] xoxxxoxo ooxoooxo [MSB]
  2424. 03:07:06.559 -> 838 |3 2 6|[0] xxxxxoxo ooxoooxo [MSB]
  2425. 03:07:06.559 -> 839 |3 2 7|[0] xxxxxxxx xoxoxoxo [MSB]
  2426. 03:07:06.559 -> 840 |3 2 8|[0] xxxxxxxx xoxxxoxx [MSB]
  2427. 03:07:06.559 -> 841 |3 2 9|[0] xxxxxxxx xxxxxxxx [MSB]
  2428. 03:07:06.559 -> TX Bit0 (815~834) 20 824, Bit8 (817~838) 22 827,
  2429. 03:07:06.559 -> TX Bit1 (818~837) 20 827, Bit9 (818~840) 23 829,
  2430. 03:07:06.559 -> TX Bit2 (812~833) 22 822, Bit10 (816~836) 21 826,
  2431. 03:07:06.559 -> TX Bit3 (818~835) 18 826, Bit11 (816~839) 24 827,
  2432. 03:07:06.559 -> TX Bit4 (815~833) 19 824, Bit12 (813~838) 26 825,
  2433. 03:07:06.559 -> TX Bit5 (817~838) 22 827, Bit13 (817~840) 24 828,
  2434. 03:07:06.559 -> TX Bit6 (812~833) 22 822, Bit14 (817~836) 20 826,
  2435. 03:07:06.559 -> TX Bit7 (816~838) 23 827, Bit15 (815~839) 25 827,
  2436. 03:07:06.559 ->
  2437. 03:07:06.559 -> [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =704/100 ps
  2438. 03:07:06.606 -> == TX Byte 0 ==
  2439. 03:07:06.606 -> u2DelayCellOfst[0]=2 cells (2 PI)
  2440. 03:07:06.606 -> u2DelayCellOfst[1]=6 cells (5 PI)
  2441. 03:07:06.606 -> u2DelayCellOfst[2]=0 cells (0 PI)
  2442. 03:07:06.606 -> u2DelayCellOfst[3]=5 cells (4 PI)
  2443. 03:07:06.606 -> u2DelayCellOfst[4]=2 cells (2 PI)
  2444. 03:07:06.606 -> u2DelayCellOfst[5]=6 cells (5 PI)
  2445. 03:07:06.606 -> u2DelayCellOfst[6]=0 cells (0 PI)
  2446. 03:07:06.606 -> u2DelayCellOfst[7]=6 cells (5 PI)
  2447. 03:07:06.606 -> Update DQ dly =822 (3 ,0, 54) DQ OEN =(2 ,5)
  2448. 03:07:06.606 -> Update DQM dly =824 (3 ,0, 56) DQM OEN =(2 ,5)
  2449. 03:07:06.606 ->
  2450. 03:07:06.606 -> == TX Byte 1 ==
  2451. 03:07:06.606 -> u2DelayCellOfst[8]=2 cells (2 PI)
  2452. 03:07:06.606 -> u2DelayCellOfst[9]=5 cells (4 PI)
  2453. 03:07:06.668 -> u2DelayCellOfst[10]=1 cells (1 PI)
  2454. 03:07:06.668 -> u2DelayCellOfst[11]=2 cells (2 PI)
  2455. 03:07:06.668 -> u2DelayCellOfst[12]=0 cells (0 PI)
  2456. 03:07:06.668 -> u2DelayCellOfst[13]=4 cells (3 PI)
  2457. 03:07:06.668 -> u2DelayCellOfst[14]=1 cells (1 PI)
  2458. 03:07:06.668 -> u2DelayCellOfst[15]=2 cells (2 PI)
  2459. 03:07:06.668 -> Update DQ dly =825 (3 ,0, 57) DQ OEN =(2 ,5)
  2460. 03:07:06.668 -> Update DQM dly =827 (3 ,0, 59) DQM OEN =(2 ,5)
  2461. 03:07:06.668 ->
  2462. 03:07:06.668 -> ===============================================================================
  2463. 03:07:06.668 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2464. 03:07:06.668 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2465. 03:07:06.668 -> ===============================================================================
  2466. 03:07:06.668 -> DATLAT Default: 0xc
  2467. 03:07:06.668 -> 0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0xbest_step = 11
  2468. 03:07:06.668 ->
  2469. 03:07:06.668 -> ===============================================================================
  2470. 03:07:06.739 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2471. 03:07:06.739 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2472. 03:07:06.739 -> ===============================================================================
  2473. 03:07:06.739 -> Start DQ dly to find pass range UseTestEngine =1
  2474. 03:07:06.739 -> UseTestEngine: 1
  2475. 03:07:06.739 -> RX Vref Scan: 1
  2476. 03:07:06.739 ->
  2477. 03:07:06.739 -> Set Vref Range= 9 -> 21
  2478. 03:07:06.739 ->
  2479. 03:07:06.739 -> RX Vref 9 -> 21, step: 1
  2480. 03:07:06.739 ->
  2481. 03:07:06.739 -> RX Delay -14 -> 63, step: 2
  2482. 03:07:06.739 ->
  2483. 03:07:06.739 -> Set Vref, RX VrefLevel [Byte0]: 9 [Byte1]: 9
  2484. 03:07:06.739 -> RX Vref B0= 9, Window Sum 228, worse bit 2, min window 26
  2485. 03:07:06.739 -> RX Vref B1= 9, Window Sum 216, worse bit 10, min window 22
  2486. 03:07:06.739 ->
  2487. 03:07:06.739 -> Set Vref, RX VrefLevel [Byte0]: 10 [Byte1]: 10
  2488. 03:07:06.739 -> RX Vref B0= 10, Window Sum 238, worse bit 2, min window 26
  2489. 03:07:06.739 -> RX Vref B1= 10, Window Sum 218, worse bit 10, min window 22
  2490. 03:07:06.739 ->
  2491. 03:07:06.739 -> Set Vref, RX VrefLevel [Byte0]: 11 [Byte1]: 11
  2492. 03:07:06.793 -> RX Vref B0= 11, Window Sum 248, worse bit 4, min window 28
  2493. 03:07:06.793 -> RX Vref B1= 11, Window Sum 234, worse bit 10, min window 26
  2494. 03:07:06.793 ->
  2495. 03:07:06.793 -> Set Vref, RX VrefLevel [Byte0]: 12 [Byte1]: 12
  2496. 03:07:06.793 -> RX Vref B0= 12, Window Sum 254, worse bit 4, min window 28
  2497. 03:07:06.793 -> RX Vref B1= 12, Window Sum 242, worse bit 10, min window 26
  2498. 03:07:06.793 ->
  2499. 03:07:06.793 -> Set Vref, RX VrefLevel [Byte0]: 13 [Byte1]: 13
  2500. 03:07:06.793 -> RX Vref B0= 13, Window Sum 268, worse bit 4, min window 30
  2501. 03:07:06.793 -> RX Vref B1= 13, Window Sum 252, worse bit 10, min window 28
  2502. 03:07:06.793 ->
  2503. 03:07:06.793 -> Set Vref, RX VrefLevel [Byte0]: 14 [Byte1]: 14
  2504. 03:07:06.841 -> RX Vref B0= 14, Window Sum 270, worse bit 2, min window 32
  2505. 03:07:06.841 -> RX Vref B1= 14, Window Sum 262, worse bit 10, min window 28
  2506. 03:07:06.841 ->
  2507. 03:07:06.841 -> Set Vref, RX VrefLevel [Byte0]: 15 [Byte1]: 15
  2508. 03:07:06.841 -> RX Vref B0= 15, Window Sum 276, worse bit 2, min window 32
  2509. 03:07:06.841 -> RX Vref B1= 15, Window Sum 268, worse bit 10, min window 30
  2510. 03:07:06.841 ->
  2511. 03:07:06.841 -> Set Vref, RX VrefLevel [Byte0]: 16 [Byte1]: 16
  2512. 03:07:06.841 -> RX Vref B0= 16, Window Sum 284, worse bit 2, min window 34
  2513. 03:07:06.841 -> RX Vref B1= 16, Window Sum 272, worse bit 10, min window 32
  2514. 03:07:06.841 ->
  2515. 03:07:06.841 -> Set Vref, RX VrefLevel [Byte0]: 17 [Byte1]: 17
  2516. 03:07:06.914 -> RX Vref B0= 17, Window Sum 286, worse bit 2, min window 34
  2517. 03:07:06.914 -> RX Vref B1= 17, Window Sum 282, worse bit 10, min window 32
  2518. 03:07:06.914 ->
  2519. 03:07:06.914 -> Set Vref, RX VrefLevel [Byte0]: 18 [Byte1]: 18
  2520. 03:07:06.914 ->
  2521. 03:07:06.914 -> Set Vref, RX VrefLevel [Byte0]: 19 [Byte1]: 19
  2522. 03:07:06.914 ->
  2523. 03:07:06.914 -> Set Vref, RX VrefLevel [Byte0]: 20 [Byte1]: 20
  2524. 03:07:06.914 ->
  2525. 03:07:06.914 -> Set Vref, RX VrefLevel [Byte0]: 21 [Byte1]: 21
  2526. 03:07:06.914 ->
  2527. 03:07:06.914 -> Final RX Vref Byte 0 = 17 to rank0 to rank1
  2528. 03:07:06.914 ->
  2529. 03:07:06.914 -> Final RX Vref Byte 1 = 17 to rank0 to rank1
  2530. 03:07:06.914 -> ===============================================================================
  2531. 03:07:06.914 -> Dram Type= 4, Freq= 1600, CH_0, rank 0
  2532. 03:07:06.914 -> fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  2533. 03:07:06.914 -> ===============================================================================
  2534. 03:07:06.914 -> DQS Delay:
  2535. 03:07:06.914 -> DQS0 = 0, DQS1 = 0
  2536. 03:07:06.914 -> DQM Delay:
  2537. 03:07:06.965 -> DQM0 = 21, DQM1 = 23
  2538. 03:07:06.965 -> DQ Delay:
  2539. 03:07:06.965 -> DQ0 =23, DQ1 =27, DQ2 =18, DQ3 =25
  2540. 03:07:06.965 -> DQ4 =20, DQ5 =24, DQ6 =15, DQ7 =23
  2541. 03:07:06.965 -> DQ8 =23, DQ9 =25, DQ10 =21, DQ11 =26
  2542. 03:07:06.965 -> DQ12 =23, DQ13 =25, DQ14 =22, DQ15 =24
  2543. 03:07:06.965 ->
  2544. 03:07:06.965 ->
  2545. 03:07:06.965 -> [DualRankRxdatlatCal] RK0: 11, RK1: 0, Final_Datlat 11
  2546. 03:07:06.965 ->
  2547. 03:07:06.965 ->
  2548. 03:07:06.965 -> [Calibration Summary] Freqency 1600
  2549. 03:07:06.965 -> CH 0, Rank 0
  2550. 03:07:06.965 -> SW Impedance : PASS
  2551. 03:07:06.965 -> DUTY Scan : NO K
  2552. 03:07:06.965 -> ZQ Calibration : PASS
  2553. 03:07:06.965 -> Jitter Meter : NO K
  2554. 03:07:06.965 -> CBT Training : NO K
  2555. 03:07:06.965 -> Write leveling : PASS
  2556. 03:07:06.965 -> RX DQS gating : PASS
  2557. 03:07:06.965 -> RX DQ/DQS(RDDQC) : PASS
  2558. 03:07:06.965 -> TX DQ/DQS : PASS
  2559. 03:07:06.965 -> RX DATLAT : PASS
  2560. 03:07:06.965 -> RX DQ/DQS(Engine): PASS
  2561. 03:07:06.965 -> TX OE : NO K
  2562. 03:07:06.965 -> All Pass.
  2563. 03:07:06.965 ->
  2564. 03:07:06.965 -> TX_TRACKING: OFF
  2565. 03:07:06.965 -> [AUTO] write start address pass, BASE_ADDR : 0x0, OFFSET : 0x3
  2566. 03:07:07.028 -> [AUTO] Detect DramSize: 0x8000000
  2567. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x8000000, OFFSET : 0x3
  2568. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  2569. 03:07:07.028 ->
  2570. 03:07:07.028 ->
  2571. 03:07:07.028 -> [AUTO] Detect DramSize: 0x10000000
  2572. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x10000000, OFFSET : 0x3
  2573. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  2574. 03:07:07.028 ->
  2575. 03:07:07.028 ->
  2576. 03:07:07.028 -> [AUTO] Detect DramSize: 0x20000000
  2577. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x20000000, OFFSET : 0x3
  2578. 03:07:07.028 -> [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  2579. 03:07:07.028 -> [AUTO] TA2 read check fail, u4err_value = 65535, 3
  2580. 03:07:07.028 -> [AUTO] Detect full size
  2581. 03:07:07.028 ->
  2582. 03:07:07.028 ->
  2583. 03:07:07.028 -> u4DramSize 0x20000000
  2584. 03:07:07.028 -> NOTICE: EMI: Detected DRAM size: 512MB
  2585. 03:07:07.028 ->
  2586. 03:07:07.028 -> [MEM_TEST] 02: After DFS, before run time config
  2587. 03:07:07.028 -> [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  2588. 03:07:07.075 ->
  2589. 03:07:07.075 -> [TA2_TEST]
  2590. 03:07:07.075 -> === TA2 HW
  2591. 03:07:07.075 -> === OFFSET:0x200
  2592. 03:07:07.075 -> TA2 PAT: 3
  2593. 03:07:07.075 ->
  2594. 03:07:07.075 -> TA2 Trigger Write
  2595. 03:07:07.075 -> HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
  2596. 03:07:07.075 -> [DramcRunTimeConfig]: ON
  2597. 03:07:07.075 -> PHYPLL
  2598. 03:07:07.075 -> DPM_CONTROL_AFTERK: ON
  2599. 03:07:07.075 -> PER_BANK_REFRESH: OFF
  2600. 03:07:07.075 -> REFRESH_OVERHEAD_REDUCTION: ON
  2601. 03:07:07.075 -> CMD_PICG_NEW_MODE: OFF
  2602. 03:07:07.075 -> TX_TRACKING: OFF
  2603. 03:07:07.075 -> RDSEL_TRACKING: OFF
  2604. 03:07:07.075 -> DQS Precalculation for DVFS: OFF
  2605. 03:07:07.075 -> RX_TRACKING: OFF
  2606. 03:07:07.075 -> DDR_HW_GATING DBG: ON
  2607. 03:07:07.075 -> DDR_ZQCS_ENABLE: ON
  2608. 03:07:07.075 -> RX_PICG_NEW_MODE: ON
  2609. 03:07:07.075 -> TX_PICG_NEW_MODE: ON
  2610. 03:07:07.075 -> ENABLE_RX_DCM_DPHY: ON
  2611. 03:07:07.075 -> LOWPOWER_GOLDEN_SETTINGS(DCM): ON
  2612. 03:07:07.075 -> DUMMY_READ_FOR_TRACKING: OFF
  2613. 03:07:07.075 -> !!! SPM_CONTROL_AFTERK: OFF
  2614. 03:07:07.138 -> !!! SPM could not control APHY
  2615. 03:07:07.138 -> IMPEDANCE_TRACKING: OFF
  2616. 03:07:07.138 -> HW_SAVE_FOR_SR: OFF
  2617. 03:07:07.138 -> CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
  2618. 03:07:07.138 -> PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
  2619. 03:07:07.138 -> Read ODT Tracking: OFF
  2620. 03:07:07.138 -> Refresh Rate DeBounce: OFF
  2621. 03:07:07.138 -> DFS_NO_QUEUE_FLUSH: OFF
  2622. 03:07:07.138 -> DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
  2623. 03:07:07.138 -> ENABLE_DFS_RUNTIME_MRW: OFF
  2624. 03:07:07.138 -> DDR_RESERVE_NEW_MODE: ON
  2625. 03:07:07.138 -> =========================
  2626. 03:07:07.138 ->
  2627. 03:07:07.138 -> [MEM_TEST] 03: After run time config
  2628. 03:07:07.138 -> [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  2629. 03:07:07.138 ->
  2630. 03:07:07.138 -> [TA2_TEST]
  2631. 03:07:07.138 -> === TA2 HW
  2632. 03:07:07.138 -> === OFFSET:0x200
  2633. 03:07:07.138 ->
  2634. 03:07:07.138 -> TA2 Trigger Write
  2635. 03:07:07.138 -> HW channel(0) Rank(0), TA2 pass, pass_cnt:2, err_cnt:0
  2636. 03:07:07.138 ->
  2637. 03:07:07.138 -> Init_DRAM:2480: init PCDDR4 dram End
  2638. 03:07:07.138 -> EMI: complex real chip dram calibration
  2639. 03:07:07.200 -> Verify pattern 1 (0x00~0xff)...
  2640. 03:07:07.200 -> EMI: mem8_base[0] = pattern8 = 0x0
  2641. 03:07:07.200 -> Verify pattern 2 (0x00~0xffff)...
  2642. 03:07:07.200 -> EMI: mem16_base[0] = pattern16 = 0x0
  2643. 03:07:07.200 -> Verify pattern 3 (0x00~0xffffffff)...
  2644. 03:07:07.200 -> EMI: mem32_base[0] = pattern32 = 0x0
  2645. 03:07:07.200 -> NOTICE: EMI: complex R/W mem test passed
  2646. 03:07:07.200 ->
  2647. 03:07:07.200 -> drm_dram_reserved: MTK_DRM_MODE(22000000)
  2648. 03:07:07.200 ->
  2649. 03:07:07.200 -> NOTICE: SPI_NAND parses attributes from parameter page.
  2650. 03:07:07.200 -> NOTICE: SPI_NAND Detected ID 0x0
  2651. 03:07:07.200 -> NOTICE: Page size 2048, Block size 131072, size 134217728
  2652. 03:07:07.200 -> NOTICE: Initializing NMBM ...
  2653. 03:07:07.200 -> NOTICE: Signature found at block 1023 [0x07fe0000]
  2654. 03:07:07.263 -> NOTICE: First info table with writecount 0 found in block 960
  2655. 03:07:07.263 -> NOTICE: Second info table with writecount 0 found in block 963
  2656. 03:07:07.263 -> NOTICE: NMBM has been successfully attached in read-only mode
  2657. 03:07:07.263 -> INFO: BL2: Loading image id 3
  2658. 03:07:07.263 -> INFO: Loading image id=3 at address 0x42000000
  2659. 03:07:07.263 -> INFO: Image id=3 loaded: 0x42000000 - 0x42009061
  2660. 03:07:07.325 -> INFO: BL2: Loading image id 5
  2661. 03:07:07.325 -> INFO: Loading image id=5 at address 0x42000000
  2662. 03:07:07.608 -> INFO: Image id=5 loaded: 0x42000000 - 0x420ae288
  2663. 03:07:07.784 -> NOTICE: BL2: Booting BL31
  2664. 03:07:07.784 -> INFO: Entry point address = 0x43001000
  2665. 03:07:07.784 -> INFO: SPSR = 0x3cd
  2666. 03:07:07.784 -> INFO: Total CPU count: 4
  2667. 03:07:07.784 -> INFO: MCUSYS: Disable 512KB L2C shared SRAM
  2668. 03:07:07.818 -> INFO: check_ver = 0
  2669. 03:07:07.818 -> INFO: Secondary bootloader is AArch64
  2670. 03:07:07.818 -> INFO: GICv3 without legacy support detected.
  2671. 03:07:07.818 -> INFO: ARM GICv3 driver initialized in EL3
  2672. 03:07:07.818 -> INFO: Maximum SPI INTID supported: 671
  2673. 03:07:07.818 -> INFO: SPMC: Changed to SPMC mode
  2674. 03:07:07.818 -> NOTICE: BL31: v2.6(release):82a3fbe10a-dirty
  2675. 03:07:07.818 -> NOTICE: BL31: Built : 16:56:29, Mar 29 2022
  2676. 03:07:07.855 -> INFO: [MPU](Region0)sa:0x0300, ea:0x0302
  2677. 03:07:07.855 -> INFO: [MPU](Region0)apc0:0x80b6db69, apc1:0x00b6db6d
  2678. 03:07:07.855 -> INFO: [MPU](Region1)sa:0x0000, ea:0x0000
  2679. 03:07:07.855 -> INFO: [MPU](Region1)apc0:0x00000000, apc1:0x00000000
  2680. 03:07:07.855 -> INFO: [MPU](Region2)sa:0x0000, ea:0x0000
  2681. 03:07:07.855 -> INFO: [MPU](Region2)apc0:0x00000000, apc1:0x00000000
  2682. 03:07:07.855 -> INFO: [MPU](Region3)sa:0x0000, ea:0x0000
  2683. 03:07:07.855 -> INFO: [MPU](Region3)apc0:0x00000000, apc1:0x00000000
  2684. 03:07:07.909 -> INFO: [DEVAPC] devapc_init done
  2685. 03:07:07.909 -> INFO: BL31: Initializing runtime services
  2686. 03:07:07.909 -> INFO: BL31: Preparing for EL3 exit to normal world
  2687. 03:07:07.909 -> INFO: Entry point address = 0x41e00000
  2688. 03:07:07.909 -> INFO: SPSR = 0x3c9
  2689. 03:07:07.982 -> In: serial@11002000
  2690. 03:07:07.982 -> Out: serial@11002000
  2691. 03:07:07.982 -> Err: serial@11002000
  2692. 03:07:07.982 -> Net: eth0: ethernet@15100000
  2693. 03:07:09.000 -> [?25l *** U-Boot Boot Menu *** Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit 1. Startup system (Default) 2. Startup firmware0 3. Startup firmware1 4. Upgrade firmware 5. Upgrade ATF BL2 6. Upgrade ATF FIP 7. Upgrade single image 8. Load image 0. U-Boot console Hit any key to stop autoboot: 5  4  3  2  1 
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