Guest User

Untitled

a guest
Jul 23rd, 2020
69
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 61.74 KB | None | 0 0
  1.  
  2. ****** Vivado v2019.2 (64-bit)
  3. **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
  4. **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
  5. ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  6.  
  7. source top.tcl
  8. # create_project -force -name top -part xc7z020clg400-1
  9. # add_files top.v
  10. # read_xdc top.xdc
  11. # synth_design -top top
  12. Command: synth_design -top top
  13. Starting synth_design
  14. Using part: xc7z020clg400-1
  15. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
  16. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
  17. INFO: [Device 21-403] Loading part xc7z020clg400-1
  18. INFO: Launching helper process for spawning children vivado processes
  19. INFO: Helper process launched with PID 91228
  20. ---------------------------------------------------------------------------------
  21. Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1997.309 ; gain = 201.676 ; free physical = 5003 ; free virtual = 6298
  22. ---------------------------------------------------------------------------------
  23. INFO: [Synth 8-6157] synthesizing module 'top' [/home/simpleton/checking_nmigen/build/top.v:65]
  24. INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/simpleton/checking_nmigen/build/top.v:69]
  25. INFO: [Synth 8-6157] synthesizing module 'blink' [/home/simpleton/checking_nmigen/build/top.v:4]
  26. INFO: [Synth 8-6155] done synthesizing module 'blink' (1#1) [/home/simpleton/checking_nmigen/build/top.v:4]
  27. INFO: [Synth 8-6157] synthesizing module 'cd_sync' [/home/simpleton/checking_nmigen/build/top.v:31]
  28. INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78135]
  29. Parameter PROG_USR bound to: FALSE - type: string
  30. Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double
  31. INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (2#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78135]
  32. WARNING: [Synth 8-7023] instance 'U$$0' of module 'STARTUPE2' has 13 connections declared, but only 1 given [/home/simpleton/checking_nmigen/build/top.v:36]
  33. INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1085]
  34. Parameter CE_TYPE bound to: SYNC - type: string
  35. Parameter IS_CE_INVERTED bound to: 1'b0
  36. Parameter IS_I_INVERTED bound to: 1'b0
  37. Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
  38. Parameter STARTUP_SYNC bound to: FALSE - type: string
  39. INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (3#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1085]
  40. INFO: [Synth 8-6155] done synthesizing module 'cd_sync' (4#1) [/home/simpleton/checking_nmigen/build/top.v:31]
  41. INFO: [Synth 8-6157] synthesizing module 'pin_clk125_0' [/home/simpleton/checking_nmigen/build/top.v:46]
  42. INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:32937]
  43. Parameter CAPACITANCE bound to: DONT_CARE - type: string
  44. Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
  45. Parameter IBUF_LOW_PWR bound to: TRUE - type: string
  46. Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
  47. Parameter IOSTANDARD bound to: DEFAULT - type: string
  48. INFO: [Synth 8-6155] done synthesizing module 'IBUF' (5#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:32937]
  49. INFO: [Synth 8-6155] done synthesizing module 'pin_clk125_0' (6#1) [/home/simpleton/checking_nmigen/build/top.v:46]
  50. INFO: [Synth 8-6157] synthesizing module 'pin_led_2' [/home/simpleton/checking_nmigen/build/top.v:56]
  51. INFO: [Synth 8-6157] synthesizing module 'OBUF' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:46211]
  52. Parameter CAPACITANCE bound to: DONT_CARE - type: string
  53. Parameter DRIVE bound to: 12 - type: integer
  54. Parameter IOSTANDARD bound to: DEFAULT - type: string
  55. Parameter SLEW bound to: SLOW - type: string
  56. INFO: [Synth 8-6155] done synthesizing module 'OBUF' (7#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:46211]
  57. INFO: [Synth 8-6155] done synthesizing module 'pin_led_2' (8#1) [/home/simpleton/checking_nmigen/build/top.v:56]
  58. INFO: [Synth 8-6155] done synthesizing module 'top' (9#1) [/home/simpleton/checking_nmigen/build/top.v:65]
  59. ---------------------------------------------------------------------------------
  60. Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2059.062 ; gain = 263.430 ; free physical = 5036 ; free virtual = 6334
  61. ---------------------------------------------------------------------------------
  62.  
  63. Report Check Netlist:
  64. +------+------------------+-------+---------+-------+------------------+
  65. | |Item |Errors |Warnings |Status |Description |
  66. +------+------------------+-------+---------+-------+------------------+
  67. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  68. +------+------------------+-------+---------+-------+------------------+
  69. ---------------------------------------------------------------------------------
  70. Start Handling Custom Attributes
  71. ---------------------------------------------------------------------------------
  72. ---------------------------------------------------------------------------------
  73. Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2062.027 ; gain = 266.395 ; free physical = 5028 ; free virtual = 6327
  74. ---------------------------------------------------------------------------------
  75. ---------------------------------------------------------------------------------
  76. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2062.027 ; gain = 266.395 ; free physical = 5028 ; free virtual = 6327
  77. ---------------------------------------------------------------------------------
  78. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2071.934 ; gain = 0.000 ; free physical = 5020 ; free virtual = 6319
  79. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  80. INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
  81. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  82. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  83. INFO: [Project 1-570] Preparing netlist for logic optimization
  84.  
  85. Processing XDC Constraints
  86. Initializing timing engine
  87. Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
  88. Finished Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
  89. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/simpleton/checking_nmigen/build/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
  90. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
  91. Completed Processing XDC Constraints
  92.  
  93. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2164.762 ; gain = 0.000 ; free physical = 4939 ; free virtual = 6238
  94. INFO: [Project 1-111] Unisim Transformation Summary:
  95. A total of 1 instances were transformed.
  96. BUFGCE => BUFGCTRL: 1 instance
  97.  
  98. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2164.762 ; gain = 0.000 ; free physical = 4939 ; free virtual = 6238
  99. ---------------------------------------------------------------------------------
  100. Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6306
  101. ---------------------------------------------------------------------------------
  102. ---------------------------------------------------------------------------------
  103. Start Loading Part and Timing Information
  104. ---------------------------------------------------------------------------------
  105. Loading part: xc7z020clg400-1
  106. ---------------------------------------------------------------------------------
  107. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6306
  108. ---------------------------------------------------------------------------------
  109. ---------------------------------------------------------------------------------
  110. Start Applying 'set_property' XDC Constraints
  111. ---------------------------------------------------------------------------------
  112. ---------------------------------------------------------------------------------
  113. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6305
  114. ---------------------------------------------------------------------------------
  115. ---------------------------------------------------------------------------------
  116. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4996 ; free virtual = 6297
  117. ---------------------------------------------------------------------------------
  118.  
  119. Report RTL Partitions:
  120. +-+--------------+------------+----------+
  121. | |RTL Partition |Replication |Instances |
  122. +-+--------------+------------+----------+
  123. +-+--------------+------------+----------+
  124. ---------------------------------------------------------------------------------
  125. Start RTL Component Statistics
  126. ---------------------------------------------------------------------------------
  127. Detailed RTL Component Info :
  128. +---XORs :
  129. 2 Input 1 Bit XORs := 1
  130. +---Registers :
  131. 1 Bit Registers := 1
  132. ---------------------------------------------------------------------------------
  133. Finished RTL Component Statistics
  134. ---------------------------------------------------------------------------------
  135. ---------------------------------------------------------------------------------
  136. Start RTL Hierarchical Component Statistics
  137. ---------------------------------------------------------------------------------
  138. Hierarchical RTL Component report
  139. Module blink
  140. Detailed RTL Component Info :
  141. +---XORs :
  142. 2 Input 1 Bit XORs := 1
  143. +---Registers :
  144. 1 Bit Registers := 1
  145. ---------------------------------------------------------------------------------
  146. Finished RTL Hierarchical Component Statistics
  147. ---------------------------------------------------------------------------------
  148. ---------------------------------------------------------------------------------
  149. Start Part Resource Summary
  150. ---------------------------------------------------------------------------------
  151. Part Resources:
  152. DSPs: 220 (col length:60)
  153. BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
  154. ---------------------------------------------------------------------------------
  155. Finished Part Resource Summary
  156. ---------------------------------------------------------------------------------
  157. ---------------------------------------------------------------------------------
  158. Start Cross Boundary and Area Optimization
  159. ---------------------------------------------------------------------------------
  160. Warning: Parallel synthesis criteria is not met
  161. ---------------------------------------------------------------------------------
  162. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4983 ; free virtual = 6287
  163. ---------------------------------------------------------------------------------
  164.  
  165. Report RTL Partitions:
  166. +-+--------------+------------+----------+
  167. | |RTL Partition |Replication |Instances |
  168. +-+--------------+------------+----------+
  169. +-+--------------+------------+----------+
  170. ---------------------------------------------------------------------------------
  171. Start Applying XDC Timing Constraints
  172. ---------------------------------------------------------------------------------
  173. ---------------------------------------------------------------------------------
  174. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
  175. ---------------------------------------------------------------------------------
  176. ---------------------------------------------------------------------------------
  177. Start Timing Optimization
  178. ---------------------------------------------------------------------------------
  179. ---------------------------------------------------------------------------------
  180. Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
  181. ---------------------------------------------------------------------------------
  182.  
  183. Report RTL Partitions:
  184. +-+--------------+------------+----------+
  185. | |RTL Partition |Replication |Instances |
  186. +-+--------------+------------+----------+
  187. +-+--------------+------------+----------+
  188. ---------------------------------------------------------------------------------
  189. Start Technology Mapping
  190. ---------------------------------------------------------------------------------
  191. ---------------------------------------------------------------------------------
  192. Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
  193. ---------------------------------------------------------------------------------
  194.  
  195. Report RTL Partitions:
  196. +-+--------------+------------+----------+
  197. | |RTL Partition |Replication |Instances |
  198. +-+--------------+------------+----------+
  199. +-+--------------+------------+----------+
  200. ---------------------------------------------------------------------------------
  201. Start IO Insertion
  202. ---------------------------------------------------------------------------------
  203. ---------------------------------------------------------------------------------
  204. Start Flattening Before IO Insertion
  205. ---------------------------------------------------------------------------------
  206. ---------------------------------------------------------------------------------
  207. Finished Flattening Before IO Insertion
  208. ---------------------------------------------------------------------------------
  209. ---------------------------------------------------------------------------------
  210. Start Final Netlist Cleanup
  211. ---------------------------------------------------------------------------------
  212. ---------------------------------------------------------------------------------
  213. Finished Final Netlist Cleanup
  214. ---------------------------------------------------------------------------------
  215. ---------------------------------------------------------------------------------
  216. Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  217. ---------------------------------------------------------------------------------
  218. ---------------------------------------------------------------------------------
  219. Start Renaming Generated Instances
  220. ---------------------------------------------------------------------------------
  221. ---------------------------------------------------------------------------------
  222. Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  223. ---------------------------------------------------------------------------------
  224.  
  225. Report RTL Partitions:
  226. +-+--------------+------------+----------+
  227. | |RTL Partition |Replication |Instances |
  228. +-+--------------+------------+----------+
  229. +-+--------------+------------+----------+
  230.  
  231. Report Check Netlist:
  232. +------+------------------+-------+---------+-------+------------------+
  233. | |Item |Errors |Warnings |Status |Description |
  234. +------+------------------+-------+---------+-------+------------------+
  235. |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
  236. +------+------------------+-------+---------+-------+------------------+
  237. ---------------------------------------------------------------------------------
  238. Start Rebuilding User Hierarchy
  239. ---------------------------------------------------------------------------------
  240. ---------------------------------------------------------------------------------
  241. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  242. ---------------------------------------------------------------------------------
  243. ---------------------------------------------------------------------------------
  244. Start Renaming Generated Ports
  245. ---------------------------------------------------------------------------------
  246. ---------------------------------------------------------------------------------
  247. Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  248. ---------------------------------------------------------------------------------
  249. ---------------------------------------------------------------------------------
  250. Start Handling Custom Attributes
  251. ---------------------------------------------------------------------------------
  252. ---------------------------------------------------------------------------------
  253. Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  254. ---------------------------------------------------------------------------------
  255. ---------------------------------------------------------------------------------
  256. Start Renaming Generated Nets
  257. ---------------------------------------------------------------------------------
  258. ---------------------------------------------------------------------------------
  259. Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  260. ---------------------------------------------------------------------------------
  261. ---------------------------------------------------------------------------------
  262. Start Writing Synthesis Report
  263. ---------------------------------------------------------------------------------
  264.  
  265. Report BlackBoxes:
  266. +-+--------------+----------+
  267. | |BlackBox name |Instances |
  268. +-+--------------+----------+
  269. +-+--------------+----------+
  270.  
  271. Report Cell Usage:
  272. +------+----------+------+
  273. | |Cell |Count |
  274. +------+----------+------+
  275. |1 |BUFGCE | 1|
  276. |2 |CARRY4 | 7|
  277. |3 |LUT1 | 1|
  278. |4 |LUT3 | 1|
  279. |5 |LUT4 | 3|
  280. |6 |LUT5 | 1|
  281. |7 |LUT6 | 5|
  282. |8 |STARTUPE2 | 1|
  283. |9 |FDRE | 28|
  284. |10 |IBUF | 1|
  285. |11 |OBUF | 1|
  286. +------+----------+------+
  287.  
  288. Report Instance Areas:
  289. +------+---------------+-------------+------+
  290. | |Instance |Module |Cells |
  291. +------+---------------+-------------+------+
  292. |1 |top | | 50|
  293. |2 | blink |blink | 46|
  294. |3 | cd_sync |cd_sync | 2|
  295. |4 | pin_clk125_0 |pin_clk125_0 | 1|
  296. |5 | pin_led_2 |pin_led_2 | 1|
  297. +------+---------------+-------------+------+
  298. ---------------------------------------------------------------------------------
  299. Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
  300. ---------------------------------------------------------------------------------
  301. Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
  302. Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 2170.699 ; gain = 272.332 ; free physical = 4916 ; free virtual = 6220
  303. Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 2170.703 ; gain = 375.066 ; free physical = 4916 ; free virtual = 6220
  304. INFO: [Project 1-571] Translating synthesized netlist
  305. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2170.703 ; gain = 0.000 ; free physical = 4909 ; free virtual = 6213
  306. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  307. INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
  308. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  309. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  310. INFO: [Project 1-570] Preparing netlist for logic optimization
  311. Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
  312. Finished Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
  313. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  314. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2188.512 ; gain = 0.000 ; free physical = 4918 ; free virtual = 6222
  315. INFO: [Project 1-111] Unisim Transformation Summary:
  316. A total of 1 instances were transformed.
  317. BUFGCE => BUFGCTRL: 1 instance
  318.  
  319. INFO: [Common 17-83] Releasing license: Synthesis
  320. 33 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
  321. synth_design completed successfully
  322. synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:01:11 . Memory (MB): peak = 2188.512 ; gain = 616.453 ; free physical = 5051 ; free virtual = 6355
  323. # foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
  324. # set_false_path -to $cell
  325. # }
  326. # foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
  327. # set clock [get_clocks -of_objects \
  328. # [all_fanin -flat -startpoints_only [get_pin $cell/D]]]
  329. # if {[llength $clock] != 0} {
  330. # set_max_delay -datapath_only -from $clock \
  331. # -to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
  332. # }
  333. # }
  334. # report_timing_summary -file top_timing_synth.rpt
  335. INFO: [Timing 38-35] Done setting XDC timing constraints.
  336. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  337. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
  338. report_timing_summary: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2418.461 ; gain = 229.949 ; free physical = 4755 ; free virtual = 6059
  339. # report_utilization -hierarchical -file top_utilization_hierachical_synth.rpt
  340. # report_utilization -file top_utilization_synth.rpt
  341. # opt_design
  342. Command: opt_design
  343. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  344. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  345. Running DRC as a precondition to command opt_design
  346.  
  347. Starting DRC Task
  348. INFO: [DRC 23-27] Running DRC with 4 threads
  349. INFO: [Project 1-461] DRC finished with 0 Errors
  350. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  351.  
  352. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2503.012 ; gain = 84.551 ; free physical = 4749 ; free virtual = 6053
  353.  
  354. Starting Cache Timing Information Task
  355. Ending Cache Timing Information Task | Checksum: 20d955e5f
  356.  
  357. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2503.012 ; gain = 0.000 ; free physical = 4749 ; free virtual = 6053
  358.  
  359. Starting Logic Optimization Task
  360.  
  361. Phase 1 Retarget
  362. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  363. INFO: [Opt 31-49] Retargeted 0 cell(s).
  364. Phase 1 Retarget | Checksum: 20d955e5f
  365.  
  366. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  367. INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  368.  
  369. Phase 2 Constant propagation
  370. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  371. Phase 2 Constant propagation | Checksum: 20d955e5f
  372.  
  373. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  374. INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  375.  
  376. Phase 3 Sweep
  377. Phase 3 Sweep | Checksum: 1ce5b7ba3
  378.  
  379. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  380. INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  381.  
  382. Phase 4 BUFG optimization
  383. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
  384. INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
  385. INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
  386. Phase 4 BUFG optimization | Checksum: 1ce5b7ba3
  387.  
  388. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  389. INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  390.  
  391. Phase 5 Shift Register Optimization
  392. INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  393. Phase 5 Shift Register Optimization | Checksum: 1ce5b7ba3
  394.  
  395. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  396. INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  397.  
  398. Phase 6 Post Processing Netlist
  399. Phase 6 Post Processing Netlist | Checksum: 1ce5b7ba3
  400.  
  401. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  402. INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  403. Opt_design Change Summary
  404. =========================
  405.  
  406.  
  407. -------------------------------------------------------------------------------------------------------------------------
  408. | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  409. -------------------------------------------------------------------------------------------------------------------------
  410. | Retarget | 0 | 0 | 0 |
  411. | Constant propagation | 0 | 0 | 0 |
  412. | Sweep | 0 | 0 | 0 |
  413. | BUFG optimization | 0 | 0 | 0 |
  414. | Shift Register Optimization | 0 | 0 | 0 |
  415. | Post Processing Netlist | 0 | 0 | 0 |
  416. -------------------------------------------------------------------------------------------------------------------------
  417.  
  418.  
  419.  
  420. Starting Connectivity Check Task
  421.  
  422. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4619 ; free virtual = 5923
  423. Ending Logic Optimization Task | Checksum: 199893003
  424.  
  425. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
  426.  
  427. Starting Power Optimization Task
  428. INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  429. Ending Power Optimization Task | Checksum: 199893003
  430.  
  431. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
  432.  
  433. Starting Final Cleanup Task
  434. Ending Final Cleanup Task | Checksum: 199893003
  435.  
  436. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
  437.  
  438. Starting Netlist Obfuscation Task
  439. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
  440. Ending Netlist Obfuscation Task | Checksum: 199893003
  441.  
  442. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
  443. INFO: [Common 17-83] Releasing license: Implementation
  444. 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  445. opt_design completed successfully
  446. opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2581.008 ; gain = 162.547 ; free physical = 4618 ; free virtual = 5922
  447. # place_design
  448. Command: place_design
  449. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  450. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  451. INFO: [DRC 23-27] Running DRC with 4 threads
  452. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  453. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  454. Running DRC as a precondition to command place_design
  455. INFO: [DRC 23-27] Running DRC with 4 threads
  456. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  457. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  458.  
  459. Starting Placer Task
  460. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
  461.  
  462. Phase 1 Placer Initialization
  463.  
  464. Phase 1.1 Placer Initialization Netlist Sorting
  465. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
  466. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16b6ae653
  467.  
  468. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
  469. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
  470.  
  471. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  472. INFO: [Timing 38-35] Done setting XDC timing constraints.
  473. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: edca637b
  474.  
  475. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4641 ; free virtual = 5945
  476.  
  477. Phase 1.3 Build Placer Netlist Model
  478. Phase 1.3 Build Placer Netlist Model | Checksum: 1d2bdff66
  479.  
  480. Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4641 ; free virtual = 5945
  481.  
  482. Phase 1.4 Constrain Clocks/Macros
  483. Phase 1.4 Constrain Clocks/Macros | Checksum: 1d2bdff66
  484.  
  485. Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4641 ; free virtual = 5945
  486. Phase 1 Placer Initialization | Checksum: 1d2bdff66
  487.  
  488. Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4640 ; free virtual = 5944
  489.  
  490. Phase 2 Global Placement
  491.  
  492. Phase 2.1 Floorplanning
  493. Phase 2.1 Floorplanning | Checksum: f5be1de3
  494.  
  495. Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4639 ; free virtual = 5943
  496.  
  497. Phase 2.2 Global Placement Core
  498.  
  499. Phase 2.2.1 Physical Synthesis In Placer
  500. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  501. INFO: [Physopt 32-65] No nets found for high-fanout optimization.
  502. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
  503. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  504. INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
  505. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
  506. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
  507. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
  508. INFO: [Physopt 32-949] No candidate nets found for HD net replication
  509. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  510. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2613.023 ; gain = 0.000 ; free physical = 4629 ; free virtual = 5933
  511.  
  512. Summary of Physical Synthesis Optimizations
  513. ============================================
  514.  
  515.  
  516. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  517. | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
  518. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  519. | LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  520. | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  521. | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  522. | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  523. | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  524. | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  525. | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  526. | Total | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
  527. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  528.  
  529.  
  530. Phase 2.2.1 Physical Synthesis In Placer | Checksum: 152961924
  531.  
  532. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4629 ; free virtual = 5933
  533. Phase 2.2 Global Placement Core | Checksum: 1cd764371
  534.  
  535. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
  536. Phase 2 Global Placement | Checksum: 1cd764371
  537.  
  538. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
  539.  
  540. Phase 3 Detail Placement
  541.  
  542. Phase 3.1 Commit Multi Column Macros
  543. Phase 3.1 Commit Multi Column Macros | Checksum: 1719e8549
  544.  
  545. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
  546.  
  547. Phase 3.2 Commit Most Macros & LUTRAMs
  548. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d738e37a
  549.  
  550. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
  551.  
  552. Phase 3.3 Area Swap Optimization
  553. Phase 3.3 Area Swap Optimization | Checksum: 133aec23c
  554.  
  555. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
  556.  
  557. Phase 3.4 Pipeline Register Optimization
  558. Phase 3.4 Pipeline Register Optimization | Checksum: 133aec23c
  559.  
  560. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
  561.  
  562. Phase 3.5 Small Shape Detail Placement
  563. Phase 3.5 Small Shape Detail Placement | Checksum: 198124b57
  564.  
  565. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
  566.  
  567. Phase 3.6 Re-assign LUT pins
  568. Phase 3.6 Re-assign LUT pins | Checksum: 1b43ca254
  569.  
  570. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
  571.  
  572. Phase 3.7 Pipeline Register Optimization
  573. Phase 3.7 Pipeline Register Optimization | Checksum: 1b43ca254
  574.  
  575. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
  576. Phase 3 Detail Placement | Checksum: 1b43ca254
  577.  
  578. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
  579.  
  580. Phase 4 Post Placement Optimization and Clean-Up
  581.  
  582. Phase 4.1 Post Commit Optimization
  583. INFO: [Timing 38-35] Done setting XDC timing constraints.
  584.  
  585. Phase 4.1.1 Post Placement Optimization
  586. Post Placement Optimization Initialization | Checksum: 1e46fbb9b
  587.  
  588. Phase 4.1.1.1 BUFG Insertion
  589. INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
  590. Phase 4.1.1.1 BUFG Insertion | Checksum: 1e46fbb9b
  591.  
  592. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
  593. INFO: [Place 30-746] Post Placement Timing Summary WNS=3.937. For the most accurate timing information please run report_timing.
  594. Phase 4.1.1 Post Placement Optimization | Checksum: 1e83c9c75
  595.  
  596. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
  597. Phase 4.1 Post Commit Optimization | Checksum: 1e83c9c75
  598.  
  599. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
  600.  
  601. Phase 4.2 Post Placement Cleanup
  602. Phase 4.2 Post Placement Cleanup | Checksum: 1e83c9c75
  603.  
  604. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
  605.  
  606. Phase 4.3 Placer Reporting
  607. Phase 4.3 Placer Reporting | Checksum: 1e83c9c75
  608.  
  609. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
  610.  
  611. Phase 4.4 Final Placement Cleanup
  612. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4627 ; free virtual = 5931
  613. Phase 4.4 Final Placement Cleanup | Checksum: 22d166899
  614.  
  615. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
  616. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 22d166899
  617.  
  618. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
  619. Ending Placer Task | Checksum: 1483d3c16
  620.  
  621. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
  622. INFO: [Common 17-83] Releasing license: Implementation
  623. 23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  624. place_design completed successfully
  625. place_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2614.930 ; gain = 33.922 ; free physical = 4634 ; free virtual = 5939
  626. # report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
  627. # report_utilization -file top_utilization_place.rpt
  628. # report_io -file top_io.rpt
  629. report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4627 ; free virtual = 5931
  630. # report_control_sets -verbose -file top_control_sets.rpt
  631. report_control_sets: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4636 ; free virtual = 5940
  632. # report_clock_utilization -file top_clock_utilization.rpt
  633. # route_design
  634. Command: route_design
  635. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  636. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  637. Running DRC as a precondition to command route_design
  638. INFO: [DRC 23-27] Running DRC with 4 threads
  639. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  640. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  641.  
  642.  
  643. Starting Routing Task
  644. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
  645. Checksum: PlaceDB: 8bf79bcb ConstDB: 0 ShapeSum: bc45a04b RouteDB: 0
  646.  
  647. Phase 1 Build RT Design
  648. Phase 1 Build RT Design | Checksum: 1decbe14a
  649.  
  650. Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2724.289 ; gain = 71.668 ; free physical = 4498 ; free virtual = 5802
  651. Post Restoration Checksum: NetGraph: e7ae0298 NumContArr: f71ddeb2 Constraints: 0 Timing: 0
  652.  
  653. Phase 2 Router Initialization
  654.  
  655. Phase 2.1 Create Timer
  656. Phase 2.1 Create Timer | Checksum: 1decbe14a
  657.  
  658. Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2737.289 ; gain = 84.668 ; free physical = 4478 ; free virtual = 5782
  659.  
  660. Phase 2.2 Fix Topology Constraints
  661. Phase 2.2 Fix Topology Constraints | Checksum: 1decbe14a
  662.  
  663. Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2753.289 ; gain = 100.668 ; free physical = 4461 ; free virtual = 5765
  664.  
  665. Phase 2.3 Pre Route Cleanup
  666. Phase 2.3 Pre Route Cleanup | Checksum: 1decbe14a
  667.  
  668. Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2753.289 ; gain = 100.668 ; free physical = 4461 ; free virtual = 5765
  669. Number of Nodes with overlaps = 0
  670.  
  671. Phase 2.4 Update Timing
  672. Phase 2.4 Update Timing | Checksum: 126206e26
  673.  
  674. Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 2774.352 ; gain = 121.730 ; free physical = 4450 ; free virtual = 5754
  675. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.855 | TNS=0.000 | WHS=-0.072 | THS=-0.149 |
  676.  
  677. Phase 2 Router Initialization | Checksum: 1795e7a1c
  678.  
  679. Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 2774.352 ; gain = 121.730 ; free physical = 4452 ; free virtual = 5756
  680.  
  681. Router Utilization Summary
  682. Global Vertical Routing Utilization = 0 %
  683. Global Horizontal Routing Utilization = 0 %
  684. Routable Net Status*
  685. *Does not include unroutable nets such as driverless and loadless.
  686. Run report_route_status for detailed report.
  687. Number of Failed Nets = 44
  688. (Failed Nets is the sum of unrouted and partially routed nets)
  689. Number of Unrouted Nets = 44
  690. Number of Partially Routed Nets = 0
  691. Number of Node Overlaps = 0
  692.  
  693.  
  694. Phase 3 Initial Routing
  695. Phase 3 Initial Routing | Checksum: 15445a32f
  696.  
  697. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4454 ; free virtual = 5758
  698.  
  699. Phase 4 Rip-up And Reroute
  700.  
  701. Phase 4.1 Global Iteration 0
  702. Number of Nodes with overlaps = 3
  703. Number of Nodes with overlaps = 0
  704. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.468 | TNS=0.000 | WHS=N/A | THS=N/A |
  705.  
  706. Phase 4.1 Global Iteration 0 | Checksum: 18ccae16b
  707.  
  708. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  709. Phase 4 Rip-up And Reroute | Checksum: 18ccae16b
  710.  
  711. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  712.  
  713. Phase 5 Delay and Skew Optimization
  714.  
  715. Phase 5.1 Delay CleanUp
  716. Phase 5.1 Delay CleanUp | Checksum: 18ccae16b
  717.  
  718. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  719.  
  720. Phase 5.2 Clock Skew Optimization
  721. Phase 5.2 Clock Skew Optimization | Checksum: 18ccae16b
  722.  
  723. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  724. Phase 5 Delay and Skew Optimization | Checksum: 18ccae16b
  725.  
  726. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  727.  
  728. Phase 6 Post Hold Fix
  729.  
  730. Phase 6.1 Hold Fix Iter
  731.  
  732. Phase 6.1.1 Update Timing
  733. Phase 6.1.1 Update Timing | Checksum: 1780f12f7
  734.  
  735. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  736. INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.639 | TNS=0.000 | WHS=0.249 | THS=0.000 |
  737.  
  738. Phase 6.1 Hold Fix Iter | Checksum: 1780f12f7
  739.  
  740. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  741. Phase 6 Post Hold Fix | Checksum: 1780f12f7
  742.  
  743. Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  744.  
  745. Phase 7 Route finalize
  746.  
  747. Router Utilization Summary
  748. Global Vertical Routing Utilization = 0.00393497 %
  749. Global Horizontal Routing Utilization = 0.00549358 %
  750. Routable Net Status*
  751. *Does not include unroutable nets such as driverless and loadless.
  752. Run report_route_status for detailed report.
  753. Number of Failed Nets = 0
  754. (Failed Nets is the sum of unrouted and partially routed nets)
  755. Number of Unrouted Nets = 0
  756. Number of Partially Routed Nets = 0
  757. Number of Node Overlaps = 0
  758.  
  759. Phase 7 Route finalize | Checksum: 218151504
  760.  
  761. Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
  762.  
  763. Phase 8 Verifying routed nets
  764.  
  765. Verification completed successfully
  766. Phase 8 Verifying routed nets | Checksum: 218151504
  767.  
  768. Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
  769.  
  770. Phase 9 Depositing Routes
  771. Phase 9 Depositing Routes | Checksum: 25fa78c41
  772.  
  773. Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
  774.  
  775. Phase 10 Post Router Timing
  776. INFO: [Route 35-57] Estimated Timing Summary | WNS=3.639 | TNS=0.000 | WHS=0.249 | THS=0.000 |
  777.  
  778. INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
  779. Phase 10 Post Router Timing | Checksum: 25fa78c41
  780.  
  781. Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
  782. INFO: [Route 35-16] Router Completed Successfully
  783.  
  784. Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4473 ; free virtual = 5777
  785.  
  786. Routing Is Done.
  787. INFO: [Common 17-83] Releasing license: Implementation
  788. 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  789. route_design completed successfully
  790. route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:35 . Memory (MB): peak = 2831.742 ; gain = 216.812 ; free physical = 4472 ; free virtual = 5776
  791. INFO: [Common 17-600] The following parameters have non-default value.
  792. general.maxThreads
  793. # phys_opt_design
  794. Command: phys_opt_design
  795. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  796. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  797. INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
  798. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
  799. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
  800. INFO: [Common 17-83] Releasing license: Implementation
  801. 5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  802. phys_opt_design completed successfully
  803. INFO: [Common 17-600] The following parameters have non-default value.
  804. general.maxThreads
  805. # report_timing_summary -no_header -no_detailed_paths
  806. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  807. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
  808. ------------------------------------------------------------------------------------------------
  809. | Timer Settings
  810. | --------------
  811. ------------------------------------------------------------------------------------------------
  812.  
  813. Enable Multi Corner Analysis : Yes
  814. Enable Pessimism Removal : Yes
  815. Pessimism Removal Resolution : Nearest Common Node
  816. Enable Input Delay Default Clock : No
  817. Enable Preset / Clear Arcs : No
  818. Disable Flight Delays : No
  819. Ignore I/O Paths : No
  820. Timing Early Launch at Borrowing Latches : No
  821. Borrow Time for Max Delay Exceptions : Yes
  822. Merge Timing Exceptions : Yes
  823.  
  824. Corner Analyze Analyze
  825. Name Max Paths Min Paths
  826. ------ --------- ---------
  827. Slow Yes Yes
  828. Fast Yes Yes
  829.  
  830.  
  831.  
  832. check_timing report
  833.  
  834. Table of Contents
  835. -----------------
  836. 1. checking no_clock
  837. 2. checking constant_clock
  838. 3. checking pulse_width_clock
  839. 4. checking unconstrained_internal_endpoints
  840. 5. checking no_input_delay
  841. 6. checking no_output_delay
  842. 7. checking multiple_clock
  843. 8. checking generated_clocks
  844. 9. checking loops
  845. 10. checking partial_input_delay
  846. 11. checking partial_output_delay
  847. 12. checking latch_loops
  848.  
  849. 1. checking no_clock
  850. --------------------
  851. There are 0 register/latch pins with no clock.
  852.  
  853.  
  854. 2. checking constant_clock
  855. --------------------------
  856. There are 0 register/latch pins with constant_clock.
  857.  
  858.  
  859. 3. checking pulse_width_clock
  860. -----------------------------
  861. There are 0 register/latch pins which need pulse_width check
  862.  
  863.  
  864. 4. checking unconstrained_internal_endpoints
  865. --------------------------------------------
  866. There are 0 pins that are not constrained for maximum delay.
  867.  
  868. There are 0 pins that are not constrained for maximum delay due to constant clock.
  869.  
  870.  
  871. 5. checking no_input_delay
  872. --------------------------
  873. There are 0 input ports with no input delay specified.
  874.  
  875. There are 0 input ports with no input delay but user has a false path constraint.
  876.  
  877.  
  878. 6. checking no_output_delay
  879. ---------------------------
  880. There is 1 port with no output delay specified. (HIGH)
  881.  
  882. There are 0 ports with no output delay but user has a false path constraint
  883.  
  884. There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
  885.  
  886.  
  887. 7. checking multiple_clock
  888. --------------------------
  889. There are 0 register/latch pins with multiple clocks.
  890.  
  891.  
  892. 8. checking generated_clocks
  893. ----------------------------
  894. There are 0 generated clocks that are not connected to a clock source.
  895.  
  896.  
  897. 9. checking loops
  898. -----------------
  899. There are 0 combinational loops in the design.
  900.  
  901.  
  902. 10. checking partial_input_delay
  903. --------------------------------
  904. There are 0 input ports with partial input delay specified.
  905.  
  906.  
  907. 11. checking partial_output_delay
  908. ---------------------------------
  909. There are 0 ports with partial output delay specified.
  910.  
  911.  
  912. 12. checking latch_loops
  913. ------------------------
  914. There are 0 combinational latch loops in the design through latch input
  915.  
  916.  
  917.  
  918. ------------------------------------------------------------------------------------------------
  919. | Design Timing Summary
  920. | ---------------------
  921. ------------------------------------------------------------------------------------------------
  922.  
  923. WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  924. ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  925. 3.640 0.000 0 55 0.265 0.000 0 55 3.500 0.000 0 29
  926.  
  927.  
  928. All user specified timing constraints are met.
  929.  
  930.  
  931. ------------------------------------------------------------------------------------------------
  932. | Clock Summary
  933. | -------------
  934. ------------------------------------------------------------------------------------------------
  935.  
  936. Clock Waveform(ns) Period(ns) Frequency(MHz)
  937. ----- ------------ ---------- --------------
  938. clk125_0__io {0.000 4.000} 8.000 125.000
  939.  
  940.  
  941. ------------------------------------------------------------------------------------------------
  942. | Intra Clock Table
  943. | -----------------
  944. ------------------------------------------------------------------------------------------------
  945.  
  946. Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  947. ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  948. clk125_0__io 3.640 0.000 0 55 0.265 0.000 0 55 3.500 0.000 0 29
  949.  
  950.  
  951. ------------------------------------------------------------------------------------------------
  952. | Inter Clock Table
  953. | -----------------
  954. ------------------------------------------------------------------------------------------------
  955.  
  956. From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  957. ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  958.  
  959.  
  960. ------------------------------------------------------------------------------------------------
  961. | Other Path Groups Table
  962. | -----------------------
  963. ------------------------------------------------------------------------------------------------
  964.  
  965. Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  966. ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  967.  
  968.  
  969. # write_checkpoint -force top_route.dcp
  970. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.742 ; gain = 0.000 ; free physical = 4472 ; free virtual = 5776
  971. INFO: [Timing 38-480] Writing timing data to binary archive.
  972. Writing placer database...
  973. Writing XDEF routing.
  974. Writing XDEF routing logical nets.
  975. Writing XDEF routing special nets.
  976. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2834.660 ; gain = 2.918 ; free physical = 4468 ; free virtual = 5773
  977. INFO: [Common 17-1381] The checkpoint '/home/simpleton/checking_nmigen/build/top_route.dcp' has been generated.
  978. # report_route_status -file top_route_status.rpt
  979. # report_drc -file top_drc.rpt
  980. Command: report_drc -file top_drc.rpt
  981. INFO: [IP_Flow 19-234] Refreshing IP repositories
  982. INFO: [IP_Flow 19-1704] No user IP repositories specified
  983. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.2/data/ip'.
  984. INFO: [DRC 23-27] Running DRC with 4 threads
  985. INFO: [Coretcl 2-168] The results of DRC are in file /home/simpleton/checking_nmigen/build/top_drc.rpt.
  986. report_drc completed successfully
  987. report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2879.262 ; gain = 44.598 ; free physical = 4464 ; free virtual = 5768
  988. # report_methodology -file top_methodology.rpt
  989. Command: report_methodology -file top_methodology.rpt
  990. INFO: [Timing 38-35] Done setting XDC timing constraints.
  991. INFO: [DRC 23-133] Running Methodology with 4 threads
  992. INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/simpleton/checking_nmigen/build/top_methodology.rpt.
  993. report_methodology completed successfully
  994. # report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
  995. INFO: [Timing 38-35] Done setting XDC timing constraints.
  996. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
  997. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
  998. # report_power -file top_power.rpt
  999. Command: report_power -file top_power.rpt
  1000. INFO: [Power 33-23] Power model is not available for U$$0
  1001. Running Vector-less Activity Propagation...
  1002.  
  1003. Finished Running Vector-less Activity Propagation
  1004. 1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1005. report_power completed successfully
  1006. # write_bitstream -force -bin_file top.bit
  1007. Command: write_bitstream -force -bin_file top.bit
  1008. Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
  1009. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
  1010. Running DRC as a precondition to command write_bitstream
  1011. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  1012. INFO: [DRC 23-27] Running DRC with 4 threads
  1013. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
  1014. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
  1015. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  1016. INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
  1017. Loading data files...
  1018. Loading site data...
  1019. Loading route data...
  1020. Processing options...
  1021. Creating bitmap...
  1022. Creating bitstream...
  1023. Writing bitstream ./top.bit...
  1024. Writing bitstream ./top.bin...
  1025. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  1026. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  1027. INFO: [Common 17-186] '/home/simpleton/checking_nmigen/build/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Jul 23 08:53:40 2020. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
  1028. INFO: [Common 17-83] Releasing license: Implementation
  1029. 10 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1030. write_bitstream completed successfully
  1031. write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 3200.129 ; gain = 304.863 ; free physical = 4439 ; free virtual = 5743
  1032. # quit
  1033. INFO: [Common 17-206] Exiting Vivado at Thu Jul 23 08:53:41 2020...
  1034.  
  1035. ****** Vivado v2019.2 (64-bit)
  1036. **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
  1037. **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
  1038. ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  1039.  
  1040. source program_fpga.tcl
  1041. # open_hw_manager
  1042. # connect_hw_server -allow_non_jtag
  1043. INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
  1044. INFO: [Labtools 27-2222] Launching hw_server...
  1045. INFO: [Labtools 27-2221] Launch Output:
  1046.  
  1047. ****** Xilinx hw_server v2019.2
  1048. **** Build date : Nov 6 2019 at 22:13:42
  1049. ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  1050.  
  1051.  
  1052. INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
  1053. INFO: [Labtools 27-3417] Launching cs_server...
  1054. INFO: [Labtools 27-2221] Launch Output:
  1055. [?1034h
  1056.  
  1057. ****** Xilinx cs_server v2019.2.0
  1058. **** Build date : Nov 07 2019-05:41:48
  1059. ** Copyright 2017-2019 Xilinx, Inc. All Rights Reserved.
  1060.  
  1061.  
  1062.  
  1063. # open_hw_target
  1064. INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/003017A704DCA
  1065. # current_hw_device [get_hw_devices xc7z020_1]
  1066. # set_property PROGRAM.FILE [lindex $argv 0] [get_hw_devices xc7z020_1]
  1067. # program_hw_devices [get_hw_devices xc7z020_1]
  1068. INFO: [Labtools 27-3164] End of startup status: HIGH
  1069. # refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
  1070. INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
  1071. INFO: [Common 17-206] Exiting Vivado at Thu Jul 23 08:54:14 2020...
Add Comment
Please, Sign In to add comment