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- ****** Vivado v2019.2 (64-bit)
- **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
- **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
- ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
- source top.tcl
- # create_project -force -name top -part xc7z020clg400-1
- # add_files top.v
- # read_xdc top.xdc
- # synth_design -top top
- Command: synth_design -top top
- Starting synth_design
- Using part: xc7z020clg400-1
- Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
- INFO: [Device 21-403] Loading part xc7z020clg400-1
- INFO: Launching helper process for spawning children vivado processes
- INFO: Helper process launched with PID 91228
- ---------------------------------------------------------------------------------
- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1997.309 ; gain = 201.676 ; free physical = 5003 ; free virtual = 6298
- ---------------------------------------------------------------------------------
- INFO: [Synth 8-6157] synthesizing module 'top' [/home/simpleton/checking_nmigen/build/top.v:65]
- INFO: [Synth 8-5534] Detected attribute (* keep = "TRUE" *) [/home/simpleton/checking_nmigen/build/top.v:69]
- INFO: [Synth 8-6157] synthesizing module 'blink' [/home/simpleton/checking_nmigen/build/top.v:4]
- INFO: [Synth 8-6155] done synthesizing module 'blink' (1#1) [/home/simpleton/checking_nmigen/build/top.v:4]
- INFO: [Synth 8-6157] synthesizing module 'cd_sync' [/home/simpleton/checking_nmigen/build/top.v:31]
- INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78135]
- Parameter PROG_USR bound to: FALSE - type: string
- Parameter SIM_CCLK_FREQ bound to: 0.000000 - type: double
- INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (2#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:78135]
- WARNING: [Synth 8-7023] instance 'U$$0' of module 'STARTUPE2' has 13 connections declared, but only 1 given [/home/simpleton/checking_nmigen/build/top.v:36]
- INFO: [Synth 8-6157] synthesizing module 'BUFGCE' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1085]
- Parameter CE_TYPE bound to: SYNC - type: string
- Parameter IS_CE_INVERTED bound to: 1'b0
- Parameter IS_I_INVERTED bound to: 1'b0
- Parameter SIM_DEVICE bound to: ULTRASCALE - type: string
- Parameter STARTUP_SYNC bound to: FALSE - type: string
- INFO: [Synth 8-6155] done synthesizing module 'BUFGCE' (3#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1085]
- INFO: [Synth 8-6155] done synthesizing module 'cd_sync' (4#1) [/home/simpleton/checking_nmigen/build/top.v:31]
- INFO: [Synth 8-6157] synthesizing module 'pin_clk125_0' [/home/simpleton/checking_nmigen/build/top.v:46]
- INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:32937]
- Parameter CAPACITANCE bound to: DONT_CARE - type: string
- Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
- Parameter IBUF_LOW_PWR bound to: TRUE - type: string
- Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
- Parameter IOSTANDARD bound to: DEFAULT - type: string
- INFO: [Synth 8-6155] done synthesizing module 'IBUF' (5#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:32937]
- INFO: [Synth 8-6155] done synthesizing module 'pin_clk125_0' (6#1) [/home/simpleton/checking_nmigen/build/top.v:46]
- INFO: [Synth 8-6157] synthesizing module 'pin_led_2' [/home/simpleton/checking_nmigen/build/top.v:56]
- INFO: [Synth 8-6157] synthesizing module 'OBUF' [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:46211]
- Parameter CAPACITANCE bound to: DONT_CARE - type: string
- Parameter DRIVE bound to: 12 - type: integer
- Parameter IOSTANDARD bound to: DEFAULT - type: string
- Parameter SLEW bound to: SLOW - type: string
- INFO: [Synth 8-6155] done synthesizing module 'OBUF' (7#1) [/tools/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:46211]
- INFO: [Synth 8-6155] done synthesizing module 'pin_led_2' (8#1) [/home/simpleton/checking_nmigen/build/top.v:56]
- INFO: [Synth 8-6155] done synthesizing module 'top' (9#1) [/home/simpleton/checking_nmigen/build/top.v:65]
- ---------------------------------------------------------------------------------
- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2059.062 ; gain = 263.430 ; free physical = 5036 ; free virtual = 6334
- ---------------------------------------------------------------------------------
- Report Check Netlist:
- +------+------------------+-------+---------+-------+------------------+
- | |Item |Errors |Warnings |Status |Description |
- +------+------------------+-------+---------+-------+------------------+
- |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
- +------+------------------+-------+---------+-------+------------------+
- ---------------------------------------------------------------------------------
- Start Handling Custom Attributes
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2062.027 ; gain = 266.395 ; free physical = 5028 ; free virtual = 6327
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2062.027 ; gain = 266.395 ; free physical = 5028 ; free virtual = 6327
- ---------------------------------------------------------------------------------
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2071.934 ; gain = 0.000 ; free physical = 5020 ; free virtual = 6319
- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
- INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
- INFO: [Project 1-570] Preparing netlist for logic optimization
- Processing XDC Constraints
- Initializing timing engine
- Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
- Finished Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
- INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/simpleton/checking_nmigen/build/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
- Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
- Completed Processing XDC Constraints
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2164.762 ; gain = 0.000 ; free physical = 4939 ; free virtual = 6238
- INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 1 instances were transformed.
- BUFGCE => BUFGCTRL: 1 instance
- Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2164.762 ; gain = 0.000 ; free physical = 4939 ; free virtual = 6238
- ---------------------------------------------------------------------------------
- Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6306
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Loading Part and Timing Information
- ---------------------------------------------------------------------------------
- Loading part: xc7z020clg400-1
- ---------------------------------------------------------------------------------
- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6306
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Applying 'set_property' XDC Constraints
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.762 ; gain = 369.129 ; free physical = 5006 ; free virtual = 6305
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4996 ; free virtual = 6297
- ---------------------------------------------------------------------------------
- Report RTL Partitions:
- +-+--------------+------------+----------+
- | |RTL Partition |Replication |Instances |
- +-+--------------+------------+----------+
- +-+--------------+------------+----------+
- ---------------------------------------------------------------------------------
- Start RTL Component Statistics
- ---------------------------------------------------------------------------------
- Detailed RTL Component Info :
- +---XORs :
- 2 Input 1 Bit XORs := 1
- +---Registers :
- 1 Bit Registers := 1
- ---------------------------------------------------------------------------------
- Finished RTL Component Statistics
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start RTL Hierarchical Component Statistics
- ---------------------------------------------------------------------------------
- Hierarchical RTL Component report
- Module blink
- Detailed RTL Component Info :
- +---XORs :
- 2 Input 1 Bit XORs := 1
- +---Registers :
- 1 Bit Registers := 1
- ---------------------------------------------------------------------------------
- Finished RTL Hierarchical Component Statistics
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Part Resource Summary
- ---------------------------------------------------------------------------------
- Part Resources:
- DSPs: 220 (col length:60)
- BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
- ---------------------------------------------------------------------------------
- Finished Part Resource Summary
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Cross Boundary and Area Optimization
- ---------------------------------------------------------------------------------
- Warning: Parallel synthesis criteria is not met
- ---------------------------------------------------------------------------------
- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4983 ; free virtual = 6287
- ---------------------------------------------------------------------------------
- Report RTL Partitions:
- +-+--------------+------------+----------+
- | |RTL Partition |Replication |Instances |
- +-+--------------+------------+----------+
- +-+--------------+------------+----------+
- ---------------------------------------------------------------------------------
- Start Applying XDC Timing Constraints
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Timing Optimization
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
- ---------------------------------------------------------------------------------
- Report RTL Partitions:
- +-+--------------+------------+----------+
- | |RTL Partition |Replication |Instances |
- +-+--------------+------------+----------+
- +-+--------------+------------+----------+
- ---------------------------------------------------------------------------------
- Start Technology Mapping
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2164.766 ; gain = 369.133 ; free physical = 4860 ; free virtual = 6164
- ---------------------------------------------------------------------------------
- Report RTL Partitions:
- +-+--------------+------------+----------+
- | |RTL Partition |Replication |Instances |
- +-+--------------+------------+----------+
- +-+--------------+------------+----------+
- ---------------------------------------------------------------------------------
- Start IO Insertion
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Flattening Before IO Insertion
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Flattening Before IO Insertion
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Final Netlist Cleanup
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Final Netlist Cleanup
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Renaming Generated Instances
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- Report RTL Partitions:
- +-+--------------+------------+----------+
- | |RTL Partition |Replication |Instances |
- +-+--------------+------------+----------+
- +-+--------------+------------+----------+
- Report Check Netlist:
- +------+------------------+-------+---------+-------+------------------+
- | |Item |Errors |Warnings |Status |Description |
- +------+------------------+-------+---------+-------+------------------+
- |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
- +------+------------------+-------+---------+-------+------------------+
- ---------------------------------------------------------------------------------
- Start Rebuilding User Hierarchy
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Renaming Generated Ports
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Handling Custom Attributes
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Renaming Generated Nets
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- ---------------------------------------------------------------------------------
- Start Writing Synthesis Report
- ---------------------------------------------------------------------------------
- Report BlackBoxes:
- +-+--------------+----------+
- | |BlackBox name |Instances |
- +-+--------------+----------+
- +-+--------------+----------+
- Report Cell Usage:
- +------+----------+------+
- | |Cell |Count |
- +------+----------+------+
- |1 |BUFGCE | 1|
- |2 |CARRY4 | 7|
- |3 |LUT1 | 1|
- |4 |LUT3 | 1|
- |5 |LUT4 | 3|
- |6 |LUT5 | 1|
- |7 |LUT6 | 5|
- |8 |STARTUPE2 | 1|
- |9 |FDRE | 28|
- |10 |IBUF | 1|
- |11 |OBUF | 1|
- +------+----------+------+
- Report Instance Areas:
- +------+---------------+-------------+------+
- | |Instance |Module |Cells |
- +------+---------------+-------------+------+
- |1 |top | | 50|
- |2 | blink |blink | 46|
- |3 | cd_sync |cd_sync | 2|
- |4 | pin_clk125_0 |pin_clk125_0 | 1|
- |5 | pin_led_2 |pin_led_2 | 1|
- +------+---------------+-------------+------+
- ---------------------------------------------------------------------------------
- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 2170.699 ; gain = 375.066 ; free physical = 4859 ; free virtual = 6163
- ---------------------------------------------------------------------------------
- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
- Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 2170.699 ; gain = 272.332 ; free physical = 4916 ; free virtual = 6220
- Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:48 . Memory (MB): peak = 2170.703 ; gain = 375.066 ; free physical = 4916 ; free virtual = 6220
- INFO: [Project 1-571] Translating synthesized netlist
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2170.703 ; gain = 0.000 ; free physical = 4909 ; free virtual = 6213
- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCE' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
- INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'cd_sync/U$$1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
- INFO: [Project 1-570] Preparing netlist for logic optimization
- Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
- Finished Parsing XDC File [/home/simpleton/checking_nmigen/build/top.xdc]
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2188.512 ; gain = 0.000 ; free physical = 4918 ; free virtual = 6222
- INFO: [Project 1-111] Unisim Transformation Summary:
- A total of 1 instances were transformed.
- BUFGCE => BUFGCTRL: 1 instance
- INFO: [Common 17-83] Releasing license: Synthesis
- 33 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
- synth_design completed successfully
- synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:01:11 . Memory (MB): peak = 2188.512 ; gain = 616.453 ; free physical = 5051 ; free virtual = 6355
- # foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
- # set_false_path -to $cell
- # }
- # foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
- # set clock [get_clocks -of_objects \
- # [all_fanin -flat -startpoints_only [get_pin $cell/D]]]
- # if {[llength $clock] != 0} {
- # set_max_delay -datapath_only -from $clock \
- # -to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
- # }
- # }
- # report_timing_summary -file top_timing_synth.rpt
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
- report_timing_summary: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2418.461 ; gain = 229.949 ; free physical = 4755 ; free virtual = 6059
- # report_utilization -hierarchical -file top_utilization_hierachical_synth.rpt
- # report_utilization -file top_utilization_synth.rpt
- # opt_design
- Command: opt_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
- Running DRC as a precondition to command opt_design
- Starting DRC Task
- INFO: [DRC 23-27] Running DRC with 4 threads
- INFO: [Project 1-461] DRC finished with 0 Errors
- INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2503.012 ; gain = 84.551 ; free physical = 4749 ; free virtual = 6053
- Starting Cache Timing Information Task
- Ending Cache Timing Information Task | Checksum: 20d955e5f
- Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2503.012 ; gain = 0.000 ; free physical = 4749 ; free virtual = 6053
- Starting Logic Optimization Task
- Phase 1 Retarget
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- INFO: [Opt 31-49] Retargeted 0 cell(s).
- Phase 1 Retarget | Checksum: 20d955e5f
- Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
- Phase 2 Constant propagation
- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
- Phase 2 Constant propagation | Checksum: 20d955e5f
- Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
- Phase 3 Sweep
- Phase 3 Sweep | Checksum: 1ce5b7ba3
- Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
- Phase 4 BUFG optimization
- INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver.
- INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver.
- INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s).
- Phase 4 BUFG optimization | Checksum: 1ce5b7ba3
- Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
- Phase 5 Shift Register Optimization
- INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
- Phase 5 Shift Register Optimization | Checksum: 1ce5b7ba3
- Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
- Phase 6 Post Processing Netlist
- Phase 6 Post Processing Netlist | Checksum: 1ce5b7ba3
- Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
- Opt_design Change Summary
- =========================
- -------------------------------------------------------------------------------------------------------------------------
- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
- -------------------------------------------------------------------------------------------------------------------------
- | Retarget | 0 | 0 | 0 |
- | Constant propagation | 0 | 0 | 0 |
- | Sweep | 0 | 0 | 0 |
- | BUFG optimization | 0 | 0 | 0 |
- | Shift Register Optimization | 0 | 0 | 0 |
- | Post Processing Netlist | 0 | 0 | 0 |
- -------------------------------------------------------------------------------------------------------------------------
- Starting Connectivity Check Task
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4619 ; free virtual = 5923
- Ending Logic Optimization Task | Checksum: 199893003
- Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2581.008 ; gain = 0.004 ; free physical = 4619 ; free virtual = 5923
- Starting Power Optimization Task
- INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
- Ending Power Optimization Task | Checksum: 199893003
- Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
- Starting Final Cleanup Task
- Ending Final Cleanup Task | Checksum: 199893003
- Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
- Starting Netlist Obfuscation Task
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
- Ending Netlist Obfuscation Task | Checksum: 199893003
- Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.008 ; gain = 0.000 ; free physical = 4618 ; free virtual = 5922
- INFO: [Common 17-83] Releasing license: Implementation
- 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- opt_design completed successfully
- opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2581.008 ; gain = 162.547 ; free physical = 4618 ; free virtual = 5922
- # place_design
- Command: place_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [DRC 23-27] Running DRC with 4 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
- Running DRC as a precondition to command place_design
- INFO: [DRC 23-27] Running DRC with 4 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
- Starting Placer Task
- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
- Phase 1 Placer Initialization
- Phase 1.1 Placer Initialization Netlist Sorting
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16b6ae653
- Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4644 ; free virtual = 5948
- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: edca637b
- Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2581.012 ; gain = 0.000 ; free physical = 4641 ; free virtual = 5945
- Phase 1.3 Build Placer Netlist Model
- Phase 1.3 Build Placer Netlist Model | Checksum: 1d2bdff66
- Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4641 ; free virtual = 5945
- Phase 1.4 Constrain Clocks/Macros
- Phase 1.4 Constrain Clocks/Macros | Checksum: 1d2bdff66
- Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4641 ; free virtual = 5945
- Phase 1 Placer Initialization | Checksum: 1d2bdff66
- Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4640 ; free virtual = 5944
- Phase 2 Global Placement
- Phase 2.1 Floorplanning
- Phase 2.1 Floorplanning | Checksum: f5be1de3
- Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2605.020 ; gain = 24.008 ; free physical = 4639 ; free virtual = 5943
- Phase 2.2 Global Placement Core
- Phase 2.2.1 Physical Synthesis In Placer
- INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
- INFO: [Physopt 32-65] No nets found for high-fanout optimization.
- INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
- INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
- INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
- INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
- INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
- INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
- INFO: [Physopt 32-949] No candidate nets found for HD net replication
- INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2613.023 ; gain = 0.000 ; free physical = 4629 ; free virtual = 5933
- Summary of Physical Synthesis Optimizations
- ============================================
- -----------------------------------------------------------------------------------------------------------------------------------------------------------
- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
- -----------------------------------------------------------------------------------------------------------------------------------------------------------
- | LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
- | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
- | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
- | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
- | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
- | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
- | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
- | Total | 0 | 0 | 0 | 0 | 3 | 00:00:00 |
- -----------------------------------------------------------------------------------------------------------------------------------------------------------
- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 152961924
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4629 ; free virtual = 5933
- Phase 2.2 Global Placement Core | Checksum: 1cd764371
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
- Phase 2 Global Placement | Checksum: 1cd764371
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
- Phase 3 Detail Placement
- Phase 3.1 Commit Multi Column Macros
- Phase 3.1 Commit Multi Column Macros | Checksum: 1719e8549
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4628 ; free virtual = 5932
- Phase 3.2 Commit Most Macros & LUTRAMs
- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d738e37a
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
- Phase 3.3 Area Swap Optimization
- Phase 3.3 Area Swap Optimization | Checksum: 133aec23c
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
- Phase 3.4 Pipeline Register Optimization
- Phase 3.4 Pipeline Register Optimization | Checksum: 133aec23c
- Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4627 ; free virtual = 5931
- Phase 3.5 Small Shape Detail Placement
- Phase 3.5 Small Shape Detail Placement | Checksum: 198124b57
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
- Phase 3.6 Re-assign LUT pins
- Phase 3.6 Re-assign LUT pins | Checksum: 1b43ca254
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
- Phase 3.7 Pipeline Register Optimization
- Phase 3.7 Pipeline Register Optimization | Checksum: 1b43ca254
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
- Phase 3 Detail Placement | Checksum: 1b43ca254
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2613.023 ; gain = 32.012 ; free physical = 4625 ; free virtual = 5929
- Phase 4 Post Placement Optimization and Clean-Up
- Phase 4.1 Post Commit Optimization
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- Phase 4.1.1 Post Placement Optimization
- Post Placement Optimization Initialization | Checksum: 1e46fbb9b
- Phase 4.1.1.1 BUFG Insertion
- INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
- Phase 4.1.1.1 BUFG Insertion | Checksum: 1e46fbb9b
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
- INFO: [Place 30-746] Post Placement Timing Summary WNS=3.937. For the most accurate timing information please run report_timing.
- Phase 4.1.1 Post Placement Optimization | Checksum: 1e83c9c75
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
- Phase 4.1 Post Commit Optimization | Checksum: 1e83c9c75
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4625 ; free virtual = 5929
- Phase 4.2 Post Placement Cleanup
- Phase 4.2 Post Placement Cleanup | Checksum: 1e83c9c75
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
- Phase 4.3 Placer Reporting
- Phase 4.3 Placer Reporting | Checksum: 1e83c9c75
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
- Phase 4.4 Final Placement Cleanup
- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4627 ; free virtual = 5931
- Phase 4.4 Final Placement Cleanup | Checksum: 22d166899
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 22d166899
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
- Ending Placer Task | Checksum: 1483d3c16
- Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2614.930 ; gain = 33.918 ; free physical = 4627 ; free virtual = 5931
- INFO: [Common 17-83] Releasing license: Implementation
- 23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- place_design completed successfully
- place_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2614.930 ; gain = 33.922 ; free physical = 4634 ; free virtual = 5939
- # report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
- # report_utilization -file top_utilization_place.rpt
- # report_io -file top_io.rpt
- report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4627 ; free virtual = 5931
- # report_control_sets -verbose -file top_control_sets.rpt
- report_control_sets: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2614.930 ; gain = 0.000 ; free physical = 4636 ; free virtual = 5940
- # report_clock_utilization -file top_clock_utilization.rpt
- # route_design
- Command: route_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
- Running DRC as a precondition to command route_design
- INFO: [DRC 23-27] Running DRC with 4 threads
- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
- INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
- Starting Routing Task
- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
- Checksum: PlaceDB: 8bf79bcb ConstDB: 0 ShapeSum: bc45a04b RouteDB: 0
- Phase 1 Build RT Design
- Phase 1 Build RT Design | Checksum: 1decbe14a
- Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2724.289 ; gain = 71.668 ; free physical = 4498 ; free virtual = 5802
- Post Restoration Checksum: NetGraph: e7ae0298 NumContArr: f71ddeb2 Constraints: 0 Timing: 0
- Phase 2 Router Initialization
- Phase 2.1 Create Timer
- Phase 2.1 Create Timer | Checksum: 1decbe14a
- Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2737.289 ; gain = 84.668 ; free physical = 4478 ; free virtual = 5782
- Phase 2.2 Fix Topology Constraints
- Phase 2.2 Fix Topology Constraints | Checksum: 1decbe14a
- Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2753.289 ; gain = 100.668 ; free physical = 4461 ; free virtual = 5765
- Phase 2.3 Pre Route Cleanup
- Phase 2.3 Pre Route Cleanup | Checksum: 1decbe14a
- Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2753.289 ; gain = 100.668 ; free physical = 4461 ; free virtual = 5765
- Number of Nodes with overlaps = 0
- Phase 2.4 Update Timing
- Phase 2.4 Update Timing | Checksum: 126206e26
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 2774.352 ; gain = 121.730 ; free physical = 4450 ; free virtual = 5754
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.855 | TNS=0.000 | WHS=-0.072 | THS=-0.149 |
- Phase 2 Router Initialization | Checksum: 1795e7a1c
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 2774.352 ; gain = 121.730 ; free physical = 4452 ; free virtual = 5756
- Router Utilization Summary
- Global Vertical Routing Utilization = 0 %
- Global Horizontal Routing Utilization = 0 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 44
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 44
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
- Phase 3 Initial Routing
- Phase 3 Initial Routing | Checksum: 15445a32f
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4454 ; free virtual = 5758
- Phase 4 Rip-up And Reroute
- Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 3
- Number of Nodes with overlaps = 0
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.468 | TNS=0.000 | WHS=N/A | THS=N/A |
- Phase 4.1 Global Iteration 0 | Checksum: 18ccae16b
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 4 Rip-up And Reroute | Checksum: 18ccae16b
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 5 Delay and Skew Optimization
- Phase 5.1 Delay CleanUp
- Phase 5.1 Delay CleanUp | Checksum: 18ccae16b
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 5.2 Clock Skew Optimization
- Phase 5.2 Clock Skew Optimization | Checksum: 18ccae16b
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 5 Delay and Skew Optimization | Checksum: 18ccae16b
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 6 Post Hold Fix
- Phase 6.1 Hold Fix Iter
- Phase 6.1.1 Update Timing
- Phase 6.1.1 Update Timing | Checksum: 1780f12f7
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.639 | TNS=0.000 | WHS=0.249 | THS=0.000 |
- Phase 6.1 Hold Fix Iter | Checksum: 1780f12f7
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 6 Post Hold Fix | Checksum: 1780f12f7
- Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 7 Route finalize
- Router Utilization Summary
- Global Vertical Routing Utilization = 0.00393497 %
- Global Horizontal Routing Utilization = 0.00549358 %
- Routable Net Status*
- *Does not include unroutable nets such as driverless and loadless.
- Run report_route_status for detailed report.
- Number of Failed Nets = 0
- (Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 0
- Number of Partially Routed Nets = 0
- Number of Node Overlaps = 0
- Phase 7 Route finalize | Checksum: 218151504
- Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4453 ; free virtual = 5757
- Phase 8 Verifying routed nets
- Verification completed successfully
- Phase 8 Verifying routed nets | Checksum: 218151504
- Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
- Phase 9 Depositing Routes
- Phase 9 Depositing Routes | Checksum: 25fa78c41
- Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
- Phase 10 Post Router Timing
- INFO: [Route 35-57] Estimated Timing Summary | WNS=3.639 | TNS=0.000 | WHS=0.249 | THS=0.000 |
- INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
- Phase 10 Post Router Timing | Checksum: 25fa78c41
- Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4452 ; free virtual = 5756
- INFO: [Route 35-16] Router Completed Successfully
- Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 2775.355 ; gain = 122.734 ; free physical = 4473 ; free virtual = 5777
- Routing Is Done.
- INFO: [Common 17-83] Releasing license: Implementation
- 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- route_design completed successfully
- route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:35 . Memory (MB): peak = 2831.742 ; gain = 216.812 ; free physical = 4472 ; free virtual = 5776
- INFO: [Common 17-600] The following parameters have non-default value.
- general.maxThreads
- # phys_opt_design
- Command: phys_opt_design
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
- INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
- INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
- INFO: [Common 17-83] Releasing license: Implementation
- 5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- phys_opt_design completed successfully
- INFO: [Common 17-600] The following parameters have non-default value.
- general.maxThreads
- # report_timing_summary -no_header -no_detailed_paths
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
- ------------------------------------------------------------------------------------------------
- | Timer Settings
- | --------------
- ------------------------------------------------------------------------------------------------
- Enable Multi Corner Analysis : Yes
- Enable Pessimism Removal : Yes
- Pessimism Removal Resolution : Nearest Common Node
- Enable Input Delay Default Clock : No
- Enable Preset / Clear Arcs : No
- Disable Flight Delays : No
- Ignore I/O Paths : No
- Timing Early Launch at Borrowing Latches : No
- Borrow Time for Max Delay Exceptions : Yes
- Merge Timing Exceptions : Yes
- Corner Analyze Analyze
- Name Max Paths Min Paths
- ------ --------- ---------
- Slow Yes Yes
- Fast Yes Yes
- check_timing report
- Table of Contents
- -----------------
- 1. checking no_clock
- 2. checking constant_clock
- 3. checking pulse_width_clock
- 4. checking unconstrained_internal_endpoints
- 5. checking no_input_delay
- 6. checking no_output_delay
- 7. checking multiple_clock
- 8. checking generated_clocks
- 9. checking loops
- 10. checking partial_input_delay
- 11. checking partial_output_delay
- 12. checking latch_loops
- 1. checking no_clock
- --------------------
- There are 0 register/latch pins with no clock.
- 2. checking constant_clock
- --------------------------
- There are 0 register/latch pins with constant_clock.
- 3. checking pulse_width_clock
- -----------------------------
- There are 0 register/latch pins which need pulse_width check
- 4. checking unconstrained_internal_endpoints
- --------------------------------------------
- There are 0 pins that are not constrained for maximum delay.
- There are 0 pins that are not constrained for maximum delay due to constant clock.
- 5. checking no_input_delay
- --------------------------
- There are 0 input ports with no input delay specified.
- There are 0 input ports with no input delay but user has a false path constraint.
- 6. checking no_output_delay
- ---------------------------
- There is 1 port with no output delay specified. (HIGH)
- There are 0 ports with no output delay but user has a false path constraint
- There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
- 7. checking multiple_clock
- --------------------------
- There are 0 register/latch pins with multiple clocks.
- 8. checking generated_clocks
- ----------------------------
- There are 0 generated clocks that are not connected to a clock source.
- 9. checking loops
- -----------------
- There are 0 combinational loops in the design.
- 10. checking partial_input_delay
- --------------------------------
- There are 0 input ports with partial input delay specified.
- 11. checking partial_output_delay
- ---------------------------------
- There are 0 ports with partial output delay specified.
- 12. checking latch_loops
- ------------------------
- There are 0 combinational latch loops in the design through latch input
- ------------------------------------------------------------------------------------------------
- | Design Timing Summary
- | ---------------------
- ------------------------------------------------------------------------------------------------
- WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
- 3.640 0.000 0 55 0.265 0.000 0 55 3.500 0.000 0 29
- All user specified timing constraints are met.
- ------------------------------------------------------------------------------------------------
- | Clock Summary
- | -------------
- ------------------------------------------------------------------------------------------------
- Clock Waveform(ns) Period(ns) Frequency(MHz)
- ----- ------------ ---------- --------------
- clk125_0__io {0.000 4.000} 8.000 125.000
- ------------------------------------------------------------------------------------------------
- | Intra Clock Table
- | -----------------
- ------------------------------------------------------------------------------------------------
- Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
- ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
- clk125_0__io 3.640 0.000 0 55 0.265 0.000 0 55 3.500 0.000 0 29
- ------------------------------------------------------------------------------------------------
- | Inter Clock Table
- | -----------------
- ------------------------------------------------------------------------------------------------
- From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
- ------------------------------------------------------------------------------------------------
- | Other Path Groups Table
- | -----------------------
- ------------------------------------------------------------------------------------------------
- Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
- ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
- # write_checkpoint -force top_route.dcp
- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.742 ; gain = 0.000 ; free physical = 4472 ; free virtual = 5776
- INFO: [Timing 38-480] Writing timing data to binary archive.
- Writing placer database...
- Writing XDEF routing.
- Writing XDEF routing logical nets.
- Writing XDEF routing special nets.
- Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2834.660 ; gain = 2.918 ; free physical = 4468 ; free virtual = 5773
- INFO: [Common 17-1381] The checkpoint '/home/simpleton/checking_nmigen/build/top_route.dcp' has been generated.
- # report_route_status -file top_route_status.rpt
- # report_drc -file top_drc.rpt
- Command: report_drc -file top_drc.rpt
- INFO: [IP_Flow 19-234] Refreshing IP repositories
- INFO: [IP_Flow 19-1704] No user IP repositories specified
- INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.2/data/ip'.
- INFO: [DRC 23-27] Running DRC with 4 threads
- INFO: [Coretcl 2-168] The results of DRC are in file /home/simpleton/checking_nmigen/build/top_drc.rpt.
- report_drc completed successfully
- report_drc: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2879.262 ; gain = 44.598 ; free physical = 4464 ; free virtual = 5768
- # report_methodology -file top_methodology.rpt
- Command: report_methodology -file top_methodology.rpt
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [DRC 23-133] Running Methodology with 4 threads
- INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/simpleton/checking_nmigen/build/top_methodology.rpt.
- report_methodology completed successfully
- # report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
- INFO: [Timing 38-35] Done setting XDC timing constraints.
- INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
- INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
- # report_power -file top_power.rpt
- Command: report_power -file top_power.rpt
- INFO: [Power 33-23] Power model is not available for U$$0
- Running Vector-less Activity Propagation...
- Finished Running Vector-less Activity Propagation
- 1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
- report_power completed successfully
- # write_bitstream -force -bin_file top.bit
- Command: write_bitstream -force -bin_file top.bit
- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
- Running DRC as a precondition to command write_bitstream
- INFO: [IP_Flow 19-1839] IP Catalog is up to date.
- INFO: [DRC 23-27] Running DRC with 4 threads
- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
- INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
- INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
- INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
- Loading data files...
- Loading site data...
- Loading route data...
- Processing options...
- Creating bitmap...
- Creating bitstream...
- Writing bitstream ./top.bit...
- Writing bitstream ./top.bin...
- INFO: [Vivado 12-1842] Bitgen Completed Successfully.
- INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
- INFO: [Common 17-186] '/home/simpleton/checking_nmigen/build/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Jul 23 08:53:40 2020. For additional details about this file, please refer to the WebTalk help file at /tools/Xilinx/Vivado/2019.2/doc/webtalk_introduction.html.
- INFO: [Common 17-83] Releasing license: Implementation
- 10 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
- write_bitstream completed successfully
- write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:35 . Memory (MB): peak = 3200.129 ; gain = 304.863 ; free physical = 4439 ; free virtual = 5743
- # quit
- INFO: [Common 17-206] Exiting Vivado at Thu Jul 23 08:53:41 2020...
- ****** Vivado v2019.2 (64-bit)
- **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
- **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
- ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
- source program_fpga.tcl
- # open_hw_manager
- # connect_hw_server -allow_non_jtag
- INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
- INFO: [Labtools 27-2222] Launching hw_server...
- INFO: [Labtools 27-2221] Launch Output:
- ****** Xilinx hw_server v2019.2
- **** Build date : Nov 6 2019 at 22:13:42
- ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
- INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
- INFO: [Labtools 27-3417] Launching cs_server...
- INFO: [Labtools 27-2221] Launch Output:
- [?1034h
- ****** Xilinx cs_server v2019.2.0
- **** Build date : Nov 07 2019-05:41:48
- ** Copyright 2017-2019 Xilinx, Inc. All Rights Reserved.
- # open_hw_target
- INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/003017A704DCA
- # current_hw_device [get_hw_devices xc7z020_1]
- # set_property PROGRAM.FILE [lindex $argv 0] [get_hw_devices xc7z020_1]
- # program_hw_devices [get_hw_devices xc7z020_1]
- INFO: [Labtools 27-3164] End of startup status: HIGH
- # refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
- INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
- INFO: [Common 17-206] Exiting Vivado at Thu Jul 23 08:54:14 2020...
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