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lite-on c-100 stock dts (extracted)

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Oct 9th, 2023
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x01>;
  5. #size-cells = <0x01>;
  6. model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
  7. compatible = "qcom,ipq4019";
  8. interrupt-parent = <0x01>;
  9. qcom,board-id = <0x08 0x00>;
  10. qcom,msm-id = <0x111 0x00>;
  11. qcom,pmic-id = <0x00 0x00 0x00 0x00>;
  12.  
  13. chosen {
  14. bootargs-append = " clk_ignore_unused";
  15. };
  16.  
  17. aliases {
  18. spi0 = "/soc/spi@78b5000";
  19. spi1 = "/soc/spi@78b6000";
  20. i2c0 = "/soc/i2c@78b7000";
  21. i2c1 = "/soc/i2c@78b8000";
  22. ethernet0 = "/soc/edma/gmac0";
  23. ethernet1 = "/soc/edma/gmac1";
  24. mhi1 = "/soc/qcom,mhi@1";
  25. sdhc1 = "/soc/sdhci@7824000";
  26. };
  27.  
  28. memory {
  29. device_type = "memory";
  30. reg = <0x80000000 0x10000000>;
  31. };
  32.  
  33. cpus {
  34. #address-cells = <0x01>;
  35. #size-cells = <0x00>;
  36.  
  37. cpu@0 {
  38. device_type = "cpu";
  39. compatible = "arm,cortex-a7";
  40. enable-method = "qcom,kpss-acc-v1";
  41. qcom,acc = <0x02>;
  42. qcom,saw = <0x03>;
  43. reg = <0x00>;
  44. clocks = <0x04 0x09>;
  45. clock-frequency = <0x00>;
  46. operating-points = <0xbb80 0x10c8e0 0x30d40 0x10c8e0 0x7a120 0x10c8e0 0xa4100 0x10c8e0 0xaece0 0x10c8e0>;
  47. clock-latency = <0x186a0>;
  48. };
  49.  
  50. cpu@1 {
  51. device_type = "cpu";
  52. compatible = "arm,cortex-a7";
  53. enable-method = "qcom,kpss-acc-v1";
  54. qcom,acc = <0x05>;
  55. qcom,saw = <0x06>;
  56. reg = <0x01>;
  57. clocks = <0x04 0x09>;
  58. clock-frequency = <0x00>;
  59. };
  60.  
  61. cpu@2 {
  62. device_type = "cpu";
  63. compatible = "arm,cortex-a7";
  64. enable-method = "qcom,kpss-acc-v1";
  65. qcom,acc = <0x07>;
  66. qcom,saw = <0x08>;
  67. reg = <0x02>;
  68. clocks = <0x04 0x09>;
  69. clock-frequency = <0x00>;
  70. };
  71.  
  72. cpu@3 {
  73. device_type = "cpu";
  74. compatible = "arm,cortex-a7";
  75. enable-method = "qcom,kpss-acc-v1";
  76. qcom,acc = <0x09>;
  77. qcom,saw = <0x0a>;
  78. reg = <0x03>;
  79. clocks = <0x04 0x09>;
  80. clock-frequency = <0x00>;
  81. };
  82. };
  83.  
  84. pmu {
  85. compatible = "arm,cortex-a7-pmu";
  86. interrupts = <0x01 0x07 0xf04>;
  87. };
  88.  
  89. clocks {
  90.  
  91. gcc_sleep_clk_src {
  92. compatible = "fixed-clock";
  93. clock-frequency = <0x7d00>;
  94. #clock-cells = <0x00>;
  95. linux,phandle = <0x11>;
  96. phandle = <0x11>;
  97. };
  98.  
  99. xo {
  100. compatible = "fixed-clock";
  101. clock-frequency = <0x2dc6c00>;
  102. #clock-cells = <0x00>;
  103. };
  104. };
  105.  
  106. firmware {
  107.  
  108. scm {
  109. compatible = "qcom,scm-ipq40xx";
  110. };
  111.  
  112. qfprom {
  113. compatible = "qcom,qfprom-sec";
  114. };
  115. };
  116.  
  117. soc {
  118. #address-cells = <0x01>;
  119. #size-cells = <0x01>;
  120. ranges;
  121. compatible = "simple-bus";
  122.  
  123. interrupt-controller@b000000 {
  124. compatible = "qcom,msm-qgic2";
  125. interrupt-controller;
  126. #interrupt-cells = <0x03>;
  127. reg = <0xb000000 0x1000 0xb002000 0x1000>;
  128. linux,phandle = <0x01>;
  129. phandle = <0x01>;
  130. };
  131.  
  132. counter {
  133. compatible = "qcom,qca-gcnt";
  134. reg = <0x4a1000 0x04>;
  135. };
  136.  
  137. clock-controller@1800000 {
  138. compatible = "qcom,gcc-ipq4019";
  139. #clock-cells = <0x01>;
  140. #reset-cells = <0x01>;
  141. reg = <0x1800000 0x60000>;
  142. linux,phandle = <0x04>;
  143. phandle = <0x04>;
  144. };
  145.  
  146. pinctrl@0x01000000 {
  147. compatible = "qcom,ipq4019-pinctrl";
  148. reg = <0x1000000 0x300000>;
  149. gpio-controller;
  150. #gpio-cells = <0x02>;
  151. interrupt-controller;
  152. #interrupt-cells = <0x02>;
  153. interrupts = <0x00 0xd0 0x00>;
  154. linux,phandle = <0x0d>;
  155. phandle = <0x0d>;
  156.  
  157. serial0_pinmux {
  158. linux,phandle = <0x0f>;
  159. phandle = <0x0f>;
  160.  
  161. mux {
  162. pins = "gpio16\0gpio17";
  163. function = "blsp_uart0";
  164. bias-disable;
  165. };
  166. };
  167.  
  168. led0_pinmux {
  169. linux,phandle = <0x12>;
  170. phandle = <0x12>;
  171.  
  172. mux_1 {
  173. pins = "gpio36";
  174. function = "led0";
  175. bias-pull-down;
  176. };
  177.  
  178. mux_2 {
  179. pins = "gpio40";
  180. function = "led4";
  181. bias-pull-down;
  182. };
  183. };
  184.  
  185. serial1_pinmux {
  186. linux,phandle = <0x10>;
  187. phandle = <0x10>;
  188.  
  189. mux {
  190. pins = "gpio8\0gpio9\0gpio10\0gpio11";
  191. function = "blsp_uart1";
  192. bias-disable;
  193. };
  194. };
  195.  
  196. spi_0_pinmux {
  197. linux,phandle = <0x0c>;
  198. phandle = <0x0c>;
  199.  
  200. pinmux {
  201. function = "blsp_spi0";
  202. pins = "gpio13\0gpio14\0gpio15";
  203. bias-disable;
  204. };
  205.  
  206. pinmux_cs {
  207. function = "gpio";
  208. pins = "gpio12";
  209. bias-disable;
  210. output-high;
  211. };
  212. };
  213.  
  214. i2c_0_pinmux {
  215. linux,phandle = <0x0e>;
  216. phandle = <0x0e>;
  217.  
  218. mux {
  219. pins = "gpio20\0gpio21";
  220. function = "blsp_i2c0";
  221. bias-disable;
  222. };
  223. };
  224.  
  225. sd_0_pinmux {
  226. linux,phandle = <0x13>;
  227. phandle = <0x13>;
  228.  
  229. sd0 {
  230. pins = "gpio23";
  231. function = "sdio0";
  232. pull-res = <0x02>;
  233. drive-type = <0x01>;
  234. vm-enable;
  235. };
  236.  
  237. sd1 {
  238. pins = "gpio24";
  239. function = "sdio1";
  240. pull-res = <0x02>;
  241. drive-type = <0x01>;
  242. vm-enable;
  243. };
  244.  
  245. sd2 {
  246. pins = "gpio25";
  247. function = "sdio2";
  248. pull-res = <0x02>;
  249. drive-type = <0x01>;
  250. vm-enable;
  251. };
  252.  
  253. sd3 {
  254. pins = "gpio26";
  255. function = "sdio3";
  256. pull-res = <0x02>;
  257. drive-type = <0x01>;
  258. vm-enable;
  259. };
  260.  
  261. sdclk {
  262. pins = "gpio27";
  263. function = "sdio_clk";
  264. pull-res = <0x02>;
  265. drive-type = <0x07>;
  266. vm-enable;
  267. };
  268.  
  269. sdcmd {
  270. pins = "gpio28";
  271. function = "sdio_cmd";
  272. pull-res = <0x02>;
  273. drive-type = <0x01>;
  274. vm-enable;
  275. };
  276.  
  277. sd4 {
  278. pins = "gpio29";
  279. function = "sdio4";
  280. pull-res = <0x02>;
  281. drive-type = <0x01>;
  282. vm-enable;
  283. };
  284.  
  285. sd5 {
  286. pins = "gpio30";
  287. function = "sdio5";
  288. pull-res = <0x02>;
  289. drive-type = <0x01>;
  290. vm-enable;
  291. };
  292.  
  293. sd6 {
  294. pins = "gpio31";
  295. function = "sdio6";
  296. pull-res = <0x02>;
  297. drive-type = <0x01>;
  298. vm-enable;
  299. };
  300.  
  301. sd7 {
  302. pins = "gpio32";
  303. function = "sdio7";
  304. pull-res = <0x02>;
  305. drive-type = <0x01>;
  306. vm-enable;
  307. };
  308. };
  309.  
  310. sd_1_pinmux {
  311. linux,phandle = <0x14>;
  312. phandle = <0x14>;
  313.  
  314. sd0 {
  315. pins = "gpio23";
  316. function = "sdio0";
  317. pull-res = <0x02>;
  318. drive-type = <0x00>;
  319. vm-enable;
  320. };
  321.  
  322. sd1 {
  323. pins = "gpio24";
  324. function = "sdio1";
  325. pull-res = <0x02>;
  326. drive-type = <0x00>;
  327. vm-enable;
  328. };
  329.  
  330. sd2 {
  331. pins = "gpio25";
  332. function = "sdio2";
  333. pull-res = <0x02>;
  334. drive-type = <0x00>;
  335. vm-enable;
  336. };
  337.  
  338. sd3 {
  339. pins = "gpio26";
  340. function = "sdio3";
  341. pull-res = <0x02>;
  342. drive-type = <0x00>;
  343. vm-enable;
  344. };
  345.  
  346. sdclk {
  347. pins = "gpio27";
  348. function = "sdio_clk";
  349. pull-res = <0x02>;
  350. drive-type = <0x00>;
  351. vm-enable;
  352. };
  353.  
  354. sdcmd {
  355. pins = "gpio28";
  356. function = "sdio_cmd";
  357. pull-res = <0x02>;
  358. drive-type = <0x00>;
  359. vm-enable;
  360. };
  361.  
  362. sd4 {
  363. pins = "gpio29";
  364. function = "sdio4";
  365. pull-res = <0x02>;
  366. drive-type = <0x00>;
  367. vm-enable;
  368. };
  369.  
  370. sd5 {
  371. pins = "gpio30";
  372. function = "sdio5";
  373. pull-res = <0x02>;
  374. drive-type = <0x00>;
  375. vm-enable;
  376. };
  377.  
  378. sd6 {
  379. pins = "gpio31";
  380. function = "sdio6";
  381. pull-res = <0x02>;
  382. drive-type = <0x00>;
  383. vm-enable;
  384. };
  385.  
  386. sd7 {
  387. pins = "gpio32";
  388. function = "sdio7";
  389. pull-res = <0x02>;
  390. drive-type = <0x00>;
  391. vm-enable;
  392. };
  393. };
  394.  
  395. ts_0_pinmux {
  396.  
  397. mux_1 {
  398. pins = "gpio34";
  399. output-high;
  400. };
  401.  
  402. mux_2 {
  403. pins = "gpio35";
  404. input-enable;
  405. bias-pull-up;
  406. };
  407. };
  408.  
  409. mdio_pinmux {
  410. linux,phandle = <0x19>;
  411. phandle = <0x19>;
  412.  
  413. mux_1 {
  414. pins = "gpio6";
  415. function = "mdio0";
  416. bias-pull-up;
  417. };
  418.  
  419. mux_2 {
  420. pins = "gpio7";
  421. function = "mdc";
  422. bias-pull-up;
  423. };
  424. };
  425.  
  426. nand_pins {
  427. linux,phandle = <0x1b>;
  428. phandle = <0x1b>;
  429.  
  430. mux_1 {
  431. pins = "gpio52\0gpio53\0gpio54\0gpio55\0gpio56\0gpio61\0gpio62\0gpio63\0gpio69";
  432. function = "qpic_pad";
  433. bias-disable;
  434. };
  435.  
  436. mux_2 {
  437. pins = "gpio67";
  438. function = "qpic_pad0";
  439. bias-disable;
  440. };
  441.  
  442. mux_3 {
  443. pins = "gpio64";
  444. function = "qpic_pad1";
  445. bias-disable;
  446. };
  447.  
  448. mux_4 {
  449. pins = "gpio65";
  450. function = "qpic_pad2";
  451. bias-disable;
  452. };
  453.  
  454. mux_5 {
  455. pins = "gpio66";
  456. function = "qpic_pad3";
  457. bias-disable;
  458. };
  459.  
  460. mux_6 {
  461. pins = "gpio57";
  462. function = "qpic_pad4";
  463. bias-disable;
  464. };
  465.  
  466. mux_7 {
  467. pins = "gpio58";
  468. function = "qpic_pad5";
  469. bias-disable;
  470. };
  471.  
  472. mux_8 {
  473. pins = "gpio59";
  474. function = "qpic_pad6";
  475. bias-disable;
  476. };
  477.  
  478. mux_9 {
  479. pins = "gpio60";
  480. function = "qpic_pad7";
  481. bias-disable;
  482. };
  483.  
  484. mux_10 {
  485. pins = "gpio68";
  486. function = "qpic_pad8";
  487. bias-disable;
  488. };
  489.  
  490. pullups {
  491. pins = "gpio52\0gpio53\0gpio58\0gpio59";
  492. bias-pull-up;
  493. };
  494.  
  495. pulldowns {
  496. pins = "gpio54\0gpio55\0gpio56\0gpio57\0gpio60\0gpio61\0gpio62\0gpio63\0gpio64\0gpio65\0gpio66\0gpio67\0gpio68\0gpio69";
  497. bias-pull-down;
  498. };
  499. };
  500. };
  501.  
  502. timer {
  503. compatible = "arm,armv7-timer";
  504. interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
  505. clock-frequency = <0x2dc6c00>;
  506. always-on;
  507. };
  508.  
  509. dma@7884000 {
  510. compatible = "qcom,bam-v1.7.0";
  511. reg = <0x7884000 0x23000>;
  512. interrupts = <0x00 0xee 0x00>;
  513. clocks = <0x04 0x15>;
  514. clock-names = "bam_clk";
  515. #dma-cells = <0x01>;
  516. qcom,ee = <0x00>;
  517. status = "ok";
  518. linux,phandle = <0x0b>;
  519. phandle = <0x0b>;
  520. };
  521.  
  522. spi@78b5000 {
  523. compatible = "qcom,spi-qup-v2.2.1";
  524. reg = <0x78b5000 0x600>;
  525. interrupts = <0x00 0x5f 0x04>;
  526. clocks = <0x04 0x17 0x04 0x15>;
  527. clock-names = "core\0iface";
  528. #address-cells = <0x01>;
  529. #size-cells = <0x00>;
  530. dmas = <0x0b 0x05 0x0b 0x04>;
  531. dma-names = "rx\0tx";
  532. status = "ok";
  533. pinctrl-0 = <0x0c>;
  534. pinctrl-names = "default";
  535. cs-gpios = <0x0d 0x0c 0x00>;
  536.  
  537. m25p80@0 {
  538. #address-cells = <0x01>;
  539. #size-cells = <0x01>;
  540. reg = <0x00>;
  541. compatible = "n25q128a11";
  542. linux,modalias = "m25p80\0n25q128a11";
  543. spi-max-frequency = <0x16e3600>;
  544. use-default-sizes;
  545. };
  546. };
  547.  
  548. spi@78b6000 {
  549. compatible = "qcom,spi-qup-v2.2.1";
  550. reg = <0x78b6000 0x600>;
  551. interrupts = <0x00 0x60 0x04>;
  552. clocks = <0x04 0x19 0x04 0x15>;
  553. clock-names = "core\0iface";
  554. #address-cells = <0x01>;
  555. #size-cells = <0x00>;
  556. dmas = <0x0b 0x07 0x0b 0x06>;
  557. dma-names = "rx\0tx";
  558. status = "disabled";
  559. };
  560.  
  561. rng@0x00022000 {
  562. compatible = "qcom,prng";
  563. reg = <0x22000 0x140>;
  564. clocks = <0x04 0x2b>;
  565. clock-names = "core";
  566. };
  567.  
  568. i2c@78b7000 {
  569. compatible = "qcom,i2c-qup-v2.2.1";
  570. #address-cells = <0x01>;
  571. #size-cells = <0x00>;
  572. reg = <0x78b7000 0x600>;
  573. interrupts = <0x00 0x61 0x04>;
  574. clocks = <0x04 0x15 0x04 0x16>;
  575. clock-names = "iface\0core";
  576. clock-frequency = <0x186a0>;
  577. qup-clock-frequency = <0x122ae10>;
  578. dmas = <0x0b 0x09 0x0b 0x08>;
  579. dma-names = "rx\0tx";
  580. status = "ok";
  581. pinctrl-0 = <0x0e>;
  582. pinctrl-names = "default";
  583.  
  584. lcd_ts@40 {
  585. compatible = "qca,gsl1680_ts";
  586. reg = <0x40>;
  587. status = "disabled";
  588. };
  589. };
  590.  
  591. i2c@78b8000 {
  592. compatible = "qcom,i2c-qup-v2.2.1";
  593. #address-cells = <0x01>;
  594. #size-cells = <0x00>;
  595. reg = <0x78b8000 0x600>;
  596. interrupts = <0x00 0x62 0x04>;
  597. clocks = <0x04 0x15 0x04 0x18>;
  598. clock-names = "iface\0core";
  599. clock-frequency = <0x186a0>;
  600. qup-clock-frequency = <0x122ae10>;
  601. dmas = <0x0b 0x0b 0x0b 0x0a>;
  602. dma-names = "rx\0tx";
  603. status = "disabled";
  604. };
  605.  
  606. qcom,sps {
  607. compatible = "qcom,msm_sps_4k";
  608. qcom,device-type = <0x03>;
  609. qcom,pipe-attr-ee;
  610. };
  611.  
  612. qcrypto@8e20000 {
  613. compatible = "qcom,qcrypto";
  614. reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
  615. reg-names = "crypto-base\0crypto-bam-base";
  616. interrupts = <0x00 0xcf 0x00>;
  617. qcom,bam-pipe-pair = <0x01>;
  618. qcom,ce-hw-instance = <0x00>;
  619. qcom,ce-hw-shared = <0x01>;
  620. qcom,ce-device = <0x00>;
  621. qcom,ce-opp-freq = <0x7735940>;
  622. clocks = <0x04 0x23 0x04 0x22 0x04 0x21>;
  623. clock-names = "core_clk\0bus_clk\0iface_clk";
  624. status = "ok";
  625. };
  626.  
  627. qcedev@8e20000 {
  628. compatible = "qcom,qcedev";
  629. reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
  630. reg-names = "crypto-base\0crypto-bam-base";
  631. interrupts = <0x00 0xcf 0x00>;
  632. qcom,bam-pipe-pair = <0x01>;
  633. qcom,ce-hw-instance = <0x00>;
  634. qcom,ce-hw-shared = <0x01>;
  635. qcom,ce-device = <0x00>;
  636. qcom,ce-opp-freq = <0x7735940>;
  637. clocks = <0x04 0x23 0x04 0x22 0x04 0x21>;
  638. clock-names = "core_clk\0bus_clk\0iface_clk";
  639. status = "ok";
  640. };
  641.  
  642. clock-controller@b088000 {
  643. compatible = "qcom,kpss-acc-v1";
  644. reg = <0xb088000 0x1000 0xb008000 0x1000>;
  645. linux,phandle = <0x02>;
  646. phandle = <0x02>;
  647. };
  648.  
  649. clock-controller@b098000 {
  650. compatible = "qcom,kpss-acc-v1";
  651. reg = <0xb098000 0x1000 0xb008000 0x1000>;
  652. linux,phandle = <0x05>;
  653. phandle = <0x05>;
  654. };
  655.  
  656. clock-controller@b0a8000 {
  657. compatible = "qcom,kpss-acc-v1";
  658. reg = <0xb0a8000 0x1000 0xb008000 0x1000>;
  659. linux,phandle = <0x07>;
  660. phandle = <0x07>;
  661. };
  662.  
  663. clock-controller@b0b8000 {
  664. compatible = "qcom,kpss-acc-v1";
  665. reg = <0xb0b8000 0x1000 0xb008000 0x1000>;
  666. linux,phandle = <0x09>;
  667. phandle = <0x09>;
  668. };
  669.  
  670. regulator@b089000 {
  671. compatible = "qcom,saw2";
  672. reg = <0x2089000 0x1000 0xb009000 0x1000>;
  673. regulator;
  674. linux,phandle = <0x03>;
  675. phandle = <0x03>;
  676. };
  677.  
  678. regulator@b099000 {
  679. compatible = "qcom,saw2";
  680. reg = <0xb099000 0x1000 0xb009000 0x1000>;
  681. regulator;
  682. linux,phandle = <0x06>;
  683. phandle = <0x06>;
  684. };
  685.  
  686. regulator@b0a9000 {
  687. compatible = "qcom,saw2";
  688. reg = <0xb0a9000 0x1000 0xb009000 0x1000>;
  689. regulator;
  690. linux,phandle = <0x08>;
  691. phandle = <0x08>;
  692. };
  693.  
  694. regulator@b0b9000 {
  695. compatible = "qcom,saw2";
  696. reg = <0xb0b9000 0x1000 0xb009000 0x1000>;
  697. regulator;
  698. linux,phandle = <0x0a>;
  699. phandle = <0x0a>;
  700. };
  701.  
  702. serial@78af000 {
  703. compatible = "qcom,msm-hsl-uartdm-v1.4";
  704. reg = <0x78af000 0x200>;
  705. interrupts = <0x00 0x6b 0x00>;
  706. status = "ok";
  707. clocks = <0x04 0x1a 0x04 0x15>;
  708. clock-names = "core\0iface";
  709. pinctrl-0 = <0x0f>;
  710. pinctrl-names = "default";
  711. };
  712.  
  713. serial@78b0000 {
  714. compatible = "qcom,msm-hsl-uartdm-v1.4";
  715. reg = <0x78b0000 0x200>;
  716. interrupts = <0x00 0x6c 0x00>;
  717. status = "ok";
  718. clocks = <0x04 0x1b 0x04 0x15>;
  719. clock-names = "core\0iface";
  720. dmas = <0x0b 0x03 0x0b 0x02>;
  721. dma-names = "rx\0tx";
  722. pinctrl-0 = <0x10>;
  723. pinctrl-names = "default";
  724. };
  725.  
  726. watchdog@b017000 {
  727. compatible = "qcom,kpss-wdt-ipq40xx";
  728. reg = <0xb017000 0x40 0x87b70000 0x10000>;
  729. reg-names = "kpss_wdt\0tlv";
  730. interrupt-names = "bark_irq";
  731. interrupts = <0x00 0x03 0x00>;
  732. clocks = <0x11>;
  733. timeout-sec = <0x0a>;
  734. wdt-max-timeout = <0x20>;
  735. status = "ok";
  736. };
  737.  
  738. pci@40000000 {
  739. compatible = "qcom,pcie-ipq4019";
  740. reg = <0x40000000 0xf1d 0x40000f20 0xa8 0x80000 0x2000 0x40100000 0x1000>;
  741. reg-names = "dbi\0elbi\0parf\0config";
  742. device_type = "pci";
  743. linux,pci-domain = <0x00>;
  744. bus-range = <0x00 0xff>;
  745. num-lanes = <0x01>;
  746. #address-cells = <0x03>;
  747. #size-cells = <0x02>;
  748. ranges = <0x81000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x82000000 0x00 0x48000000 0x48000000 0x00 0x10000000>;
  749. interrupts = <0x00 0x8d 0x00>;
  750. interrupt-names = "msi";
  751. #interrupt-cells = <0x01>;
  752. interrupt-map-mask = <0x00 0x00 0x00 0x07>;
  753. interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x8e 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x8f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x90 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x91 0x04>;
  754. clocks = <0x04 0x27 0x04 0x28 0x04 0x29>;
  755. clock-names = "ahb\0axi_m\0axi_s";
  756. resets = <0x04 0x1c 0x04 0x1b 0x04 0x1a 0x04 0x19 0x04 0x18 0x04 0x17 0x04 0x16 0x04 0x15 0x04 0x14 0x04 0x13 0x04 0x12 0x04 0x11>;
  757. reset-names = "axi_m\0axi_s\0pipe\0axi_m_vmid\0axi_s_xpu\0parf\0phy\0axi_m_sticky\0pipe_sticky\0pwr\0ahb\0phy_ahb";
  758. status = "ok";
  759. perst-gpio = <0x0d 0x26 0x01>;
  760. };
  761.  
  762. pwm {
  763. compatible = "qca,ipq4019-pwm";
  764. clocks = <0x04 0x14>;
  765. clock-names = "core";
  766. pwm-base-index = <0x00>;
  767. used-pwm-indices = <0x01 0x01 0x01 0x01>;
  768. status = "disabled";
  769. };
  770.  
  771. ledc@1937000 {
  772. compatible = "qca,ledc";
  773. reg = <0x1937000 0x20070>;
  774. reg-names = "ledc_base_addr";
  775. qcom,tcsr_ledc_values = <0x320193 0x14720800 0x20d 0x00 0x00 0xffffffff 0x00 0x07 0x7d0010 0x00 0x10482090 0x3fffdfc>;
  776. qcom,ledc_blink_indices_cnt = <0x00>;
  777. qcom,ledc_blink_indices = <0x00>;
  778. status = "ok";
  779. pinctrl-0 = <0x12>;
  780. pinctrl-names = "default";
  781. };
  782.  
  783. restart@4ab000 {
  784. compatible = "qcom,pshold";
  785. reg = <0x4ab000 0x04>;
  786. };
  787.  
  788. qca,scm_restart_reason {
  789. compatible = "qca,scm_restart_reason";
  790. };
  791.  
  792. sdhci@7824000 {
  793. compatible = "qcom,sdhci-msm";
  794. reg = <0x7824900 0x11c 0x7824000 0x800>;
  795. reg-names = "hc_mem\0core_mem";
  796. interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>;
  797. interrupt-names = "hc_irq\0pwr_irq";
  798. qcom,bus-width = <0x08>;
  799. qcom,max_clk = <0xb71b000>;
  800. clocks = <0x04 0x2f 0x04 0x2e>;
  801. clock-names = "core_clk\0iface_clk";
  802. qcom,large-address-bus;
  803. qcom,disable-aggressive-pm;
  804. status = "ok";
  805. qcom,bus-speed-mode = "HS200_1p8v\0DDR_1p8v";
  806. qcom,clk-rates = <0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>;
  807. pinctrl-0 = <0x13>;
  808. pinctrl-1 = <0x14>;
  809. pinctrl-names = "active\0sleep";
  810. vqmmc-supply = <0x15>;
  811. cd-gpios = <0x0d 0x16 0x01>;
  812. sd-ldo-gpios = <0x0d 0x21 0x01>;
  813. };
  814.  
  815. clock-controller@7700038 {
  816. compatible = "qcom,adcc-ipq4019";
  817. #clock-cells = <0x01>;
  818. #reset-cells = <0x01>;
  819. reg = <0x7700038 0x1dc>;
  820. status = "disabled";
  821. };
  822.  
  823. tcsr@194b000 {
  824. compatible = "ipq,tcsr";
  825. reg = <0x194b000 0x100>;
  826. ipq,usb-hsphy-mode-select = <0xe700e7>;
  827. status = "ok";
  828. };
  829.  
  830. ess_tcsr@1953000 {
  831. compatible = "ipq,tcsr";
  832. reg = <0x1953000 0x1000>;
  833. ipq,ess-interface-select = <0x00>;
  834. };
  835.  
  836. ssphy@0 {
  837. compatible = "qca,uni-ssphy";
  838. reg = <0x9a000 0x800>;
  839. reg-names = "phy_base";
  840. resets = <0x04 0x0c>;
  841. reset-names = "por_rst";
  842. qca,host = <0x01>;
  843. #phy-cells = <0x00>;
  844. status = "ok";
  845. linux,phandle = <0x17>;
  846. phandle = <0x17>;
  847. };
  848.  
  849. hsphy@a6000 {
  850. compatible = "qca,baldur-usb-hsphy";
  851. reg = <0xa6000 0x40 0x8af8800 0x100>;
  852. reg-names = "phy_base\0qscratch_base";
  853. resets = <0x04 0x0d 0x04 0x0e>;
  854. reset-names = "por_rst\0srif_rst";
  855. qca,host = <0x01>;
  856. #phy-cells = <0x00>;
  857. status = "ok";
  858. linux,phandle = <0x16>;
  859. phandle = <0x16>;
  860. };
  861.  
  862. hsphy@a8000 {
  863. compatible = "qca,baldur-usb-hsphy";
  864. reg = <0xa8000 0x40>;
  865. reg-names = "phy_base";
  866. resets = <0x04 0x0f 0x04 0x10>;
  867. reset-names = "por_rst\0srif_rst";
  868. qca,host = <0x01>;
  869. #phy-cells = <0x00>;
  870. status = "ok";
  871. linux,phandle = <0x18>;
  872. phandle = <0x18>;
  873. };
  874.  
  875. usb3@8a00000 {
  876. compatible = "qcom,dwc3";
  877. #address-cells = <0x01>;
  878. #size-cells = <0x01>;
  879. ranges;
  880. reg = <0x8af8800 0x100>;
  881. reg-names = "qscratch_base";
  882. clocks = <0x04 0x38 0x04 0x39 0x04 0x3a>;
  883. clock-names = "master\0sleep\0mock_utmi";
  884. qca,host = <0x01>;
  885. status = "ok";
  886.  
  887. dwc3@8a00000 {
  888. compatible = "snps,dwc3";
  889. reg = <0x8a00000 0xf8000>;
  890. interrupts = <0x00 0x84 0x00>;
  891. #phy-cells = <0x00>;
  892. phys = <0x16 0x17>;
  893. phy-names = "usb2-phy\0usb3-phy";
  894. tx-fifo-resize;
  895. dr_mode = "host";
  896. usb2-susphy-quirk;
  897. usb2-host-discon-quirk;
  898. usb2-host-discon-phy-misc-reg = <0x24>;
  899. usb2-host-discon-mask = <0x100>;
  900. };
  901. };
  902.  
  903. usb2@6000000 {
  904. compatible = "qcom,dwc3";
  905. #address-cells = <0x01>;
  906. #size-cells = <0x01>;
  907. ranges;
  908. reg = <0x60f8800 0x100>;
  909. reg-names = "qscratch_base";
  910. clocks = <0x04 0x35 0x04 0x36 0x04 0x37>;
  911. clock-names = "master\0sleep\0mock_utmi";
  912. qca,host = <0x01>;
  913. status = "ok";
  914.  
  915. dwc3@6000000 {
  916. compatible = "snps,dwc3";
  917. reg = <0x6000000 0xf8000>;
  918. interrupts = <0x00 0x88 0x00>;
  919. #phy-cells = <0x00>;
  920. phys = <0x18>;
  921. phy-names = "usb2-phy";
  922. tx-fifo-resize;
  923. dr_mode = "host";
  924. usb2-susphy-quirk;
  925. usb2-host-discon-quirk;
  926. usb2-host-discon-phy-misc-reg = <0x24>;
  927. usb2-host-discon-mask = <0x100>;
  928. };
  929. };
  930.  
  931. dma@7984000 {
  932. compatible = "qcom,bam-v1.7.0";
  933. reg = <0x7984000 0x1a000>;
  934. interrupts = <0x00 0x65 0x00>;
  935. clocks = <0x04 0x2d>;
  936. clock-names = "bam_clk";
  937. #dma-cells = <0x01>;
  938. qcom,ee = <0x00>;
  939. status = "ok";
  940. linux,phandle = <0x1a>;
  941. phandle = <0x1a>;
  942. };
  943.  
  944. ess-switch@c000000 {
  945. compatible = "qcom,ess-switch";
  946. reg = <0xc000000 0x80000>;
  947. switch_access_mode = "local bus";
  948. resets = <0x04 0x1d 0x04 0x4e 0x04 0x4f 0x04 0x50 0x04 0x51 0x04 0x52>;
  949. reset-names = "ess_rst\0ess_mac1_clk_dis\0ess_mac2_clk_dis\0ess_mac3_clk_dis\0ess_mac4_clk_dis\0ess_mac5_clk_dis";
  950. clocks = <0x04 0x24>;
  951. clock-names = "ess_clk";
  952. switch_cpu_bmp = <0x01>;
  953. switch_lan_bmp = <0x1e>;
  954. switch_wan_bmp = <0x20>;
  955. switch_mac_mode = <0x00>;
  956. switch_initvlas = <0x7c 0x54>;
  957.  
  958. led_source@0 {
  959. led = <0x03>;
  960. source = <0x01>;
  961. mode = "normal";
  962. speed = "all";
  963. freq = "auto";
  964. };
  965.  
  966. led_source@1 {
  967. led = <0x04>;
  968. source = <0x04>;
  969. mode = "normal";
  970. speed = "all";
  971. freq = "auto";
  972. };
  973.  
  974. led_source@2 {
  975. led = <0x05>;
  976. source = <0x07>;
  977. mode = "normal";
  978. speed = "all";
  979. freq = "auto";
  980. };
  981.  
  982. led_source@3 {
  983. led = <0x06>;
  984. source = <0x0a>;
  985. mode = "normal";
  986. speed = "all";
  987. freq = "auto";
  988. };
  989.  
  990. led_source@4 {
  991. led = <0x07>;
  992. source = <0x0d>;
  993. mode = "normal";
  994. speed = "all";
  995. freq = "auto";
  996. };
  997. };
  998.  
  999. ess-psgmii@98000 {
  1000. compatible = "qcom,ess-psgmii";
  1001. reg = <0x98000 0x800>;
  1002. psgmii_access_mode = "local bus";
  1003. resets = <0x04 0x4d>;
  1004. reset-names = "psgmii_rst";
  1005. };
  1006.  
  1007. mdio@90000 {
  1008. #address-cells = <0x01>;
  1009. #size-cells = <0x01>;
  1010. compatible = "qcom,ipq40xx-mdio";
  1011. reg = <0x90000 0x64>;
  1012. status = "ok";
  1013. pinctrl-0 = <0x19>;
  1014. pinctrl-names = "default";
  1015. phy-reset-gpio = <0x0d 0x2f 0x00>;
  1016. bias-disable;
  1017.  
  1018. ethernet-phy@0 {
  1019. reg = <0x00>;
  1020. };
  1021.  
  1022. ethernet-phy@1 {
  1023. reg = <0x01>;
  1024. };
  1025.  
  1026. ethernet-phy@2 {
  1027. reg = <0x02>;
  1028. };
  1029.  
  1030. ethernet-phy@3 {
  1031. reg = <0x03>;
  1032. };
  1033.  
  1034. ethernet-phy@4 {
  1035. reg = <0x04>;
  1036. };
  1037. };
  1038.  
  1039. qpic-nand@79b0000 {
  1040. compatible = "qcom,ebi2-nandc-bam\0qcom,msm-nand";
  1041. reg = <0x79b0000 0x1000>;
  1042. #address-cells = <0x01>;
  1043. #size-cells = <0x00>;
  1044. clocks = <0x04 0x2d 0x04 0x2c>;
  1045. clock-names = "core\0aon";
  1046. dmas = <0x1a 0x00 0x1a 0x01 0x1a 0x02>;
  1047. dma-names = "tx\0rx\0cmd";
  1048. status = "ok";
  1049. pinctrl-0 = <0x1b>;
  1050. pinctrl-names = "default";
  1051.  
  1052. nandcs@0 {
  1053. compatible = "qcom,nandcs";
  1054. reg = <0x00>;
  1055. #address-cells = <0x01>;
  1056. #size-cells = <0x01>;
  1057. nand-ecc-strength = <0x04>;
  1058. nand-ecc-step-size = <0x200>;
  1059. nand-bus-width = <0x08>;
  1060. };
  1061. };
  1062.  
  1063. tcsr@1949000 {
  1064. compatible = "ipq,tcsr";
  1065. reg = <0x1949000 0x100>;
  1066. ipq,wifi_glb_cfg = <0x41000000>;
  1067. };
  1068.  
  1069. tcsr@1957000 {
  1070. compatible = "ipq,tcsr";
  1071. reg = <0x1957000 0x100>;
  1072. ipq,wifi_noc_memtype_m0_m2 = <0x2222222>;
  1073. };
  1074.  
  1075. wifi@a000000 {
  1076. compatible = "qca,wifi-ipq40xx";
  1077. reg = <0xa000000 0x200000>;
  1078. core-id = <0x00>;
  1079. resets = <0x04 0x00 0x04 0x01 0x04 0x02 0x04 0x03 0x04 0x04 0x04 0x05>;
  1080. reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
  1081. clocks = <0x04 0x3b 0x04 0x3c 0x04 0x3d>;
  1082. clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
  1083. interrupts = <0x00 0x20 0x01 0x00 0x21 0x01 0x00 0x22 0x01 0x00 0x23 0x01 0x00 0x24 0x01 0x00 0x25 0x01 0x00 0x26 0x01 0x00 0x27 0x01 0x00 0x28 0x01 0x00 0x29 0x01 0x00 0x2a 0x01 0x00 0x2b 0x01 0x00 0x2c 0x01 0x00 0x2d 0x01 0x00 0x2e 0x01 0x00 0x2f 0x01 0x00 0xa8 0x00>;
  1084. interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
  1085. status = "ok";
  1086. qca,msi_addr = <0xb006040>;
  1087. qca,msi_base = <0x40>;
  1088. wifi_led_num = <0x02>;
  1089. wifi_led_source = <0x00>;
  1090. };
  1091.  
  1092. wifi@a800000 {
  1093. compatible = "qca,wifi-ipq40xx";
  1094. reg = <0xa800000 0x200000>;
  1095. core-id = <0x01>;
  1096. resets = <0x04 0x06 0x04 0x07 0x04 0x08 0x04 0x09 0x04 0x0a 0x04 0x0b>;
  1097. reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
  1098. clocks = <0x04 0x3e 0x04 0x3f 0x04 0x40>;
  1099. clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
  1100. interrupts = <0x00 0x30 0x01 0x00 0x31 0x01 0x00 0x32 0x01 0x00 0x33 0x01 0x00 0x34 0x01 0x00 0x35 0x01 0x00 0x36 0x01 0x00 0x37 0x01 0x00 0x38 0x01 0x00 0x39 0x01 0x00 0x3a 0x01 0x00 0x3b 0x01 0x00 0x3c 0x01 0x00 0x3d 0x01 0x00 0x3e 0x01 0x00 0x3f 0x01 0x00 0xa9 0x00>;
  1101. interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
  1102. status = "ok";
  1103. qca,msi_addr = <0xb006040>;
  1104. qca,msi_base = <0x50>;
  1105. wifi_led_num = <0x01>;
  1106. wifi_led_source = <0x02>;
  1107. };
  1108.  
  1109. qcom,msm-imem@86074b0 {
  1110. compatible = "qcom,msm-imem";
  1111. reg = <0x86074b0 0xa50>;
  1112. ranges = <0x00 0x86074b0 0xa50>;
  1113. #address-cells = <0x01>;
  1114. #size-cells = <0x01>;
  1115.  
  1116. mem_dump_table@10 {
  1117. compatible = "qcom,msm-imem-mem_dump_table";
  1118. reg = <0x10 0x08>;
  1119. };
  1120.  
  1121. dload_type@18 {
  1122. compatible = "qcom,msm-imem-dload-type";
  1123. reg = <0x18 0x04>;
  1124. };
  1125.  
  1126. restart_reason@65c {
  1127. compatible = "qcom,msm-imem-restart_reason";
  1128. reg = <0x65c 0x04>;
  1129. };
  1130.  
  1131. boot_stats@6b0 {
  1132. compatible = "qcom,msm-imem-boot_stats";
  1133. reg = <0x6b0 0x20>;
  1134. };
  1135.  
  1136. pil@94c {
  1137. compatible = "qcom,msm-imem-pil";
  1138. reg = <0x94c 0xc8>;
  1139. };
  1140. };
  1141.  
  1142. qcom_mdss_qpic@7980000 {
  1143. compatible = "qcom,mdss_qpic";
  1144. reg = <0x7980000 0x24000>;
  1145. interrupts = <0x00 0x6a 0x00>;
  1146. clocks = <0x04 0x2d 0x04 0x2c>;
  1147. clock-names = "core\0aon";
  1148. dmas = <0x1a 0x06>;
  1149. dma-names = "chan";
  1150. status = "ok";
  1151. };
  1152.  
  1153. qcom_mdss_qpic_panel {
  1154. compatible = "qcom,mdss-qpic-panel";
  1155. label = "qpic lcd panel";
  1156. qcom,mdss-pan-res = <0x320 0x1e0>;
  1157. qcom,mdss-pan-bpp = <0x12>;
  1158. qcom,refresh_rate = <0x3c>;
  1159. status = "ok";
  1160. };
  1161.  
  1162. edma@c080000 {
  1163. compatible = "qcom,ess-edma";
  1164. reg = <0xc080000 0x8000>;
  1165. qcom,page-mode = <0x00>;
  1166. qcom,rx-head-buf-size = <0x604>;
  1167. qcom,num-gmac = <0x02>;
  1168. qcom,mdio-supported;
  1169. interrupts = <0x00 0x41 0x01 0x00 0x42 0x01 0x00 0x43 0x01 0x00 0x44 0x01 0x00 0x45 0x01 0x00 0x46 0x01 0x00 0x47 0x01 0x00 0x48 0x01 0x00 0x49 0x01 0x00 0x4a 0x01 0x00 0x4b 0x01 0x00 0x4c 0x01 0x00 0x4d 0x01 0x00 0x4e 0x01 0x00 0x4f 0x01 0x00 0x50 0x01 0x00 0xf0 0x01 0x00 0xf1 0x01 0x00 0xf2 0x01 0x00 0xf3 0x01 0x00 0xf4 0x01 0x00 0xf5 0x01 0x00 0xf6 0x01 0x00 0xf7 0x01 0x00 0xf8 0x01 0x00 0xf9 0x01 0x00 0xfa 0x01 0x00 0xfb 0x01 0x00 0xfc 0x01 0x00 0xfd 0x01 0x00 0xfe 0x01 0x00 0xff 0x01>;
  1170.  
  1171. gmac0 {
  1172. local-mac-address = [00 00 00 00 00 00];
  1173. qcom,phy-mdio-addr = <0x03>;
  1174. qcom,poll-required = <0x01>;
  1175. qcom,poll-required-dynamic = <0x01>;
  1176. qcom,forced-speed = <0x3e8>;
  1177. qcom,forced-duplex = <0x01>;
  1178. vlan-tag = <0x01 0x1e>;
  1179. };
  1180.  
  1181. gmac1 {
  1182. local-mac-address = [00 00 00 00 00 00];
  1183. qcom,phy-mdio-addr = <0x04>;
  1184. qcom,poll-required = <0x01>;
  1185. qcom,poll-required-dynamic = <0x01>;
  1186. qcom,forced-speed = <0x3e8>;
  1187. qcom,forced-duplex = <0x01>;
  1188. vlan-tag = <0x02 0x20>;
  1189. };
  1190. };
  1191.  
  1192. qcom,ipc_router {
  1193. compatible = "qcom,ipc_router";
  1194. qcom,node-id = <0x01>;
  1195. };
  1196.  
  1197. wifi3@f00000 {
  1198. compatible = "qcom,cnss-qca6290";
  1199. qcom,mhi = <0x1c>;
  1200. qcom,wlan-ramdump-dynamic = <0x400000>;
  1201. status = "ok";
  1202. };
  1203.  
  1204. qcom,mhi {
  1205. compatible = "qcom,mhi";
  1206. };
  1207.  
  1208. qcom,mhi@1 {
  1209. compatible = "qcom,mhi";
  1210. qcom,pci-dev_id = <0x1100>;
  1211. qcom,pci-domain = <0x00>;
  1212. qcom,pci-bus = <0x01>;
  1213. qcom,pci-slot = <0x00>;
  1214. qcom,mhi-address-window = <0x00 0x80000000 0x01 0xffffffff>;
  1215. qcom,mhi-ready-timeout = <0x927c0>;
  1216. qcom,bhi-poll-timeout = <0x927c0>;
  1217. qcom,bhi-alignment = <0x40000>;
  1218. qcom,mhi-manage-boot;
  1219. qcom,mhi-fw-image = "amss.bin";
  1220. qcom,mhi-max-sbl = <0x40000>;
  1221. qcom,mhi-sg-size = <0x80000>;
  1222. mhi-chan-cfg-0 = <0x00 0x80 0x01 0x92>;
  1223. mhi-chan-cfg-1 = <0x01 0x80 0x01 0xa2>;
  1224. mhi-chan-cfg-4 = <0x04 0x80 0x01 0x92>;
  1225. mhi-chan-cfg-5 = <0x05 0x80 0x01 0xa2>;
  1226. mhi-chan-cfg-16 = <0x10 0x40 0x01 0x92>;
  1227. mhi-chan-cfg-17 = <0x11 0x40 0x01 0xa2>;
  1228. mhi-event-rings = <0x02>;
  1229. mhi-event-cfg-0 = <0x0a 0x00 0x01 0x00 0x01 0x31>;
  1230. mhi-event-cfg-1 = <0x80 0x01 0x01 0x00 0x01 0x31>;
  1231. linux,phandle = <0x1c>;
  1232. phandle = <0x1c>;
  1233. };
  1234.  
  1235. qcom,ipc_router_external_wlan_xprt {
  1236. compatible = "qcom,ipc_router_mhi_xprt";
  1237. qcom,mhi = <0x1c>;
  1238. qcom,out-chan-id = <0x10>;
  1239. qcom,in-chan-id = <0x11>;
  1240. qcom,xprt-remote = "external-wlan";
  1241. qcom,xprt-linkid = <0x01>;
  1242. qcom,xprt-version = <0x03>;
  1243. };
  1244.  
  1245. qcom,diag@0 {
  1246. compatible = "qcom,diag";
  1247. qcom,mhi = <0x1c>;
  1248. status = "ok";
  1249. };
  1250.  
  1251. regulator@0 {
  1252. compatible = "qcom,regulator-ipq40xx";
  1253. regulator-name = "SD0 VccQ";
  1254. regulator-min-microvolt = <0x1b7740>;
  1255. regulator-max-microvolt = <0x2dc6c0>;
  1256. states = <0x2dc6c0 0x03 0x1b7740 0x01>;
  1257. reg = <0x1948000 0x04>;
  1258. mask = <0x03>;
  1259. linux,phandle = <0x15>;
  1260. phandle = <0x15>;
  1261. };
  1262.  
  1263. gpio_keys {
  1264. compatible = "gpio-keys";
  1265.  
  1266. button@1 {
  1267. label = "wps";
  1268. linux,code = <0x211>;
  1269. gpios = <0x0d 0x12 0x01>;
  1270. linux,input-type = <0x01>;
  1271. };
  1272. };
  1273. };
  1274.  
  1275. reserved-memory {
  1276. #address-cells = <0x01>;
  1277. #size-cells = <0x01>;
  1278. ranges;
  1279.  
  1280. rsvd1@87000000 {
  1281. reg = <0x87000000 0x500000>;
  1282. no-map;
  1283. };
  1284.  
  1285. wifi_dump@87500000 {
  1286. reg = <0x87500000 0x600000>;
  1287. no-map;
  1288. };
  1289.  
  1290. rsvd2@87B00000 {
  1291. reg = <0x87b00000 0x500000>;
  1292. no-map;
  1293. };
  1294. };
  1295. };
  1296.  
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