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Tesla HW4 DTS

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  1. /dts-v1/;
  2.  
  3. / {
  4. compatible = "tesla,fsd\0tesla,fsd-hw4";
  5. interrupt-parent = <0x01>;
  6. #address-cells = <0x02>;
  7. #size-cells = <0x02>;
  8. model = "Tesla DAS HW4.0";
  9.  
  10. aliases {
  11. pinctrl0 = "/soc/pinctrl@250F0000";
  12. pinctrl1 = "/soc/pinctrl@7FCD0000";
  13. watchdog0 = "/soc/watchdog@25C80000";
  14. spi0 = "/soc/spi@25100000";
  15. spi1 = "/soc/spi@25110000";
  16. spi2 = "/soc/spi@25140000";
  17. spi3 = "/soc/spi@25170000";
  18. spi4 = "/soc/spi@25180000";
  19. tdm0 = "/soc/tdm@250C0000";
  20. tdm1 = "/soc/tdm@250D0000";
  21. pcierc0 = "/soc/pcie@7F800000";
  22. pcieep0 = "/soc/pcie_ep@7F800000";
  23. pcierc1 = "/soc/pcie@7F900000";
  24. pcieep1 = "/soc/pcie_ep@7F900000";
  25. pcierc2 = "/soc/pcie@7FA00000";
  26. pcieep2 = "/soc/pcie_ep@7FA00000";
  27. pcierc3 = "/soc/pcie@7FB00000";
  28. pcieep3 = "/soc/pcie_ep@7FB00000";
  29. pciephy0 = "/soc/pcie-phy@7FC60000";
  30. pciephy1 = "/soc/pcie-phy@7FC70000";
  31. eth0 = "/soc/ethernet@7f700000";
  32. eth1 = "/soc/ethernet@25300000";
  33. mali0 = "/soc/mali0@27100000";
  34. mali1 = "/soc/mali1@27500000";
  35. csis0 = "/soc/csis0@23040000";
  36. csis1 = "/soc/csis1@23050000";
  37. csis2 = "/soc/csis2@23060000";
  38. isp0 = "/soc/isp@0x22840000";
  39. isp1 = "/soc/isp@0x22C40000";
  40. serial0 = "/soc/serial@250A0000";
  41. serial1 = "/soc/serial@25080000";
  42. serial2 = "/soc/serial@25090000";
  43. };
  44.  
  45. cpus {
  46. #address-cells = <0x02>;
  47. #size-cells = <0x00>;
  48.  
  49. cpu-map {
  50.  
  51. cluster0 {
  52.  
  53. core0 {
  54. cpu = <0x02>;
  55. };
  56.  
  57. core1 {
  58. cpu = <0x03>;
  59. };
  60.  
  61. core2 {
  62. cpu = <0x04>;
  63. };
  64.  
  65. core3 {
  66. cpu = <0x05>;
  67. };
  68. };
  69.  
  70. cluster1 {
  71.  
  72. core0 {
  73. cpu = <0x06>;
  74. };
  75.  
  76. core1 {
  77. cpu = <0x07>;
  78. };
  79.  
  80. core2 {
  81. cpu = <0x08>;
  82. };
  83.  
  84. core3 {
  85. cpu = <0x09>;
  86. };
  87. };
  88.  
  89. cluster2 {
  90.  
  91. core0 {
  92. cpu = <0x0a>;
  93. };
  94.  
  95. core1 {
  96. cpu = <0x0b>;
  97. };
  98.  
  99. core2 {
  100. cpu = <0x0c>;
  101. };
  102.  
  103. core3 {
  104. cpu = <0x0d>;
  105. };
  106. };
  107.  
  108. cluster3 {
  109.  
  110. core0 {
  111. cpu = <0x0e>;
  112. };
  113.  
  114. core1 {
  115. cpu = <0x0f>;
  116. };
  117.  
  118. core2 {
  119. cpu = <0x10>;
  120. };
  121.  
  122. core3 {
  123. cpu = <0x11>;
  124. };
  125. };
  126.  
  127. cluster4 {
  128.  
  129. core0 {
  130. cpu = <0x12>;
  131. };
  132.  
  133. core1 {
  134. cpu = <0x13>;
  135. };
  136.  
  137. core2 {
  138. cpu = <0x14>;
  139. };
  140.  
  141. core3 {
  142. cpu = <0x15>;
  143. };
  144. };
  145. };
  146.  
  147. cpu@000000 {
  148. device_type = "cpu";
  149. compatible = "arm,armv8";
  150. reg = <0x00 0x00>;
  151. enable-method = "psci";
  152. cpu-idle-states = <0x16>;
  153. next-level-cache = <0x17>;
  154. clocks = <0x18 0x05>;
  155. clock-names = "cpu_coreclk0_0";
  156. cpu-supply = <0x19>;
  157. operating-points-v2 = <0x1a>;
  158. #cooling-cells = <0x02>;
  159. phandle = <0x02>;
  160. };
  161.  
  162. cpu@000100 {
  163. device_type = "cpu";
  164. compatible = "arm,armv8";
  165. reg = <0x00 0x100>;
  166. enable-method = "psci";
  167. cpu-idle-states = <0x16>;
  168. next-level-cache = <0x17>;
  169. clocks = <0x18 0x92>;
  170. clock-names = "cpu_coreclk0_1";
  171. cpu-supply = <0x19>;
  172. operating-points-v2 = <0x1a>;
  173. phandle = <0x03>;
  174. };
  175.  
  176. cpu@000200 {
  177. device_type = "cpu";
  178. compatible = "arm,armv8";
  179. reg = <0x00 0x200>;
  180. enable-method = "psci";
  181. cpu-idle-states = <0x16>;
  182. next-level-cache = <0x17>;
  183. clocks = <0x18 0x93>;
  184. clock-names = "cpu_coreclk0_2";
  185. cpu-supply = <0x19>;
  186. operating-points-v2 = <0x1a>;
  187. phandle = <0x04>;
  188. };
  189.  
  190. cpu@000300 {
  191. device_type = "cpu";
  192. compatible = "arm,armv8";
  193. reg = <0x00 0x300>;
  194. enable-method = "psci";
  195. cpu-idle-states = <0x16>;
  196. next-level-cache = <0x17>;
  197. clocks = <0x18 0x94>;
  198. clock-names = "cpu_coreclk0_3";
  199. cpu-supply = <0x19>;
  200. operating-points-v2 = <0x1a>;
  201. phandle = <0x05>;
  202. };
  203.  
  204. cpu@010000 {
  205. device_type = "cpu";
  206. compatible = "arm,armv8";
  207. reg = <0x00 0x10000>;
  208. enable-method = "psci";
  209. cpu-idle-states = <0x16>;
  210. next-level-cache = <0x17>;
  211. clocks = <0x18 0x06>;
  212. clock-names = "cpu_coreclk1_0";
  213. cpu-supply = <0x19>;
  214. operating-points-v2 = <0x1a>;
  215. phandle = <0x06>;
  216. };
  217.  
  218. cpu@010100 {
  219. device_type = "cpu";
  220. compatible = "arm,armv8";
  221. reg = <0x00 0x10100>;
  222. enable-method = "psci";
  223. cpu-idle-states = <0x16>;
  224. next-level-cache = <0x17>;
  225. clocks = <0x18 0x91>;
  226. clock-names = "cpu_coreclk1_1";
  227. cpu-supply = <0x19>;
  228. operating-points-v2 = <0x1a>;
  229. phandle = <0x07>;
  230. };
  231.  
  232. cpu@010200 {
  233. device_type = "cpu";
  234. compatible = "arm,armv8";
  235. reg = <0x00 0x10200>;
  236. enable-method = "psci";
  237. cpu-idle-states = <0x16>;
  238. next-level-cache = <0x17>;
  239. clocks = <0x18 0xa0>;
  240. clock-names = "cpu_coreclk1_2";
  241. cpu-supply = <0x19>;
  242. operating-points-v2 = <0x1a>;
  243. phandle = <0x08>;
  244. };
  245.  
  246. cpu@010300 {
  247. device_type = "cpu";
  248. compatible = "arm,armv8";
  249. reg = <0x00 0x10300>;
  250. enable-method = "psci";
  251. cpu-idle-states = <0x16>;
  252. next-level-cache = <0x17>;
  253. clocks = <0x18 0x66>;
  254. clock-names = "cpu_coreclk1_3";
  255. cpu-supply = <0x19>;
  256. operating-points-v2 = <0x1a>;
  257. phandle = <0x09>;
  258. };
  259.  
  260. cpu@020000 {
  261. device_type = "cpu";
  262. compatible = "arm,armv8";
  263. reg = <0x00 0x20000>;
  264. enable-method = "psci";
  265. cpu-idle-states = <0x16>;
  266. next-level-cache = <0x17>;
  267. clocks = <0x18 0x07>;
  268. clock-names = "cpu_coreclk2_0";
  269. cpu-supply = <0x19>;
  270. operating-points-v2 = <0x1a>;
  271. phandle = <0x0a>;
  272. };
  273.  
  274. cpu@020100 {
  275. device_type = "cpu";
  276. compatible = "arm,armv8";
  277. reg = <0x00 0x20100>;
  278. enable-method = "psci";
  279. cpu-idle-states = <0x16>;
  280. next-level-cache = <0x17>;
  281. clocks = <0x18 0x5e>;
  282. clock-names = "cpu_coreclk2_1";
  283. cpu-supply = <0x19>;
  284. operating-points-v2 = <0x1a>;
  285. phandle = <0x0b>;
  286. };
  287.  
  288. cpu@020200 {
  289. device_type = "cpu";
  290. compatible = "arm,armv8";
  291. reg = <0x00 0x20200>;
  292. enable-method = "psci";
  293. cpu-idle-states = <0x16>;
  294. next-level-cache = <0x17>;
  295. clocks = <0x18 0x5f>;
  296. clock-names = "cpu_coreclk2_2";
  297. cpu-supply = <0x19>;
  298. operating-points-v2 = <0x1a>;
  299. phandle = <0x0c>;
  300. };
  301.  
  302. cpu@020300 {
  303. device_type = "cpu";
  304. compatible = "arm,armv8";
  305. reg = <0x00 0x20300>;
  306. enable-method = "psci";
  307. cpu-idle-states = <0x16>;
  308. next-level-cache = <0x17>;
  309. clocks = <0x18 0x60>;
  310. clock-names = "cpu_coreclk2_3";
  311. cpu-supply = <0x19>;
  312. operating-points-v2 = <0x1a>;
  313. phandle = <0x0d>;
  314. };
  315.  
  316. cpu@030000 {
  317. device_type = "cpu";
  318. compatible = "arm,armv8";
  319. reg = <0x00 0x30000>;
  320. enable-method = "psci";
  321. cpu-idle-states = <0x16>;
  322. next-level-cache = <0x17>;
  323. clocks = <0x1b 0x03>;
  324. clock-names = "cpu_coreclk3_0";
  325. cpu-supply = <0x19>;
  326. operating-points-v2 = <0x1a>;
  327. phandle = <0x0e>;
  328. };
  329.  
  330. cpu@030100 {
  331. device_type = "cpu";
  332. compatible = "arm,armv8";
  333. reg = <0x00 0x30100>;
  334. enable-method = "psci";
  335. cpu-idle-states = <0x16>;
  336. next-level-cache = <0x17>;
  337. clocks = <0x1b 0x45>;
  338. clock-names = "cpu_coreclk3_1";
  339. cpu-supply = <0x19>;
  340. operating-points-v2 = <0x1a>;
  341. phandle = <0x0f>;
  342. };
  343.  
  344. cpu@030200 {
  345. device_type = "cpu";
  346. compatible = "arm,armv8";
  347. reg = <0x00 0x30200>;
  348. enable-method = "psci";
  349. cpu-idle-states = <0x16>;
  350. next-level-cache = <0x17>;
  351. clocks = <0x1b 0x49>;
  352. clock-names = "cpu_coreclk3_2";
  353. cpu-supply = <0x19>;
  354. operating-points-v2 = <0x1a>;
  355. phandle = <0x10>;
  356. };
  357.  
  358. cpu@030300 {
  359. device_type = "cpu";
  360. compatible = "arm,armv8";
  361. reg = <0x00 0x30300>;
  362. enable-method = "psci";
  363. cpu-idle-states = <0x16>;
  364. next-level-cache = <0x17>;
  365. clocks = <0x1b 0x47>;
  366. clock-names = "cpu_coreclk3_3";
  367. cpu-supply = <0x19>;
  368. operating-points-v2 = <0x1a>;
  369. phandle = <0x11>;
  370. };
  371.  
  372. cpu@040000 {
  373. device_type = "cpu";
  374. compatible = "arm,armv8";
  375. reg = <0x00 0x40000>;
  376. enable-method = "psci";
  377. cpu-idle-states = <0x16>;
  378. next-level-cache = <0x17>;
  379. clocks = <0x1b 0x04>;
  380. clock-names = "cpu_coreclk4_0";
  381. cpu-supply = <0x19>;
  382. operating-points-v2 = <0x1a>;
  383. phandle = <0x12>;
  384. };
  385.  
  386. cpu@040100 {
  387. device_type = "cpu";
  388. compatible = "arm,armv8";
  389. reg = <0x00 0x40100>;
  390. enable-method = "psci";
  391. cpu-idle-states = <0x16>;
  392. next-level-cache = <0x17>;
  393. clocks = <0x1b 0x4c>;
  394. clock-names = "cpu_coreclk4_1";
  395. cpu-supply = <0x19>;
  396. operating-points-v2 = <0x1a>;
  397. phandle = <0x13>;
  398. };
  399.  
  400. cpu@040200 {
  401. device_type = "cpu";
  402. compatible = "arm,armv8";
  403. reg = <0x00 0x40200>;
  404. enable-method = "psci";
  405. cpu-idle-states = <0x16>;
  406. next-level-cache = <0x17>;
  407. clocks = <0x1b 0x4f>;
  408. clock-names = "cpu_coreclk4_0";
  409. cpu-supply = <0x19>;
  410. operating-points-v2 = <0x1a>;
  411. phandle = <0x14>;
  412. };
  413.  
  414. cpu@040300 {
  415. device_type = "cpu";
  416. compatible = "arm,armv8";
  417. reg = <0x00 0x40300>;
  418. enable-method = "psci";
  419. cpu-idle-states = <0x16>;
  420. next-level-cache = <0x17>;
  421. clocks = <0x1b 0x50>;
  422. clock-names = "cpu_coreclk4_3";
  423. cpu-supply = <0x19>;
  424. operating-points-v2 = <0x1a>;
  425. phandle = <0x15>;
  426. };
  427.  
  428. idle-states {
  429. entry-method = "psci";
  430.  
  431. cpu-sleep {
  432. idle-state-name = "c2";
  433. compatible = "arm,idle-state";
  434. local-timer-stop;
  435. arm,psci-suspend-param = <0x10000>;
  436. entry-latency-us = <0x82>;
  437. exit-latency-us = <0x96>;
  438. min-residency-us = <0x7d0>;
  439. status = "disabled";
  440. phandle = <0x16>;
  441. };
  442. };
  443.  
  444. l2-cache0 {
  445. compatible = "cache";
  446. next-level-cache = <0x1c>;
  447. phandle = <0x17>;
  448. };
  449.  
  450. l3-cache0 {
  451. compatible = "cache";
  452. phandle = <0x1c>;
  453. };
  454.  
  455. opp_table0 {
  456. compatible = "operating-points-v2";
  457. opp-shared;
  458. phandle = <0x1a>;
  459.  
  460. opp00 {
  461. opp-hz = <0x00 0x8c184200>;
  462. opp-microvolt = <0xe57e0>;
  463. opp-microvolt-asv1 = <0xdf638>;
  464. opp-microvolt-asv2 = <0xd9490>;
  465. opp-microvolt-asv3 = <0xd4670>;
  466. opp-microvolt-asv4 = <0xcf850>;
  467. clock-latency-ns = <0x30d40>;
  468. };
  469.  
  470. opp01 {
  471. opp-hz = <0x00 0x701abb00>;
  472. opp-microvolt = <0xc5c10>;
  473. opp-microvolt-asv1 = <0xc2178>;
  474. opp-microvolt-asv2 = <0xbe6e0>;
  475. opp-microvolt-asv3 = <0xbac48>;
  476. opp-microvolt-asv4 = <0xb71b0>;
  477. clock-latency-ns = <0x30d40>;
  478. };
  479.  
  480. opp02 {
  481. opp-hz = <0x00 0x51ab97c0>;
  482. opp-microvolt = <0xb8538>;
  483. opp-microvolt-asv1 = <0xae8f8>;
  484. opp-microvolt-asv2 = <0xaae60>;
  485. opp-microvolt-asv3 = <0xa73c8>;
  486. opp-microvolt-asv4 = <0xa3930>;
  487. clock-latency-ns = <0x30d40>;
  488. };
  489. };
  490. };
  491.  
  492. trip0_opp_table {
  493. compatible = "operating-points-v2";
  494. phandle = <0x89>;
  495.  
  496. opp-2200000000 {
  497. opp-hz = <0x00 0x836a9400>;
  498. opp-microvolt = <0xd32e8 0xd32e8 0xe1d48>;
  499. opp-microvolt-asv1 = <0xce4c8 0xce4c8 0xdbba0>;
  500. opp-microvolt-asv2 = <0xc96a8 0xc96a8 0xd59f8>;
  501. opp-microvolt-asv3 = <0xc4888 0xc4888 0xcf850>;
  502. opp-microvolt-asv4 = <0xbfa68 0xbfa68 0xc96a8>;
  503. clock-latency-ns = <0x30d40>;
  504. };
  505.  
  506. opp-2000000000 {
  507. opp-hz = <0x00 0x7704c000>;
  508. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  509. opp-microvolt-asv1 = <0xc8320 0xc8320 0xdbba0>;
  510. opp-microvolt-asv2 = <0xc2178 0xc2178 0xd59f8>;
  511. opp-microvolt-asv3 = <0xbbfd0 0xbbfd0 0xcf850>;
  512. opp-microvolt-asv4 = <0xb5e28 0xb5e28 0xc96a8>;
  513. clock-latency-ns = <0x30d40>;
  514. };
  515.  
  516. opp-1800000000 {
  517. opp-hz = <0x00 0x6b8cf580>;
  518. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  519. opp-microvolt-asv1 = <0xc6f98 0xc6f98 0xdbba0>;
  520. opp-microvolt-asv2 = <0xbe6e0 0xbe6e0 0xd59f8>;
  521. opp-microvolt-asv3 = <0xb71b0 0xb71b0 0xcf850>;
  522. opp-microvolt-asv4 = <0xafc80 0xafc80 0xc96a8>;
  523. clock-latency-ns = <0x30d40>;
  524. };
  525. };
  526.  
  527. trip1_opp_table {
  528. compatible = "operating-points-v2";
  529. phandle = <0x8d>;
  530.  
  531. opp-2200000000 {
  532. opp-hz = <0x00 0x836a9400>;
  533. opp-microvolt = <0xd32e8 0xd32e8 0xe1d48>;
  534. opp-microvolt-asv1 = <0xce4c8 0xce4c8 0xdbba0>;
  535. opp-microvolt-asv2 = <0xc96a8 0xc96a8 0xd59f8>;
  536. opp-microvolt-asv3 = <0xc4888 0xc4888 0xcf850>;
  537. opp-microvolt-asv4 = <0xbfa68 0xbfa68 0xc96a8>;
  538. clock-latency-ns = <0x30d40>;
  539. };
  540.  
  541. opp-2000000000 {
  542. opp-hz = <0x00 0x7704c000>;
  543. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  544. opp-microvolt-asv1 = <0xc8320 0xc8320 0xdbba0>;
  545. opp-microvolt-asv2 = <0xc2178 0xc2178 0xd59f8>;
  546. opp-microvolt-asv3 = <0xbbfd0 0xbbfd0 0xcf850>;
  547. opp-microvolt-asv4 = <0xb5e28 0xb5e28 0xc96a8>;
  548. clock-latency-ns = <0x30d40>;
  549. };
  550.  
  551. opp-1800000000 {
  552. opp-hz = <0x00 0x6b8cf580>;
  553. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  554. opp-microvolt-asv1 = <0xc6f98 0xc6f98 0xdbba0>;
  555. opp-microvolt-asv2 = <0xbe6e0 0xbe6e0 0xd59f8>;
  556. opp-microvolt-asv3 = <0xb71b0 0xb71b0 0xcf850>;
  557. opp-microvolt-asv4 = <0xafc80 0xafc80 0xc96a8>;
  558. clock-latency-ns = <0x30d40>;
  559. };
  560. };
  561.  
  562. trip2_opp_table {
  563. compatible = "operating-points-v2";
  564. phandle = <0x90>;
  565.  
  566. opp-2200000000 {
  567. opp-hz = <0x00 0x836a9400>;
  568. opp-microvolt = <0xd32e8 0xd32e8 0xe1d48>;
  569. opp-microvolt-asv1 = <0xce4c8 0xce4c8 0xdbba0>;
  570. opp-microvolt-asv2 = <0xc96a8 0xc96a8 0xd59f8>;
  571. opp-microvolt-asv3 = <0xc4888 0xc4888 0xcf850>;
  572. opp-microvolt-asv4 = <0xbfa68 0xbfa68 0xc96a8>;
  573. clock-latency-ns = <0x30d40>;
  574. };
  575.  
  576. opp-2000000000 {
  577. opp-hz = <0x00 0x7704c000>;
  578. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  579. opp-microvolt-asv1 = <0xc8320 0xc8320 0xdbba0>;
  580. opp-microvolt-asv2 = <0xc2178 0xc2178 0xd59f8>;
  581. opp-microvolt-asv3 = <0xbbfd0 0xbbfd0 0xcf850>;
  582. opp-microvolt-asv4 = <0xb5e28 0xb5e28 0xc96a8>;
  583. clock-latency-ns = <0x30d40>;
  584. };
  585.  
  586. opp-1800000000 {
  587. opp-hz = <0x00 0x6b8cf580>;
  588. opp-microvolt = <0xce4c8 0xce4c8 0xe1d48>;
  589. opp-microvolt-asv1 = <0xc6f98 0xc6f98 0xdbba0>;
  590. opp-microvolt-asv2 = <0xbe6e0 0xbe6e0 0xd59f8>;
  591. opp-microvolt-asv3 = <0xb71b0 0xb71b0 0xcf850>;
  592. opp-microvolt-asv4 = <0xafc80 0xafc80 0xc96a8>;
  593. clock-latency-ns = <0x30d40>;
  594. };
  595. };
  596.  
  597. psci {
  598. compatible = "arm,psci-1.0";
  599. method = "smc";
  600. };
  601.  
  602. timer {
  603. compatible = "arm,armv8-timer";
  604. always-on;
  605. interrupts = <0x01 0x0b 0x08 0x01 0x0a 0x08 0x01 0x0c 0x08>;
  606. };
  607.  
  608. fsd_hw4_oscclk {
  609. compatible = "fixed-clock";
  610. clock-output-names = "fsd_hw4_oscclk";
  611. #clock-cells = <0x00>;
  612. clock-frequency = <0x18cba80>;
  613. phandle = <0x2c>;
  614. };
  615.  
  616. div_sgk_1000 {
  617. compatible = "fixed-clock";
  618. clock-output-names = "div_sgk_1000";
  619. #clock-cells = <0x00>;
  620. clock-frequency = <0x3b9aca00>;
  621. phandle = <0x22>;
  622. };
  623.  
  624. clkcmu_isp_main {
  625. compatible = "fixed-clock";
  626. clock-output-names = "clkcmu_isp_main";
  627. #clock-cells = <0x00>;
  628. clock-frequency = <0x47868c00>;
  629. phandle = <0x27>;
  630. };
  631.  
  632. clkcmu_gpu_main {
  633. compatible = "fixed-clock";
  634. clock-output-names = "clkcmu_gpu_main";
  635. #clock-cells = <0x00>;
  636. clock-frequency = <0x3b9aca00>;
  637. phandle = <0x24>;
  638. };
  639.  
  640. clkcmu_lsio_main {
  641. compatible = "fixed-clock";
  642. clock-output-names = "clkcmu_lsio_main";
  643. #clock-cells = <0x00>;
  644. clock-frequency = <0x47868c00>;
  645. phandle = <0x21>;
  646. };
  647.  
  648. clkcmu_mfc_busp {
  649. compatible = "fixed-clock";
  650. clock-output-names = "clkcmu_mfc_busp";
  651. #clock-cells = <0x00>;
  652. clock-frequency = <0x2faf0800>;
  653. phandle = <0x25>;
  654. };
  655.  
  656. clkcmu_imem_main {
  657. compatible = "fixed-clock";
  658. clock-output-names = "clkcmu_imem_main";
  659. #clock-cells = <0x00>;
  660. clock-frequency = <0x47868c00>;
  661. phandle = <0x23>;
  662. };
  663.  
  664. pll_trip_sw {
  665. compatible = "fixed-clock";
  666. clock-output-names = "pll_trip_sw";
  667. #clock-cells = <0x00>;
  668. clock-frequency = <0x77359400>;
  669. phandle = <0x28>;
  670. };
  671.  
  672. clkcmu_csi_main {
  673. compatible = "fixed-clock";
  674. clock-output-names = "clkcmu_csi_main";
  675. #clock-cells = <0x00>;
  676. clock-frequency = <0x2faf0800>;
  677. phandle = <0x26>;
  678. };
  679.  
  680. reserved-memory {
  681. #address-cells = <0x02>;
  682. #size-cells = <0x02>;
  683. ranges;
  684.  
  685. region@F0000000 {
  686. compatible = "shared-dma-pool";
  687. no-map;
  688. reg = <0x00 0xf0000000 0x00 0x4000000>;
  689. phandle = <0xa6>;
  690. };
  691.  
  692. region@fffa0000 {
  693. compatible = "shared-dma-pool";
  694. no-map;
  695. reg = <0x00 0xfffa0000 0x00 0x60000>;
  696. };
  697.  
  698. region@180000000 {
  699. compatible = "shared-dma-pool";
  700. reusable;
  701. reg = <0x01 0x80000000 0x01 0x5e000000>;
  702. alignment = <0x200000>;
  703. phandle = <0x96>;
  704. };
  705.  
  706. region@168000000 {
  707. compatible = "shared-dma-pool";
  708. reusable;
  709. reg = <0x01 0x68000000 0x00 0x18000000>;
  710. alignment = <0x200000>;
  711. phandle = <0x97>;
  712. };
  713.  
  714. region@F4000000 {
  715. compatible = "shared-dma-pool";
  716. no-map;
  717. reg = <0x00 0xf4000000 0x00 0x20000>;
  718. phandle = <0x57>;
  719. };
  720.  
  721. ramoops@80000 {
  722. compatible = "ramoops";
  723. reg = <0x00 0x80000 0x00 0x20000>;
  724. record-size = <0x10000>;
  725. console-size = <0x10000>;
  726. no-dump-oops;
  727. no-map;
  728. };
  729.  
  730. sgk-reserved@f4100000 {
  731. reg = <0x00 0xf4100000 0x00 0x4000000>;
  732. alignment = <0x1000>;
  733. no-map;
  734. };
  735. };
  736.  
  737. fsd_mbox_rtc {
  738. compatible = "tesla,fsd-mailbox-rtc";
  739. status = "okay";
  740. };
  741.  
  742. fsd_mbox_therm {
  743. compatible = "tesla,fsd-hw4-therm";
  744. #thermal-sensor-cells = <0x01>;
  745. status = "okay";
  746. phandle = <0x91>;
  747. };
  748.  
  749. fsd-mailbox-client {
  750. mboxes = <0x1d 0x00 0x1d 0x00 0x1d 0x00 0x1d 0x00 0x1d 0x00>;
  751. mbox-names = "scs_lo\0scs_hi\0sgk\0sms_lo\0sms_hi";
  752. compatible = "tesla,fsd-mailbox-client";
  753. status = "okay";
  754. };
  755.  
  756. soc {
  757. compatible = "simple-bus";
  758. #address-cells = <0x02>;
  759. #size-cells = <0x02>;
  760. ranges;
  761.  
  762. interrupt-controller@25800000 {
  763. compatible = "arm,gic-v3";
  764. #interrupt-cells = <0x03>;
  765. interrupt-controller;
  766. reg = <0x00 0x25800000 0x00 0x10000 0x00 0x25840000 0x00 0x280000>;
  767. phandle = <0x01>;
  768. };
  769.  
  770. serial@25080000 {
  771. compatible = "samsung,exynos4210-uart";
  772. reg = <0x00 0x25080000 0x00 0x100>;
  773. interrupts = <0x00 0xb3 0x04>;
  774. dmas = <0x1e 0x00 0x1e 0x01>;
  775. dma-names = "tx\0rx";
  776. clocks = <0x1f 0x24 0x1f 0x25>;
  777. clock-names = "uart\0clk_uart_baud0";
  778. pinctrl-names = "default";
  779. pinctrl-0 = <0x20>;
  780. low-latency;
  781. status = "okay";
  782. };
  783.  
  784. serial@25090000 {
  785. compatible = "samsung,exynos4210-uart";
  786. reg = <0x00 0x25090000 0x00 0x100>;
  787. interrupts = <0x00 0xb4 0x04>;
  788. clocks = <0x1f 0x26 0x1f 0x27>;
  789. clock-names = "uart\0clk_uart_baud0";
  790. status = "okay";
  791. };
  792.  
  793. serial@250A0000 {
  794. compatible = "samsung,exynos4210-uart";
  795. reg = <0x00 0x250a0000 0x00 0x100>;
  796. interrupts = <0x00 0xb5 0x04>;
  797. clocks = <0x1f 0x28 0x1f 0x29>;
  798. clock-names = "uart\0clk_uart_baud0";
  799. status = "okay";
  800. };
  801.  
  802. pinctrl@250F0000 {
  803. compatible = "tesla,fsd-hw4-pinctrl";
  804. reg = <0x00 0x250f0000 0x00 0x2024>;
  805. interrupts = <0x00 0xca 0x04>;
  806.  
  807. gpu0 {
  808. gpio-controller;
  809. #gpio-cells = <0x02>;
  810. interrupt-controller;
  811. #interrupt-cells = <0x02>;
  812. };
  813.  
  814. gpl0 {
  815. gpio-controller;
  816. #gpio-cells = <0x02>;
  817. interrupt-controller;
  818. #interrupt-cells = <0x02>;
  819. };
  820.  
  821. gpl1 {
  822. gpio-controller;
  823. #gpio-cells = <0x02>;
  824. interrupt-controller;
  825. #interrupt-cells = <0x02>;
  826. };
  827.  
  828. gpl2 {
  829. gpio-controller;
  830. #gpio-cells = <0x02>;
  831. interrupt-controller;
  832. #interrupt-cells = <0x02>;
  833. phandle = <0x2f>;
  834. };
  835.  
  836. gpl3 {
  837. gpio-controller;
  838. #gpio-cells = <0x02>;
  839. interrupt-controller;
  840. #interrupt-cells = <0x02>;
  841. };
  842.  
  843. gpl4 {
  844. gpio-controller;
  845. #gpio-cells = <0x02>;
  846. interrupt-controller;
  847. #interrupt-cells = <0x02>;
  848. };
  849.  
  850. gpl5 {
  851. gpio-controller;
  852. #gpio-cells = <0x02>;
  853. interrupt-controller;
  854. #interrupt-cells = <0x02>;
  855. };
  856.  
  857. gpl6 {
  858. gpio-controller;
  859. #gpio-cells = <0x02>;
  860. interrupt-controller;
  861. #interrupt-cells = <0x02>;
  862. };
  863.  
  864. gpl7 {
  865. gpio-controller;
  866. #gpio-cells = <0x02>;
  867. interrupt-controller;
  868. #interrupt-cells = <0x02>;
  869. };
  870.  
  871. gpl8 {
  872. gpio-controller;
  873. #gpio-cells = <0x02>;
  874. interrupt-controller;
  875. #interrupt-cells = <0x02>;
  876. };
  877.  
  878. gpg0 {
  879. gpio-controller;
  880. #gpio-cells = <0x02>;
  881. interrupt-controller;
  882. #interrupt-cells = <0x02>;
  883. };
  884.  
  885. gpg1 {
  886. gpio-controller;
  887. #gpio-cells = <0x02>;
  888. interrupt-controller;
  889. #interrupt-cells = <0x02>;
  890. };
  891.  
  892. gpg2 {
  893. gpio-controller;
  894. #gpio-cells = <0x02>;
  895. interrupt-controller;
  896. #interrupt-cells = <0x02>;
  897. phandle = <0x32>;
  898. };
  899.  
  900. gpg3 {
  901. gpio-controller;
  902. #gpio-cells = <0x02>;
  903. interrupt-controller;
  904. #interrupt-cells = <0x02>;
  905. };
  906.  
  907. gpg4 {
  908. gpio-controller;
  909. #gpio-cells = <0x02>;
  910. interrupt-controller;
  911. #interrupt-cells = <0x02>;
  912. };
  913.  
  914. gpg5 {
  915. gpio-controller;
  916. #gpio-cells = <0x02>;
  917. interrupt-controller;
  918. #interrupt-cells = <0x02>;
  919. };
  920.  
  921. gpg6 {
  922. gpio-controller;
  923. #gpio-cells = <0x02>;
  924. interrupt-controller;
  925. #interrupt-cells = <0x02>;
  926. };
  927.  
  928. gpg7 {
  929. gpio-controller;
  930. #gpio-cells = <0x02>;
  931. interrupt-controller;
  932. #interrupt-cells = <0x02>;
  933. };
  934.  
  935. gpe0 {
  936. gpio-controller;
  937. #gpio-cells = <0x02>;
  938. interrupt-controller;
  939. #interrupt-cells = <0x02>;
  940. };
  941.  
  942. gpe1 {
  943. gpio-controller;
  944. #gpio-cells = <0x02>;
  945. interrupt-controller;
  946. #interrupt-cells = <0x02>;
  947. };
  948.  
  949. lsio_ufs0_resetn {
  950. samsung,pins = "gpu0-0";
  951. samsung,pin-function = <0x02>;
  952. samsung,pin-pud = <0x00>;
  953. samsung,pin-drv = <0x02>;
  954. phandle = <0xa3>;
  955. };
  956.  
  957. lsio_ufs0_refclockout {
  958. samsung,pins = "gpu0-1";
  959. samsung,pin-function = <0x02>;
  960. samsung,pin-pud = <0x00>;
  961. samsung,pin-drv = <0x02>;
  962. phandle = <0xa4>;
  963. };
  964.  
  965. lsio_ufs0_udpd {
  966. samsung,pins = "gpu0-2";
  967. samsung,pin-function = <0x02>;
  968. samsung,pin-pud = <0x00>;
  969. samsung,pin-drv = <0x02>;
  970. phandle = <0xa5>;
  971. };
  972.  
  973. lsio_i2s0_mclk {
  974. samsung,pins = "gpl0-0";
  975. samsung,pin-function = <0x02>;
  976. samsung,pin-pud = <0x00>;
  977. samsung,pin-drv = <0x02>;
  978. };
  979.  
  980. lsio_i2s0_bclk {
  981. samsung,pins = "gpl0-1";
  982. samsung,pin-function = <0x02>;
  983. samsung,pin-pud = <0x00>;
  984. samsung,pin-drv = <0x02>;
  985. };
  986.  
  987. lsio_i2s0_ws {
  988. samsung,pins = "gpl0-2";
  989. samsung,pin-function = <0x02>;
  990. samsung,pin-pud = <0x00>;
  991. samsung,pin-drv = <0x02>;
  992. };
  993.  
  994. lsio_i2s0_sdo {
  995. samsung,pins = "gpl0-3";
  996. samsung,pin-function = <0x02>;
  997. samsung,pin-pud = <0x00>;
  998. samsung,pin-drv = <0x02>;
  999. };
  1000.  
  1001. lsio_i2s0_sdi {
  1002. samsung,pins = "gpl0-4";
  1003. samsung,pin-function = <0x02>;
  1004. samsung,pin-pud = <0x00>;
  1005. samsung,pin-drv = <0x02>;
  1006. };
  1007.  
  1008. lsio_uart0_data {
  1009. samsung,pins = "gpl1-0\0gpl1-1";
  1010. samsung,pin-function = <0x02>;
  1011. samsung,pin-pud = <0x00>;
  1012. samsung,pin-drv = <0x05>;
  1013. phandle = <0x20>;
  1014. };
  1015.  
  1016. lsio_uart0_ctsn {
  1017. samsung,pins = "gpl1-2";
  1018. samsung,pin-function = <0x02>;
  1019. samsung,pin-pud = <0x00>;
  1020. samsung,pin-drv = <0x05>;
  1021. };
  1022.  
  1023. lsio_uart0_rtsn {
  1024. samsung,pins = "gpl1-3";
  1025. samsung,pin-function = <0x02>;
  1026. samsung,pin-pud = <0x00>;
  1027. samsung,pin-drv = <0x05>;
  1028. };
  1029.  
  1030. lsio_uart1_rxd {
  1031. samsung,pins = "gpl1-4";
  1032. samsung,pin-function = <0x02>;
  1033. samsung,pin-pud = <0x00>;
  1034. samsung,pin-drv = <0x02>;
  1035. };
  1036.  
  1037. lsio_uart1_txd {
  1038. samsung,pins = "gpl1-5";
  1039. samsung,pin-function = <0x02>;
  1040. samsung,pin-pud = <0x00>;
  1041. samsung,pin-drv = <0x02>;
  1042. };
  1043.  
  1044. lsio_uart1_ctsn {
  1045. samsung,pins = "gpl1-6";
  1046. samsung,pin-function = <0x02>;
  1047. samsung,pin-pud = <0x00>;
  1048. samsung,pin-drv = <0x02>;
  1049. };
  1050.  
  1051. lsio_uart1_rtsn {
  1052. samsung,pins = "gpl1-7";
  1053. samsung,pin-function = <0x02>;
  1054. samsung,pin-pud = <0x00>;
  1055. samsung,pin-drv = <0x02>;
  1056. };
  1057.  
  1058. lsio_spi0_clk {
  1059. samsung,pins = "gpl2-0";
  1060. samsung,pin-function = <0x02>;
  1061. samsung,pin-pud = <0x00>;
  1062. samsung,pin-drv = <0x02>;
  1063. };
  1064.  
  1065. lsio_spi0_csn {
  1066. samsung,pins = "gpl2-1";
  1067. samsung,pin-function = <0x02>;
  1068. samsung,pin-pud = <0x00>;
  1069. samsung,pin-drv = <0x02>;
  1070. };
  1071.  
  1072. lsio_spi0_miso {
  1073. samsung,pins = "gpl2-2";
  1074. samsung,pin-function = <0x02>;
  1075. samsung,pin-pud = <0x00>;
  1076. samsung,pin-drv = <0x02>;
  1077. };
  1078.  
  1079. lsio_spi0_mosi {
  1080. samsung,pins = "gpl2-3";
  1081. samsung,pin-function = <0x02>;
  1082. samsung,pin-pud = <0x00>;
  1083. samsung,pin-drv = <0x02>;
  1084. };
  1085.  
  1086. lsio_mcan0_tx {
  1087. samsung,pins = "gpl2-4";
  1088. samsung,pin-function = <0x02>;
  1089. samsung,pin-pud = <0x00>;
  1090. samsung,pin-drv = <0x02>;
  1091. };
  1092.  
  1093. lsio_mcan0_rx {
  1094. samsung,pins = "gpl2-5";
  1095. samsung,pin-function = <0x02>;
  1096. samsung,pin-pud = <0x00>;
  1097. samsung,pin-drv = <0x02>;
  1098. };
  1099.  
  1100. lsio_mcan1_tx {
  1101. samsung,pins = "gpl2-6";
  1102. samsung,pin-function = <0x02>;
  1103. samsung,pin-pud = <0x00>;
  1104. samsung,pin-drv = <0x02>;
  1105. };
  1106.  
  1107. lsio_mcan1_rx {
  1108. samsung,pins = "gpl2-7";
  1109. samsung,pin-function = <0x02>;
  1110. samsung,pin-pud = <0x00>;
  1111. samsung,pin-drv = <0x02>;
  1112. };
  1113.  
  1114. lsio_i2c0_bus {
  1115. samsung,pins = "gpl4-0\0gpl4-1";
  1116. samsung,pin-function = <0x02>;
  1117. samsung,pin-pud = <0x03>;
  1118. samsung,pin-drv = <0x05>;
  1119. phandle = <0x34>;
  1120. };
  1121.  
  1122. lsio_i2c1_bus {
  1123. samsung,pins = "gpl4-2\0gpl4-3";
  1124. samsung,pin-function = <0x02>;
  1125. samsung,pin-pud = <0x03>;
  1126. samsung,pin-drv = <0x05>;
  1127. phandle = <0x35>;
  1128. };
  1129.  
  1130. lsio_i2c2_bus {
  1131. samsung,pins = "gpl4-4\0gpl4-5";
  1132. samsung,pin-function = <0x02>;
  1133. samsung,pin-pud = <0x03>;
  1134. samsung,pin-drv = <0x05>;
  1135. phandle = <0x36>;
  1136. };
  1137.  
  1138. lsio_i2c3_bus {
  1139. samsung,pins = "gpl4-6\0gpl4-7";
  1140. samsung,pin-function = <0x02>;
  1141. samsung,pin-pud = <0x03>;
  1142. samsung,pin-drv = <0x02>;
  1143. };
  1144.  
  1145. lsio_i2c4_bus {
  1146. samsung,pins = "gpl8-0\0gpl8-1";
  1147. samsung,pin-function = <0x02>;
  1148. samsung,pin-pud = <0x03>;
  1149. samsung,pin-drv = <0x02>;
  1150. };
  1151.  
  1152. lsio_i2c5_bus {
  1153. samsung,pins = "gpl8-2\0gpl8-3";
  1154. samsung,pin-function = <0x02>;
  1155. samsung,pin-pud = <0x03>;
  1156. samsung,pin-drv = <0x02>;
  1157. };
  1158.  
  1159. lsio_spi0_bus {
  1160. samsung,pins = "gpl2-0\0gpl2-2\0gpl2-3";
  1161. samsung,pin-function = <0x02>;
  1162. samsung,pin-pud = <0x03>;
  1163. samsung,pin-drv = <0x00>;
  1164. phandle = <0x2e>;
  1165. };
  1166.  
  1167. m_can0-bus {
  1168. samsung,pins = "gpl2-4\0gpl2-5";
  1169. samsung,pin-function = <0x02>;
  1170. samsung,pin-pud = <0x03>;
  1171. samsung,pin-drv = <0x00>;
  1172. phandle = <0x52>;
  1173. };
  1174.  
  1175. m_can1-bus {
  1176. samsung,pins = "gpl2-6\0gpl2-7";
  1177. samsung,pin-function = <0x02>;
  1178. samsung,pin-pud = <0x03>;
  1179. samsung,pin-drv = <0x00>;
  1180. phandle = <0x54>;
  1181. };
  1182.  
  1183. m_can2-bus {
  1184. samsung,pins = "gpl3-0\0gpl3-1";
  1185. samsung,pin-function = <0x02>;
  1186. samsung,pin-pud = <0x03>;
  1187. samsung,pin-drv = <0x00>;
  1188. phandle = <0x55>;
  1189. };
  1190.  
  1191. m_can3-bus {
  1192. samsung,pins = "gpl3-2\0gpl3-3";
  1193. samsung,pin-function = <0x02>;
  1194. samsung,pin-pud = <0x03>;
  1195. samsung,pin-drv = <0x00>;
  1196. phandle = <0x56>;
  1197. };
  1198.  
  1199. i2s0-bus {
  1200. samsung,pins = "gpl0-0\0gpl0-1\0gpl0-2\0gpl0-3\0gpl0-4";
  1201. samsung,pin-function = <0x02>;
  1202. samsung,pin-pud = <0x01>;
  1203. samsung,pin-drv = <0x02>;
  1204. phandle = <0x5d>;
  1205. };
  1206.  
  1207. i2s1-bus {
  1208. samsung,pins = "gpl6-0\0gpl6-1\0gpl6-2\0gpl6-3\0gpl6-4";
  1209. samsung,pin-function = <0x02>;
  1210. samsung,pin-pud = <0x01>;
  1211. samsung,pin-drv = <0x03>;
  1212. phandle = <0x5e>;
  1213. };
  1214.  
  1215. eth1-tx-clk {
  1216. samsung,pins = "gpe0-0";
  1217. samsung,pin-function = <0x02>;
  1218. samsung,pin-pud = <0x01>;
  1219. samsung,pin-drv = <0x03>;
  1220. phandle = <0x9a>;
  1221. };
  1222.  
  1223. eth1-tx-data {
  1224. samsung,pins = "gpe0-1\0gpe0-2\0gpe0-3\0gpe0-4";
  1225. samsung,pin-function = <0x02>;
  1226. samsung,pin-pud = <0x03>;
  1227. samsung,pin-drv = <0x03>;
  1228. phandle = <0x9b>;
  1229. };
  1230.  
  1231. eth1-tx-ctrl {
  1232. samsung,pins = "gpe0-5";
  1233. samsung,pin-function = <0x02>;
  1234. samsung,pin-pud = <0x03>;
  1235. samsung,pin-drv = <0x03>;
  1236. phandle = <0x9c>;
  1237. };
  1238.  
  1239. eth1_phy_intr {
  1240. samsung,pins = "gpe0-6";
  1241. samsung,pin-function = <0x02>;
  1242. samsung,pin-pud = <0x00>;
  1243. samsung,pin-drv = <0x02>;
  1244. phandle = <0x9d>;
  1245. };
  1246.  
  1247. eth1-rx-clk {
  1248. samsung,pins = "gpe1-0";
  1249. samsung,pin-function = <0x02>;
  1250. samsung,pin-pud = <0x03>;
  1251. samsung,pin-drv = <0x03>;
  1252. phandle = <0x9e>;
  1253. };
  1254.  
  1255. eth1-rx-data {
  1256. samsung,pins = "gpe1-1\0gpe1-2\0gpe1-3\0gpe1-4";
  1257. samsung,pin-function = <0x02>;
  1258. samsung,pin-pud = <0x03>;
  1259. samsung,pin-drv = <0x03>;
  1260. phandle = <0x9f>;
  1261. };
  1262.  
  1263. eth1-rx-ctrl {
  1264. samsung,pins = "gpe1-5";
  1265. samsung,pin-function = <0x02>;
  1266. samsung,pin-pud = <0x03>;
  1267. samsung,pin-drv = <0x03>;
  1268. phandle = <0xa0>;
  1269. };
  1270.  
  1271. eth1-mdio {
  1272. samsung,pins = "gpe1-6\0gpe1-7";
  1273. samsung,pin-function = <0x02>;
  1274. samsung,pin-pud = <0x00>;
  1275. samsung,pin-drv = <0x02>;
  1276. };
  1277.  
  1278. lsio_uart2_rxd {
  1279. samsung,pins = "gpl7-0";
  1280. samsung,pin-function = <0x02>;
  1281. samsung,pin-pud = <0x00>;
  1282. samsung,pin-drv = <0x02>;
  1283. };
  1284.  
  1285. lsio_uart2_txd {
  1286. samsung,pins = "gpl7-1";
  1287. samsung,pin-function = <0x02>;
  1288. samsung,pin-pud = <0x00>;
  1289. samsung,pin-drv = <0x02>;
  1290. };
  1291.  
  1292. lsio_uart2_ctsn {
  1293. samsung,pins = "gpl7-2";
  1294. samsung,pin-function = <0x02>;
  1295. samsung,pin-pud = <0x00>;
  1296. samsung,pin-drv = <0x02>;
  1297. };
  1298.  
  1299. lsio_uart2_rtsn {
  1300. samsung,pins = "gpl7-3";
  1301. samsung,pin-function = <0x02>;
  1302. samsung,pin-pud = <0x00>;
  1303. samsung,pin-drv = <0x02>;
  1304. };
  1305.  
  1306. neo_aud_rel_en {
  1307. samsung,pins = "gpg0-0";
  1308. samsung,pin-function = <0x02>;
  1309. samsung,pin-pud = <0x01>;
  1310. samsung,pin-drv = <0x02>;
  1311. };
  1312.  
  1313. neo_imu_spi0_gyro {
  1314. samsung,pins = "gpg0-1";
  1315. samsung,pin-function = <0x01>;
  1316. samsung,pin-pud = <0x01>;
  1317. samsung,pin-drv = <0x02>;
  1318. };
  1319.  
  1320. neo_gps_reset {
  1321. samsung,pins = "gpg0-3";
  1322. samsung,pin-function = <0x02>;
  1323. samsung,pin-pud = <0x01>;
  1324. samsung,pin-drv = <0x02>;
  1325. };
  1326.  
  1327. neo_can0_stb {
  1328. samsung,pins = "gpg0-4";
  1329. samsung,pin-function = <0x02>;
  1330. samsung,pin-pud = <0x03>;
  1331. samsung,pin-drv = <0x00>;
  1332. };
  1333.  
  1334. neo_can1_stb_r {
  1335. samsung,pins = "gpg0-5";
  1336. samsung,pin-function = <0x02>;
  1337. samsung,pin-pud = <0x03>;
  1338. samsung,pin-drv = <0x00>;
  1339. };
  1340.  
  1341. neo_can2_stb_r {
  1342. samsung,pins = "gpg0-6";
  1343. samsung,pin-function = <0x02>;
  1344. samsung,pin-pud = <0x03>;
  1345. samsung,pin-drv = <0x00>;
  1346. };
  1347.  
  1348. neo_can3_stb_r {
  1349. samsung,pins = "gpg0-7";
  1350. samsung,pin-function = <0x02>;
  1351. samsung,pin-pud = <0x03>;
  1352. samsung,pin-drv = <0x00>;
  1353. };
  1354.  
  1355. neo_aud_nmute {
  1356. samsung,pins = "gpg1-0";
  1357. samsung,pin-function = <0x02>;
  1358. samsung,pin-pud = <0x01>;
  1359. samsung,pin-drv = <0x02>;
  1360. };
  1361.  
  1362. neo_aud_stb {
  1363. samsung,pins = "gpg1-1";
  1364. samsung,pin-function = <0x02>;
  1365. samsung,pin-pud = <0x01>;
  1366. samsung,pin-drv = <0x02>;
  1367. };
  1368.  
  1369. neo_3v3_sw_ssd_en {
  1370. samsung,pins = "gpg1-3";
  1371. samsung,pin-function = <0x02>;
  1372. samsung,pin-pud = <0x01>;
  1373. samsung,pin-drv = <0x02>;
  1374. };
  1375.  
  1376. neo_aud_nwarn {
  1377. samsung,pins = "gpg1-4";
  1378. samsung,pin-function = <0x02>;
  1379. samsung,pin-pud = <0x03>;
  1380. samsung,pin-drv = <0x00>;
  1381. };
  1382.  
  1383. neo_ssd_nperst {
  1384. samsung,pins = "gpg1-5";
  1385. samsung,pin-function = <0x02>;
  1386. samsung,pin-pud = <0x03>;
  1387. samsung,pin-drv = <0x00>;
  1388. };
  1389.  
  1390. neo_debug_gpio1 {
  1391. samsung,pins = "gpg1-6";
  1392. samsung,pin-function = <0x02>;
  1393. samsung,pin-pud = <0x03>;
  1394. samsung,pin-drv = <0x00>;
  1395. };
  1396.  
  1397. neo_debug_gpio2 {
  1398. samsung,pins = "gpg1-7";
  1399. samsung,pin-function = <0x02>;
  1400. samsung,pin-pud = <0x03>;
  1401. samsung,pin-drv = <0x00>;
  1402. };
  1403.  
  1404. neo_fpd_1v8_pwn_en {
  1405. samsung,pins = "gpg2-0";
  1406. samsung,pin-function = <0x02>;
  1407. samsung,pin-pud = <0x01>;
  1408. samsung,pin-drv = <0x02>;
  1409. };
  1410.  
  1411. neo_fpdb_1v8_pwn_en {
  1412. samsung,pins = "gpg2-1";
  1413. samsung,pin-function = <0x02>;
  1414. samsung,pin-pud = <0x01>;
  1415. samsung,pin-drv = <0x02>;
  1416. };
  1417.  
  1418. neo_fpd_1v1_pwn_en {
  1419. samsung,pins = "gpg2-2";
  1420. samsung,pin-function = <0x02>;
  1421. samsung,pin-pud = <0x01>;
  1422. samsung,pin-drv = <0x02>;
  1423. };
  1424.  
  1425. neo_fpdb_1v1_pwn_en {
  1426. samsung,pins = "gpg2-4";
  1427. samsung,pin-function = <0x00>;
  1428. samsung,pin-pud = <0x00>;
  1429. samsung,pin-drv = <0x00>;
  1430. phandle = <0xa7>;
  1431. };
  1432.  
  1433. neo_imu_int1 {
  1434. samsung,pins = "gpg2-6";
  1435. samsung,pin-function = <0x00>;
  1436. samsung,pin-pud = <0x00>;
  1437. samsung,pin-drv = <0x00>;
  1438. phandle = <0x30>;
  1439. };
  1440.  
  1441. neo_imu_int2 {
  1442. samsung,pins = "gpg2-7";
  1443. samsung,pin-function = <0x00>;
  1444. samsung,pin-pud = <0x00>;
  1445. samsung,pin-drv = <0x00>;
  1446. phandle = <0x31>;
  1447. };
  1448.  
  1449. neo_trip_gpio3 {
  1450. samsung,pins = "gpg3-0";
  1451. samsung,pin-function = <0x02>;
  1452. samsung,pin-pud = <0x01>;
  1453. samsung,pin-drv = <0x02>;
  1454. };
  1455.  
  1456. neo_int_gpio3 {
  1457. samsung,pins = "gpg3-1";
  1458. samsung,pin-function = <0x02>;
  1459. samsung,pin-pud = <0x01>;
  1460. samsung,pin-drv = <0x02>;
  1461. };
  1462.  
  1463. neo_cpu_gpio3 {
  1464. samsung,pins = "gpg3-2";
  1465. samsung,pin-function = <0x02>;
  1466. samsung,pin-pud = <0x01>;
  1467. samsung,pin-drv = <0x02>;
  1468. };
  1469.  
  1470. neo_gpu_gpio3 {
  1471. samsung,pins = "gpg3-3";
  1472. samsung,pin-function = <0x02>;
  1473. samsung,pin-pud = <0x01>;
  1474. samsung,pin-drv = <0x02>;
  1475. };
  1476.  
  1477. neo_0v75_ddr_gpio3 {
  1478. samsung,pins = "gpg3-4";
  1479. samsung,pin-function = <0x02>;
  1480. samsung,pin-pud = <0x03>;
  1481. samsung,pin-drv = <0x00>;
  1482. };
  1483.  
  1484. neo_1v75_ddr_gpio3 {
  1485. samsung,pins = "gpg3-5";
  1486. samsung,pin-function = <0x02>;
  1487. samsung,pin-pud = <0x03>;
  1488. samsung,pin-drv = <0x00>;
  1489. };
  1490.  
  1491. neo_aud_nfault {
  1492. samsung,pins = "gpg3-6";
  1493. samsung,pin-function = <0x02>;
  1494. samsung,pin-pud = <0x03>;
  1495. samsung,pin-drv = <0x00>;
  1496. };
  1497.  
  1498. neo_ap_healthy {
  1499. samsung,pins = "gpg3-7";
  1500. samsung,pin-function = <0x02>;
  1501. samsung,pin-pud = <0x03>;
  1502. samsung,pin-drv = <0x00>;
  1503. };
  1504.  
  1505. neo_cam_sync_3v3 {
  1506. samsung,pins = "gpl5-0";
  1507. samsung,pin-function = <0x02>;
  1508. samsung,pin-pud = <0x01>;
  1509. samsung,pin-drv = <0x05>;
  1510. phandle = <0x2d>;
  1511. };
  1512.  
  1513. neo_pwm1_3v3 {
  1514. samsung,pins = "gpl5-1";
  1515. samsung,pin-function = <0x02>;
  1516. samsung,pin-pud = <0x01>;
  1517. samsung,pin-drv = <0x02>;
  1518. };
  1519.  
  1520. neo_a75_led1 {
  1521. samsung,pins = "gpg4-0";
  1522. samsung,pin-function = <0x02>;
  1523. samsung,pin-pud = <0x01>;
  1524. samsung,pin-drv = <0x02>;
  1525. };
  1526.  
  1527. neo_refclk_npd {
  1528. samsung,pins = "gpg4-1";
  1529. samsung,pin-function = <0x02>;
  1530. samsung,pin-pud = <0x01>;
  1531. samsung,pin-drv = <0x02>;
  1532. };
  1533.  
  1534. neo_dram_refclk_nen {
  1535. samsung,pins = "gpg4-4";
  1536. samsung,pin-function = <0x02>;
  1537. samsung,pin-pud = <0x03>;
  1538. samsung,pin-drv = <0x00>;
  1539. };
  1540.  
  1541. neo_qd1_lock {
  1542. samsung,pins = "gpg4-5";
  1543. samsung,pin-function = <0x02>;
  1544. samsung,pin-pud = <0x03>;
  1545. samsung,pin-drv = <0x00>;
  1546. };
  1547.  
  1548. neo_qd2_lock {
  1549. samsung,pins = "gpg4-6";
  1550. samsung,pin-function = <0x02>;
  1551. samsung,pin-pud = <0x03>;
  1552. samsung,pin-drv = <0x00>;
  1553. };
  1554.  
  1555. neo_qd3_intb_lock {
  1556. samsung,pins = "gpg4-7";
  1557. samsung,pin-function = <0x02>;
  1558. samsung,pin-pud = <0x03>;
  1559. samsung,pin-drv = <0x00>;
  1560. };
  1561.  
  1562. neo_qd1_clk_en {
  1563. samsung,pins = "gpg5-0";
  1564. samsung,pin-function = <0x02>;
  1565. samsung,pin-pud = <0x01>;
  1566. samsung,pin-drv = <0x02>;
  1567. };
  1568.  
  1569. neo_qd2_clk_en {
  1570. samsung,pins = "gpg5-1";
  1571. samsung,pin-function = <0x02>;
  1572. samsung,pin-pud = <0x01>;
  1573. samsung,pin-drv = <0x02>;
  1574. };
  1575.  
  1576. neo_qd3_clk_en {
  1577. samsung,pins = "gpg5-2";
  1578. samsung,pin-function = <0x02>;
  1579. samsung,pin-pud = <0x01>;
  1580. samsung,pin-drv = <0x02>;
  1581. };
  1582.  
  1583. neo_pcie0_p0_nperst {
  1584. samsung,pins = "gpg5-4";
  1585. samsung,pin-function = <0x02>;
  1586. samsung,pin-pud = <0x03>;
  1587. samsung,pin-drv = <0x00>;
  1588. };
  1589.  
  1590. neo_pcie0_p1_nperst {
  1591. samsung,pins = "gpg5-5";
  1592. samsung,pin-function = <0x02>;
  1593. samsung,pin-pud = <0x03>;
  1594. samsung,pin-drv = <0x00>;
  1595. };
  1596.  
  1597. neo_pcie1_p2_nperst {
  1598. samsung,pins = "gpg5-6";
  1599. samsung,pin-function = <0x02>;
  1600. samsung,pin-pud = <0x03>;
  1601. samsung,pin-drv = <0x00>;
  1602. };
  1603.  
  1604. neo_pcie1_p3_nperst {
  1605. samsung,pins = "gpg5-7";
  1606. samsung,pin-function = <0x02>;
  1607. samsung,pin-pud = <0x03>;
  1608. samsung,pin-drv = <0x00>;
  1609. };
  1610.  
  1611. neo_qd1_npd {
  1612. samsung,pins = "gpg6-0";
  1613. samsung,pin-function = <0x02>;
  1614. samsung,pin-pud = <0x01>;
  1615. samsung,pin-drv = <0x02>;
  1616. };
  1617.  
  1618. neo_qd2_npd {
  1619. samsung,pins = "gpg6-1";
  1620. samsung,pin-function = <0x02>;
  1621. samsung,pin-pud = <0x01>;
  1622. samsung,pin-drv = <0x02>;
  1623. };
  1624.  
  1625. neo_qd3_npd {
  1626. samsung,pins = "gpg6-3";
  1627. samsung,pin-function = <0x02>;
  1628. samsung,pin-pud = <0x01>;
  1629. samsung,pin-drv = <0x02>;
  1630. };
  1631.  
  1632. neo_fpd_1v8_pgood {
  1633. samsung,pins = "gpg6-6";
  1634. samsung,pin-function = <0x02>;
  1635. samsung,pin-pud = <0x03>;
  1636. samsung,pin-drv = <0x00>;
  1637. };
  1638.  
  1639. neo_fpd_1v1_pgood {
  1640. samsung,pins = "gpg6-7";
  1641. samsung,pin-function = <0x02>;
  1642. samsung,pin-pud = <0x03>;
  1643. samsung,pin-drv = <0x00>;
  1644. };
  1645.  
  1646. neo_pcie_refclk_npd {
  1647. samsung,pins = "gpg7-0";
  1648. samsung,pin-function = <0x02>;
  1649. samsung,pin-pud = <0x01>;
  1650. samsung,pin-drv = <0x02>;
  1651. };
  1652.  
  1653. neo_cam_pri_oc {
  1654. samsung,pins = "gpg7-4";
  1655. samsung,pin-function = <0x02>;
  1656. samsung,pin-pud = <0x03>;
  1657. samsung,pin-drv = <0x00>;
  1658. };
  1659.  
  1660. neo_cam_pri2_oc {
  1661. samsung,pins = "gpg7-5";
  1662. samsung,pin-function = <0x02>;
  1663. samsung,pin-pud = <0x03>;
  1664. samsung,pin-drv = <0x00>;
  1665. };
  1666.  
  1667. neo_cam_sec_oc {
  1668. samsung,pins = "gpg7-6";
  1669. samsung,pin-function = <0x02>;
  1670. samsung,pin-pud = <0x03>;
  1671. samsung,pin-drv = <0x00>;
  1672. };
  1673.  
  1674. neo_i2c3 {
  1675. samsung,pins = "gpl4-6\0gpl4-7";
  1676. samsung,pin-function = <0x02>;
  1677. samsung,pin-pud = <0x00>;
  1678. samsung,pin-drv = <0x02>;
  1679. phandle = <0x37>;
  1680. };
  1681.  
  1682. neo_i2c4 {
  1683. samsung,pins = "gpl8-0\0gpl8-1";
  1684. samsung,pin-function = <0x02>;
  1685. samsung,pin-pud = <0x00>;
  1686. samsung,pin-drv = <0x02>;
  1687. phandle = <0x40>;
  1688. };
  1689.  
  1690. neo_i2c5 {
  1691. samsung,pins = "gpl8-2\0gpl8-3";
  1692. samsung,pin-function = <0x02>;
  1693. samsung,pin-pud = <0x00>;
  1694. samsung,pin-drv = <0x02>;
  1695. phandle = <0x49>;
  1696. };
  1697. };
  1698.  
  1699. pinctrl@7FCD0000 {
  1700. compatible = "tesla,fsd-hw4-pinctrl";
  1701. reg = <0x00 0x7fcd0000 0x00 0x2024>;
  1702. interrupts = <0x00 0x16c 0x04>;
  1703.  
  1704. gpp0 {
  1705. gpio-controller;
  1706. #gpio-cells = <0x02>;
  1707. interrupt-controller;
  1708. #interrupt-cells = <0x02>;
  1709. };
  1710.  
  1711. gpp1 {
  1712. gpio-controller;
  1713. #gpio-cells = <0x02>;
  1714. interrupt-controller;
  1715. #interrupt-cells = <0x02>;
  1716. };
  1717.  
  1718. pcie0_clkreq {
  1719. samsung,pins = "gpp0-0";
  1720. samsung,pin-function = <0x02>;
  1721. samsung,pin-pud = <0x00>;
  1722. samsung,pin-drv = <0x02>;
  1723. };
  1724.  
  1725. pcie0_wake0 {
  1726. samsung,pins = "gpp0-1";
  1727. samsung,pin-function = <0x02>;
  1728. samsung,pin-pud = <0x00>;
  1729. samsung,pin-drv = <0x02>;
  1730. };
  1731.  
  1732. pcie0_p0_preset {
  1733. samsung,pins = "gpp0-2";
  1734. samsung,pin-function = <0x02>;
  1735. samsung,pin-pud = <0x00>;
  1736. samsung,pin-drv = <0x02>;
  1737. };
  1738.  
  1739. pcie0_p1_preset {
  1740. samsung,pins = "gpp0-3";
  1741. samsung,pin-function = <0x02>;
  1742. samsung,pin-pud = <0x00>;
  1743. samsung,pin-drv = <0x02>;
  1744. };
  1745.  
  1746. pcie0_wake1 {
  1747. samsung,pins = "gpp0-4";
  1748. samsung,pin-function = <0x02>;
  1749. samsung,pin-pud = <0x00>;
  1750. samsung,pin-drv = <0x02>;
  1751. };
  1752.  
  1753. pcie1_clkreq {
  1754. samsung,pins = "gpp1-0";
  1755. samsung,pin-function = <0x02>;
  1756. samsung,pin-pud = <0x00>;
  1757. samsung,pin-drv = <0x02>;
  1758. };
  1759.  
  1760. pcie1_wake0 {
  1761. samsung,pins = "gpp1-1";
  1762. samsung,pin-function = <0x02>;
  1763. samsung,pin-pud = <0x00>;
  1764. samsung,pin-drv = <0x02>;
  1765. };
  1766.  
  1767. pcie1_p2_preset {
  1768. samsung,pins = "gpp1-2";
  1769. samsung,pin-function = <0x02>;
  1770. samsung,pin-pud = <0x00>;
  1771. samsung,pin-drv = <0x02>;
  1772. };
  1773.  
  1774. pcie1_p3_preset {
  1775. samsung,pins = "gpp1-3";
  1776. samsung,pin-function = <0x02>;
  1777. samsung,pin-pud = <0x00>;
  1778. samsung,pin-drv = <0x02>;
  1779. };
  1780.  
  1781. pcie1_wake1 {
  1782. samsung,pins = "gpp1-4";
  1783. samsung,pin-function = <0x02>;
  1784. samsung,pin-pud = <0x00>;
  1785. samsung,pin-drv = <0x02>;
  1786. };
  1787. };
  1788.  
  1789. sms_mfd {
  1790. compatible = "tesla,fsd-sms-mfd";
  1791. status = "okay";
  1792.  
  1793. regulators {
  1794.  
  1795. voltage_turbo_int {
  1796. regulator-name = "VOLTAGE_TURBO_INT";
  1797. regulator-min-microvolt = <0xaae60>;
  1798. regulator-max-microvolt = <0xe7720>;
  1799. regulator-settling-time-up-us = <0xc8>;
  1800. regulator-boot-on;
  1801. regulator-always-on;
  1802. };
  1803.  
  1804. voltage_turbo_cpu {
  1805. regulator-name = "VOLTAGE_TURBO_CPU";
  1806. regulator-min-microvolt = <0xa3930>;
  1807. regulator-max-microvolt = <0xe7ef0>;
  1808. regulator-settling-time-up-us = <0xc8>;
  1809. regulator-boot-on;
  1810. regulator-always-on;
  1811. phandle = <0x19>;
  1812. };
  1813.  
  1814. voltage_turbo_gpu {
  1815. regulator-name = "VOLTAGE_TURBO_GPU";
  1816. regulator-min-microvolt = <0xaae60>;
  1817. regulator-max-microvolt = <0xe7b08>;
  1818. regulator-settling-time-up-us = <0xc8>;
  1819. regulator-boot-on;
  1820. regulator-always-on;
  1821. };
  1822.  
  1823. voltage_turbo_trip0 {
  1824. regulator-name = "VOLTAGE_TURBO_TRIP0";
  1825. regulator-min-microvolt = <0xaae60>;
  1826. regulator-max-microvolt = <0xe7720>;
  1827. regulator-settling-time-up-us = <0xc8>;
  1828. regulator-boot-on;
  1829. regulator-always-on;
  1830. phandle = <0x8a>;
  1831. };
  1832. };
  1833. };
  1834.  
  1835. clock-controller@25410000 {
  1836. compatible = "tesla,fsd-hw4-clock-lsio\0syscon";
  1837. reg = <0x00 0x25410000 0x00 0x3000>;
  1838. #clock-cells = <0x01>;
  1839. clocks = <0x21>;
  1840. clock-names = "clkcmu_lsio_main";
  1841. status = "okay";
  1842. phandle = <0x1f>;
  1843. };
  1844.  
  1845. clock-controller@22310000 {
  1846. compatible = "tesla,fsd-hw4-clock-cpucl1";
  1847. reg = <0x00 0x22310000 0x00 0x3000>;
  1848. #clock-cells = <0x01>;
  1849. clocks = <0x22>;
  1850. clock-names = "div_sgk_1000";
  1851. status = "okay";
  1852. phandle = <0x1b>;
  1853. };
  1854.  
  1855. clock-controller@22010000 {
  1856. compatible = "tesla,fsd-hw4-clock-cpucl0";
  1857. reg = <0x00 0x22010000 0x00 0x3000>;
  1858. #clock-cells = <0x01>;
  1859. clocks = <0x1b 0x6e 0x1b 0x6f 0x1b 0x70 0x1b 0x71 0x1b 0x72 0x1b 0x70>;
  1860. clock-names = "pll_cpucl0_div\0pll_cpucl0_div2\0pll_cpucl1_div\0pll_cpucl1_div2\0pll_cpucl1_dsu\0pll_cpucl0_dsu";
  1861. status = "okay";
  1862. phandle = <0x18>;
  1863. };
  1864.  
  1865. clock-controller@F810000 {
  1866. compatible = "tesla,fsd-hw4-clock-imem";
  1867. reg = <0x00 0xf810000 0x00 0x3000>;
  1868. #clock-cells = <0x01>;
  1869. clocks = <0x23>;
  1870. clock-names = "clkcmu_imem_main";
  1871. status = "okay";
  1872. phandle = <0x29>;
  1873. };
  1874.  
  1875. clock-controller@7FC10000 {
  1876. compatible = "tesla,fsd-hw4-clock-pcie\0syscon";
  1877. reg = <0x00 0x7fc10000 0x00 0x10000>;
  1878. #clock-cells = <0x01>;
  1879. clocks = <0x22>;
  1880. clock-names = "div_sgk_1000";
  1881. status = "okay";
  1882. phandle = <0x58>;
  1883. };
  1884.  
  1885. clock-controller@27010000 {
  1886. compatible = "tesla,fsd-hw4-clock-gpu0";
  1887. reg = <0x00 0x27010000 0x00 0x10000>;
  1888. #clock-cells = <0x01>;
  1889. clocks = <0x24>;
  1890. clock-names = "clkcmu_gpu_main";
  1891. status = "okay";
  1892. phandle = <0x62>;
  1893. };
  1894.  
  1895. clock-controller@27410000 {
  1896. compatible = "tesla,fsd-hw4-clock-gpu1";
  1897. reg = <0x00 0x27410000 0x00 0x10000>;
  1898. #clock-cells = <0x01>;
  1899. clocks = <0x24>;
  1900. clock-names = "clkcmu_gpu_main";
  1901. status = "okay";
  1902. phandle = <0x63>;
  1903. };
  1904.  
  1905. clock-controller@23810000 {
  1906. compatible = "tesla,fsd-hw4-clock-mfc0";
  1907. reg = <0x00 0x23810000 0x00 0x3000>;
  1908. #clock-cells = <0x01>;
  1909. clocks = <0x25>;
  1910. clock-names = "clkcmu_mfc_busp";
  1911. status = "okay";
  1912. phandle = <0x83>;
  1913. };
  1914.  
  1915. clock-controller@23C10000 {
  1916. compatible = "tesla,fsd-hw4-clock-mfc1";
  1917. reg = <0x00 0x23c10000 0x00 0x3000>;
  1918. #clock-cells = <0x01>;
  1919. clocks = <0x25>;
  1920. clock-names = "clkcmu_mfc_busp";
  1921. status = "okay";
  1922. phandle = <0x85>;
  1923. };
  1924.  
  1925. clock-controller@23010000 {
  1926. compatible = "tesla,fsd-hw4-clock-csi";
  1927. reg = <0x00 0x23010000 0x00 0x3000>;
  1928. #clock-cells = <0x01>;
  1929. clocks = <0x26>;
  1930. clock-names = "clkcmu_csi_main";
  1931. status = "okay";
  1932. phandle = <0x64>;
  1933. };
  1934.  
  1935. clock-controller@22810000 {
  1936. compatible = "tesla,fsd-hw4-clock-isp0";
  1937. reg = <0x00 0x22810000 0x00 0x3000>;
  1938. #clock-cells = <0x01>;
  1939. clocks = <0x27>;
  1940. clock-names = "clkcmu_isp_main";
  1941. status = "okay";
  1942. phandle = <0x7f>;
  1943. };
  1944.  
  1945. clock-controller@22C10000 {
  1946. compatible = "tesla,fsd-hw4-clock-isp1";
  1947. reg = <0x00 0x22c10000 0x00 0x3000>;
  1948. #clock-cells = <0x01>;
  1949. clocks = <0x27>;
  1950. clock-names = "clkcmu_isp_main";
  1951. status = "okay";
  1952. phandle = <0x81>;
  1953. };
  1954.  
  1955. clock-controller@20010000 {
  1956. compatible = "tesla,fsd-hw4-clock-trip0";
  1957. reg = <0x00 0x20010000 0x00 0x3000>;
  1958. #clock-cells = <0x01>;
  1959. clocks = <0x28>;
  1960. clock-names = "pll_trip_sw";
  1961. status = "okay";
  1962. phandle = <0x88>;
  1963. };
  1964.  
  1965. clock-controller@20410000 {
  1966. compatible = "tesla,fsd-hw4-clock-trip1";
  1967. reg = <0x00 0x20410000 0x00 0x3000>;
  1968. #clock-cells = <0x01>;
  1969. clocks = <0x28>;
  1970. clock-names = "pll_trip_sw";
  1971. status = "okay";
  1972. phandle = <0x8c>;
  1973. };
  1974.  
  1975. clock-controller@20810000 {
  1976. compatible = "tesla,fsd-hw4-clock-trip2";
  1977. reg = <0x00 0x20810000 0x00 0x3000>;
  1978. #clock-cells = <0x01>;
  1979. clocks = <0x28>;
  1980. clock-names = "pll_trip_sw";
  1981. status = "okay";
  1982. phandle = <0x8f>;
  1983. };
  1984.  
  1985. tcu_imem@0FA00000 {
  1986. compatible = "arm,smmu-v3";
  1987. reg = <0x00 0xfa00000 0x00 0x20000>;
  1988. interrupts = <0x00 0x67 0x01 0x00 0x64 0x01 0x00 0x6a 0x01>;
  1989. interrupt-names = "eventq\0cmdq-sync\0gerror";
  1990. #iommu-cells = <0x01>;
  1991. dma-coherent;
  1992. status = "okay";
  1993. phandle = <0x2a>;
  1994. };
  1995.  
  1996. tcu_imem_pmcg@FA02000 {
  1997. compatible = "arm-smmu-v3-pmu";
  1998. reg = <0x00 0xfa02000 0x00 0x1000 0x00 0xfa22000 0x00 0xe00>;
  1999. interrupts = <0x00 0x6d 0x01>;
  2000. status = "disabled";
  2001. };
  2002.  
  2003. mdma@0F860000 {
  2004. compatible = "arm,pl330\0arm,primecell";
  2005. reg = <0x00 0xf860000 0x00 0x1000>;
  2006. interrupts = <0x00 0x5c 0x04>;
  2007. #dma-cells = <0x01>;
  2008. #dma-channels = <0x08>;
  2009. #dma-requests = <0x20>;
  2010. clocks = <0x29 0x09>;
  2011. clock-names = "apb_pclk";
  2012. iommus = <0x2a 0x00>;
  2013. status = "okay";
  2014. };
  2015.  
  2016. mdma@0F870000 {
  2017. compatible = "arm,pl330\0arm,primecell";
  2018. reg = <0x00 0xf870000 0x00 0x1000>;
  2019. interrupts = <0x00 0x5d 0x04>;
  2020. #dma-cells = <0x01>;
  2021. #dma-channels = <0x08>;
  2022. #dma-requests = <0x20>;
  2023. clocks = <0x29 0x0a>;
  2024. clock-names = "apb_pclk";
  2025. iommus = <0x2a 0x01>;
  2026. status = "okay";
  2027. };
  2028.  
  2029. tcu_lsio@25600000 {
  2030. compatible = "arm,smmu-v3";
  2031. reg = <0x00 0x25600000 0x00 0x20000>;
  2032. interrupts = <0x00 0xbd 0x01 0x00 0xc0 0x01 0x00 0xc2 0x01>;
  2033. interrupt-names = "eventq\0cmdq-sync\0gerror";
  2034. #iommu-cells = <0x01>;
  2035. dma-coherent;
  2036. status = "okay";
  2037. phandle = <0x2b>;
  2038. };
  2039.  
  2040. tcu_lsio_pmcg@25602000 {
  2041. compatible = "arm-smmu-v3-pmu";
  2042. reg = <0x00 0x25602000 0x00 0x1000 0x00 0x25622000 0x00 0xe00>;
  2043. interrupts = <0x00 0xc4 0x01>;
  2044. status = "disabled";
  2045. };
  2046.  
  2047. pdma@25460000 {
  2048. compatible = "arm,pl330\0arm,primecell";
  2049. reg = <0x00 0x25460000 0x00 0x1000>;
  2050. interrupts = <0x00 0xb8 0x04>;
  2051. #dma-cells = <0x01>;
  2052. #dma-channels = <0x08>;
  2053. #dma-requests = <0x20>;
  2054. clocks = <0x1f 0x06>;
  2055. clock-names = "apb_pclk";
  2056. iommus = <0x2b 0x00>;
  2057. status = "okay";
  2058. phandle = <0x33>;
  2059. };
  2060.  
  2061. pdma@25470000 {
  2062. compatible = "arm,pl330\0arm,primecell";
  2063. reg = <0x00 0x25470000 0x00 0x1000>;
  2064. interrupts = <0x00 0xba 0x04>;
  2065. #dma-cells = <0x01>;
  2066. #dma-channels = <0x08>;
  2067. #dma-requests = <0x20>;
  2068. clocks = <0x1f 0x07>;
  2069. clock-names = "apb_pclk";
  2070. iommus = <0x2b 0x01>;
  2071. status = "okay";
  2072. phandle = <0x1e>;
  2073. };
  2074.  
  2075. watchdog@25C80000 {
  2076. compatible = "tesla,fsd-hw4-wdt";
  2077. reg = <0x00 0x25c80000 0x00 0x100>;
  2078. interrupts = <0x00 0x18 0x04>;
  2079. clocks = <0x2c>;
  2080. clock-names = "watchdog";
  2081. status = "okay";
  2082. };
  2083.  
  2084. watchdog@25C90000 {
  2085. compatible = "tesla,fsd-hw4-wdt";
  2086. reg = <0x00 0x25c90000 0x00 0x100>;
  2087. interrupts = <0x00 0x19 0x04>;
  2088. clocks = <0x2c>;
  2089. clock-names = "watchdog";
  2090. status = "okay";
  2091. };
  2092.  
  2093. watchdog@25CA0000 {
  2094. compatible = "tesla,fsd-hw4-wdt";
  2095. reg = <0x00 0x25ca0000 0x00 0x100>;
  2096. interrupts = <0x00 0x1a 0x04>;
  2097. clocks = <0x2c>;
  2098. clock-names = "watchdog";
  2099. status = "okay";
  2100. };
  2101.  
  2102. watchdog@25CB0000 {
  2103. compatible = "tesla,fsd-hw4-wdt";
  2104. reg = <0x00 0x25cb0000 0x00 0x100>;
  2105. interrupts = <0x00 0x1b 0x04>;
  2106. clocks = <0x2c>;
  2107. clock-names = "watchdog";
  2108. status = "okay";
  2109. };
  2110.  
  2111. watchdog@25CC0000 {
  2112. compatible = "tesla,fsd-hw4-wdt";
  2113. reg = <0x00 0x25cc0000 0x00 0x100>;
  2114. interrupts = <0x00 0x1c 0x04>;
  2115. clocks = <0x2c>;
  2116. clock-names = "watchdog";
  2117. status = "okay";
  2118. };
  2119.  
  2120. mct@25C40000 {
  2121. compatible = "samsung,exynos4210-mct";
  2122. reg = <0x00 0x25c40000 0x00 0x1644>;
  2123. interrupts = <0x00 0x00 0x04 0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04 0x00 0x06 0x04 0x00 0x07 0x04 0x00 0x08 0x04 0x00 0x09 0x04 0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04 0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x12 0x04 0x00 0x13 0x04 0x00 0x14 0x04 0x00 0x15 0x04 0x00 0x16 0x04 0x00 0x17 0x04>;
  2124. clocks = <0x2c 0x2c>;
  2125. clock-names = "fin_pll\0mct";
  2126. };
  2127.  
  2128. pwm@250E0000 {
  2129. compatible = "samsung,exynos4210-pwm";
  2130. reg = <0x00 0x250e0000 0x00 0x100>;
  2131. samsung,pwm-outputs = <0x00 0x01 0x02 0x03>;
  2132. #pwm-cells = <0x03>;
  2133. clocks = <0x2c>;
  2134. interrupts = <0x00 0x96 0x04 0x00 0x97 0x04>;
  2135. clock-names = "timers";
  2136. dmas = <0x1e 0x11>;
  2137. dma-names = "pwm";
  2138. pinctrl-names = "default";
  2139. status = "okay";
  2140. pinctrl-0 = <0x2d>;
  2141. };
  2142.  
  2143. spi@25100000 {
  2144. compatible = "tesla,fsd-spi";
  2145. reg = <0x00 0x25100000 0x00 0x100>;
  2146. interrupts = <0x00 0x9e 0x04>;
  2147. dmas = <0x1e 0x06 0x1e 0x07>;
  2148. dma-names = "tx\0rx";
  2149. #address-cells = <0x01>;
  2150. #size-cells = <0x00>;
  2151. clocks = <0x1f 0x16 0x1f 0x17>;
  2152. clock-names = "spi\0spi_busclk0";
  2153. samsung,spi-src-clk = <0x00>;
  2154. pinctrl-names = "default";
  2155. pinctrl-0 = <0x2e>;
  2156. num-cs = <0x01>;
  2157. status = "okay";
  2158. cs-gpios = <0x2f 0x01 0x01>;
  2159.  
  2160. spi@0 {
  2161. compatible = "st,asm330lhh";
  2162. pinctrl-names = "default";
  2163. pinctrl-0 = <0x30 0x31>;
  2164. spi-max-frequency = <0x7a120>;
  2165. reg = <0x00>;
  2166. interrupts = <0x06 0x04>;
  2167. interrupt-parent = <0x32>;
  2168.  
  2169. controller-data {
  2170. samsung,spi-feedback-delay = <0x00>;
  2171. };
  2172. };
  2173. };
  2174.  
  2175. spi@25110000 {
  2176. compatible = "tesla,fsd-spi";
  2177. reg = <0x00 0x25110000 0x00 0x100>;
  2178. interrupts = <0x00 0x9f 0x04>;
  2179. dmas = <0x1e 0x08 0x1e 0x09>;
  2180. dma-names = "tx\0rx";
  2181. #address-cells = <0x01>;
  2182. #size-cells = <0x00>;
  2183. clocks = <0x1f 0x18 0x1f 0x19>;
  2184. clock-names = "spi\0spi_busclk0";
  2185. samsung,spi-src-clk = <0x00>;
  2186. pinctrl-names = "default";
  2187. num-cs = <0x01>;
  2188. status = "disabled";
  2189. };
  2190.  
  2191. spi@25140000 {
  2192. compatible = "tesla,fsd-spi";
  2193. reg = <0x00 0x25140000 0x00 0x100>;
  2194. interrupts = <0x00 0xa0 0x04>;
  2195. dmas = <0x33 0x0e 0x33 0x0f>;
  2196. dma-names = "tx\0rx";
  2197. #address-cells = <0x01>;
  2198. #size-cells = <0x00>;
  2199. clocks = <0x1f 0x1a 0x1f 0x1b>;
  2200. clock-names = "spi\0spi_busclk0";
  2201. samsung,spi-src-clk = <0x00>;
  2202. pinctrl-names = "default";
  2203. num-cs = <0x01>;
  2204. status = "disabled";
  2205. };
  2206.  
  2207. spi@25170000 {
  2208. compatible = "tesla,fsd-spi";
  2209. reg = <0x00 0x25170000 0x00 0x100>;
  2210. interrupts = <0x00 0xa1 0x04>;
  2211. dmas = <0x33 0x10 0x33 0x11>;
  2212. dma-names = "tx\0rx";
  2213. #address-cells = <0x01>;
  2214. #size-cells = <0x00>;
  2215. clocks = <0x1f 0x1c 0x1f 0x1d>;
  2216. clock-names = "spi\0spi_busclk0";
  2217. samsung,spi-src-clk = <0x00>;
  2218. pinctrl-names = "default";
  2219. num-cs = <0x01>;
  2220. status = "disabled";
  2221. };
  2222.  
  2223. spi@25180000 {
  2224. compatible = "tesla,fsd-spi";
  2225. reg = <0x00 0x25180000 0x00 0x100>;
  2226. interrupts = <0x00 0xa2 0x04>;
  2227. dmas = <0x33 0x12 0x33 0x13>;
  2228. dma-names = "tx\0rx";
  2229. #address-cells = <0x01>;
  2230. #size-cells = <0x00>;
  2231. clocks = <0x1f 0x1e 0x1f 0x1f>;
  2232. clock-names = "spi\0spi_busclk0";
  2233. samsung,spi-src-clk = <0x00>;
  2234. pinctrl-names = "default";
  2235. num-cs = <0x01>;
  2236. status = "disabled";
  2237. };
  2238.  
  2239. hsi2c@251A0000 {
  2240. compatible = "samsung,exynos7-hsi2c";
  2241. reg = <0x00 0x251a0000 0x00 0x1000>;
  2242. interrupts = <0x00 0x98 0x04>;
  2243. #address-cells = <0x01>;
  2244. #size-cells = <0x00>;
  2245. pinctrl-names = "default";
  2246. pinctrl-0 = <0x34>;
  2247. clocks = <0x1f 0x08>;
  2248. clock-names = "hsi2c";
  2249. status = "okay";
  2250. };
  2251.  
  2252. hsi2c@251B0000 {
  2253. compatible = "samsung,exynos7-hsi2c";
  2254. reg = <0x00 0x251b0000 0x00 0x1000>;
  2255. interrupts = <0x00 0x99 0x04>;
  2256. #address-cells = <0x01>;
  2257. #size-cells = <0x00>;
  2258. pinctrl-names = "default";
  2259. pinctrl-0 = <0x35>;
  2260. clocks = <0x1f 0x09>;
  2261. clock-names = "hsi2c";
  2262. status = "okay";
  2263. };
  2264.  
  2265. hsi2c@251C0000 {
  2266. compatible = "samsung,exynos7-hsi2c";
  2267. reg = <0x00 0x251c0000 0x00 0x1000>;
  2268. interrupts = <0x00 0x9a 0x04>;
  2269. #address-cells = <0x01>;
  2270. #size-cells = <0x00>;
  2271. pinctrl-names = "default";
  2272. pinctrl-0 = <0x36>;
  2273. clocks = <0x1f 0x0a>;
  2274. clock-names = "hsi2c";
  2275. status = "okay";
  2276. };
  2277.  
  2278. hsi2c@251D0000 {
  2279. compatible = "samsung,exynos7-hsi2c";
  2280. reg = <0x00 0x251d0000 0x00 0x1000>;
  2281. interrupts = <0x00 0x9b 0x04>;
  2282. #address-cells = <0x01>;
  2283. #size-cells = <0x00>;
  2284. pinctrl-names = "default";
  2285. pinctrl-0 = <0x37>;
  2286. clocks = <0x1f 0x0b>;
  2287. clock-names = "hsi2c";
  2288. clock-frequency = <0x61a80>;
  2289. status = "okay";
  2290.  
  2291. fsdsensor0@10 {
  2292. compatible = "tesla,fsd-sensor0";
  2293. reg = <0x10>;
  2294.  
  2295. port {
  2296. #address-cells = <0x01>;
  2297. #size-cells = <0x00>;
  2298.  
  2299. endpoint@0 {
  2300. bus-type = <0x01>;
  2301. bus-width = <0x03>;
  2302. clock-lanes = <0x00>;
  2303. data-lanes = <0x01 0x02 0x03>;
  2304. remote-endpoint = <0x38>;
  2305. phandle = <0x67>;
  2306. };
  2307. };
  2308. };
  2309.  
  2310. fsdsensor1@11 {
  2311. compatible = "tesla,fsd-sensor1";
  2312. reg = <0x11>;
  2313.  
  2314. port {
  2315. #address-cells = <0x01>;
  2316. #size-cells = <0x00>;
  2317.  
  2318. endpoint@1 {
  2319. bus-type = <0x01>;
  2320. bus-width = <0x03>;
  2321. clock-lanes = <0x00>;
  2322. data-lanes = <0x01 0x02 0x03>;
  2323. remote-endpoint = <0x39>;
  2324. phandle = <0x68>;
  2325. };
  2326. };
  2327. };
  2328.  
  2329. fsdsensor2@12 {
  2330. compatible = "tesla,fsd-sensor2";
  2331. reg = <0x12>;
  2332.  
  2333. port {
  2334. #address-cells = <0x01>;
  2335. #size-cells = <0x00>;
  2336.  
  2337. endpoint@2 {
  2338. bus-type = <0x01>;
  2339. bus-width = <0x03>;
  2340. clock-lanes = <0x00>;
  2341. data-lanes = <0x01 0x02 0x03>;
  2342. remote-endpoint = <0x3a>;
  2343. phandle = <0x69>;
  2344. };
  2345. };
  2346. };
  2347.  
  2348. fsdsensor3@13 {
  2349. compatible = "tesla,fsd-sensor3";
  2350. reg = <0x13>;
  2351.  
  2352. port {
  2353. #address-cells = <0x01>;
  2354. #size-cells = <0x00>;
  2355.  
  2356. endpoint@3 {
  2357. bus-type = <0x01>;
  2358. bus-width = <0x03>;
  2359. clock-lanes = <0x00>;
  2360. data-lanes = <0x01 0x02 0x03>;
  2361. remote-endpoint = <0x3b>;
  2362. phandle = <0x6a>;
  2363. };
  2364. };
  2365. };
  2366.  
  2367. fsdsensor4@14 {
  2368. compatible = "tesla,fsd-sensor4";
  2369. reg = <0x14>;
  2370.  
  2371. port {
  2372. #address-cells = <0x01>;
  2373. #size-cells = <0x00>;
  2374.  
  2375. endpoint@4 {
  2376. bus-type = <0x01>;
  2377. bus-width = <0x03>;
  2378. clock-lanes = <0x00>;
  2379. data-lanes = <0x01 0x02 0x03>;
  2380. remote-endpoint = <0x3c>;
  2381. phandle = <0x6b>;
  2382. };
  2383. };
  2384. };
  2385.  
  2386. fsdsensor5@15 {
  2387. compatible = "tesla,fsd-sensor5";
  2388. reg = <0x15>;
  2389.  
  2390. port {
  2391. #address-cells = <0x01>;
  2392. #size-cells = <0x00>;
  2393.  
  2394. endpoint@5 {
  2395. bus-type = <0x01>;
  2396. bus-width = <0x03>;
  2397. clock-lanes = <0x00>;
  2398. data-lanes = <0x01 0x02 0x03>;
  2399. remote-endpoint = <0x3d>;
  2400. phandle = <0x6c>;
  2401. };
  2402. };
  2403. };
  2404.  
  2405. fsdsensor6@16 {
  2406. compatible = "tesla,fsd-sensor6";
  2407. reg = <0x16>;
  2408.  
  2409. port {
  2410. #address-cells = <0x01>;
  2411. #size-cells = <0x00>;
  2412.  
  2413. endpoint@6 {
  2414. bus-type = <0x01>;
  2415. bus-width = <0x03>;
  2416. clock-lanes = <0x00>;
  2417. data-lanes = <0x01 0x02 0x03>;
  2418. remote-endpoint = <0x3e>;
  2419. phandle = <0x6d>;
  2420. };
  2421. };
  2422. };
  2423.  
  2424. fsdsensor7@17 {
  2425. compatible = "tesla,fsd-sensor7";
  2426. reg = <0x17>;
  2427.  
  2428. port {
  2429. #address-cells = <0x01>;
  2430. #size-cells = <0x00>;
  2431.  
  2432. endpoint@7 {
  2433. bus-type = <0x01>;
  2434. bus-width = <0x03>;
  2435. clock-lanes = <0x00>;
  2436. data-lanes = <0x01 0x02 0x03>;
  2437. remote-endpoint = <0x3f>;
  2438. phandle = <0x6e>;
  2439. };
  2440. };
  2441. };
  2442. };
  2443.  
  2444. hsi2c@251E0000 {
  2445. compatible = "samsung,exynos7-hsi2c";
  2446. reg = <0x00 0x251e0000 0x00 0x1000>;
  2447. interrupts = <0x00 0x9c 0x04>;
  2448. #address-cells = <0x01>;
  2449. #size-cells = <0x00>;
  2450. pinctrl-names = "default";
  2451. pinctrl-0 = <0x40>;
  2452. clocks = <0x1f 0x0c>;
  2453. clock-names = "hsi2c";
  2454. clock-frequency = <0x61a80>;
  2455. status = "okay";
  2456.  
  2457. fsdsensor8@18 {
  2458. compatible = "tesla,fsd-sensor8";
  2459. reg = <0x18>;
  2460.  
  2461. port {
  2462. #address-cells = <0x01>;
  2463. #size-cells = <0x00>;
  2464.  
  2465. endpoint@0 {
  2466. bus-type = <0x01>;
  2467. bus-width = <0x03>;
  2468. clock-lanes = <0x00>;
  2469. data-lanes = <0x01 0x02 0x03>;
  2470. remote-endpoint = <0x41>;
  2471. phandle = <0x6f>;
  2472. };
  2473. };
  2474. };
  2475.  
  2476. fsdsensor9@19 {
  2477. compatible = "tesla,fsd-sensor9";
  2478. reg = <0x19>;
  2479.  
  2480. port {
  2481. #address-cells = <0x01>;
  2482. #size-cells = <0x00>;
  2483.  
  2484. endpoint@1 {
  2485. bus-type = <0x01>;
  2486. bus-width = <0x03>;
  2487. clock-lanes = <0x00>;
  2488. data-lanes = <0x01 0x02 0x03>;
  2489. remote-endpoint = <0x42>;
  2490. phandle = <0x70>;
  2491. };
  2492. };
  2493. };
  2494.  
  2495. fsdsensor10@1a {
  2496. compatible = "tesla,fsd-sensor10";
  2497. reg = <0x1a>;
  2498.  
  2499. port {
  2500. #address-cells = <0x01>;
  2501. #size-cells = <0x00>;
  2502.  
  2503. endpoint@2 {
  2504. bus-type = <0x01>;
  2505. bus-width = <0x03>;
  2506. clock-lanes = <0x00>;
  2507. data-lanes = <0x01 0x02 0x03>;
  2508. remote-endpoint = <0x43>;
  2509. phandle = <0x71>;
  2510. };
  2511. };
  2512. };
  2513.  
  2514. fsdsensor11@1b {
  2515. compatible = "tesla,fsd-sensor11";
  2516. reg = <0x1b>;
  2517.  
  2518. port {
  2519. #address-cells = <0x01>;
  2520. #size-cells = <0x00>;
  2521.  
  2522. endpoint@3 {
  2523. bus-type = <0x01>;
  2524. bus-width = <0x03>;
  2525. clock-lanes = <0x00>;
  2526. data-lanes = <0x01 0x02 0x03>;
  2527. remote-endpoint = <0x44>;
  2528. phandle = <0x72>;
  2529. };
  2530. };
  2531. };
  2532.  
  2533. fsdsensor12@1c {
  2534. compatible = "tesla,fsd-sensor12";
  2535. reg = <0x1c>;
  2536.  
  2537. port {
  2538. #address-cells = <0x01>;
  2539. #size-cells = <0x00>;
  2540.  
  2541. endpoint@4 {
  2542. bus-type = <0x01>;
  2543. bus-width = <0x03>;
  2544. clock-lanes = <0x00>;
  2545. data-lanes = <0x01 0x02 0x03>;
  2546. remote-endpoint = <0x45>;
  2547. phandle = <0x73>;
  2548. };
  2549. };
  2550. };
  2551.  
  2552. fsdsensor13@1d {
  2553. compatible = "tesla,fsd-sensor13";
  2554. reg = <0x1d>;
  2555.  
  2556. port {
  2557. #address-cells = <0x01>;
  2558. #size-cells = <0x00>;
  2559.  
  2560. endpoint@5 {
  2561. bus-type = <0x01>;
  2562. bus-width = <0x03>;
  2563. clock-lanes = <0x00>;
  2564. data-lanes = <0x01 0x02 0x03>;
  2565. remote-endpoint = <0x46>;
  2566. phandle = <0x74>;
  2567. };
  2568. };
  2569. };
  2570.  
  2571. fsdsensor14@1e {
  2572. compatible = "tesla,fsd-sensor14";
  2573. reg = <0x1e>;
  2574.  
  2575. port {
  2576. #address-cells = <0x01>;
  2577. #size-cells = <0x00>;
  2578.  
  2579. endpoint@6 {
  2580. bus-type = <0x01>;
  2581. bus-width = <0x03>;
  2582. clock-lanes = <0x00>;
  2583. data-lanes = <0x01 0x02 0x03>;
  2584. remote-endpoint = <0x47>;
  2585. phandle = <0x75>;
  2586. };
  2587. };
  2588. };
  2589.  
  2590. fsdsensor15@1f {
  2591. compatible = "tesla,fsd-sensor15";
  2592. reg = <0x1f>;
  2593.  
  2594. port {
  2595. #address-cells = <0x01>;
  2596. #size-cells = <0x00>;
  2597.  
  2598. endpoint@7 {
  2599. bus-type = <0x01>;
  2600. bus-width = <0x03>;
  2601. clock-lanes = <0x00>;
  2602. data-lanes = <0x01 0x02 0x03>;
  2603. remote-endpoint = <0x48>;
  2604. phandle = <0x76>;
  2605. };
  2606. };
  2607. };
  2608. };
  2609.  
  2610. hsi2c@251F0000 {
  2611. compatible = "samsung,exynos7-hsi2c";
  2612. reg = <0x00 0x251f0000 0x00 0x1000>;
  2613. interrupts = <0x00 0x9d 0x04>;
  2614. #address-cells = <0x01>;
  2615. #size-cells = <0x00>;
  2616. pinctrl-names = "default";
  2617. pinctrl-0 = <0x49>;
  2618. clocks = <0x1f 0x0d>;
  2619. clock-names = "hsi2c";
  2620. clock-frequency = <0x61a80>;
  2621. status = "okay";
  2622.  
  2623. fsdsensor16@20 {
  2624. compatible = "tesla,fsd-sensor16";
  2625. reg = <0x20>;
  2626.  
  2627. port {
  2628. #address-cells = <0x01>;
  2629. #size-cells = <0x00>;
  2630.  
  2631. endpoint@0 {
  2632. bus-type = <0x01>;
  2633. bus-width = <0x03>;
  2634. clock-lanes = <0x00>;
  2635. data-lanes = <0x01 0x02 0x03>;
  2636. remote-endpoint = <0x4a>;
  2637. phandle = <0x77>;
  2638. };
  2639. };
  2640. };
  2641.  
  2642. fsdsensor17@21 {
  2643. compatible = "tesla,fsd-sensor17";
  2644. reg = <0x21>;
  2645.  
  2646. port {
  2647. #address-cells = <0x01>;
  2648. #size-cells = <0x00>;
  2649.  
  2650. endpoint@1 {
  2651. bus-type = <0x01>;
  2652. bus-width = <0x03>;
  2653. clock-lanes = <0x00>;
  2654. data-lanes = <0x01 0x02 0x03>;
  2655. remote-endpoint = <0x4b>;
  2656. phandle = <0x78>;
  2657. };
  2658. };
  2659. };
  2660.  
  2661. fsdsensor18@22 {
  2662. compatible = "tesla,fsd-sensor18";
  2663. reg = <0x22>;
  2664.  
  2665. port {
  2666. #address-cells = <0x01>;
  2667. #size-cells = <0x00>;
  2668.  
  2669. endpoint@2 {
  2670. bus-type = <0x01>;
  2671. bus-width = <0x03>;
  2672. clock-lanes = <0x00>;
  2673. data-lanes = <0x01 0x02 0x03>;
  2674. remote-endpoint = <0x4c>;
  2675. phandle = <0x79>;
  2676. };
  2677. };
  2678. };
  2679.  
  2680. fsdsensor19@23 {
  2681. compatible = "tesla,fsd-sensor19";
  2682. reg = <0x23>;
  2683.  
  2684. port {
  2685. #address-cells = <0x01>;
  2686. #size-cells = <0x00>;
  2687.  
  2688. endpoint@3 {
  2689. bus-type = <0x01>;
  2690. bus-width = <0x03>;
  2691. clock-lanes = <0x00>;
  2692. data-lanes = <0x01 0x02 0x03>;
  2693. remote-endpoint = <0x4d>;
  2694. phandle = <0x7a>;
  2695. };
  2696. };
  2697. };
  2698.  
  2699. fsdsensor20@24 {
  2700. compatible = "tesla,fsd-sensor20";
  2701. reg = <0x24>;
  2702.  
  2703. port {
  2704. #address-cells = <0x01>;
  2705. #size-cells = <0x00>;
  2706.  
  2707. endpoint@4 {
  2708. bus-type = <0x01>;
  2709. bus-width = <0x03>;
  2710. clock-lanes = <0x00>;
  2711. data-lanes = <0x01 0x02 0x03>;
  2712. remote-endpoint = <0x4e>;
  2713. phandle = <0x7b>;
  2714. };
  2715. };
  2716. };
  2717.  
  2718. fsdsensor21@25 {
  2719. compatible = "tesla,fsd-sensor21";
  2720. reg = <0x25>;
  2721.  
  2722. port {
  2723. #address-cells = <0x01>;
  2724. #size-cells = <0x00>;
  2725.  
  2726. endpoint@5 {
  2727. bus-type = <0x01>;
  2728. bus-width = <0x03>;
  2729. clock-lanes = <0x00>;
  2730. data-lanes = <0x01 0x02 0x03>;
  2731. remote-endpoint = <0x4f>;
  2732. phandle = <0x7c>;
  2733. };
  2734. };
  2735. };
  2736.  
  2737. fsdsensor228@26 {
  2738. compatible = "tesla,fsd-sensor22";
  2739. reg = <0x26>;
  2740.  
  2741. port {
  2742. #address-cells = <0x01>;
  2743. #size-cells = <0x00>;
  2744.  
  2745. endpoint@6 {
  2746. bus-type = <0x01>;
  2747. bus-width = <0x03>;
  2748. clock-lanes = <0x00>;
  2749. data-lanes = <0x01 0x02 0x03>;
  2750. remote-endpoint = <0x50>;
  2751. phandle = <0x7d>;
  2752. };
  2753. };
  2754. };
  2755.  
  2756. fsdsensor23@27 {
  2757. compatible = "tesla,fsd-sensor23";
  2758. reg = <0x27>;
  2759.  
  2760. port {
  2761. #address-cells = <0x01>;
  2762. #size-cells = <0x00>;
  2763.  
  2764. endpoint@7 {
  2765. bus-type = <0x01>;
  2766. bus-width = <0x03>;
  2767. clock-lanes = <0x00>;
  2768. data-lanes = <0x01 0x02 0x03>;
  2769. remote-endpoint = <0x51>;
  2770. phandle = <0x7e>;
  2771. };
  2772. };
  2773. };
  2774. };
  2775.  
  2776. sysreg_lsio@25430000 {
  2777. compatible = "samsung,sysreg_lsio\0syscon";
  2778. reg = <0x00 0x25430000 0x00 0x1000>;
  2779. phandle = <0x53>;
  2780. };
  2781.  
  2782. sysreg_pcie@7FC30000 {
  2783. compatible = "tesla,sysreg_pcie\0syscon";
  2784. reg = <0x00 0x7fc30000 0x00 0x1000>;
  2785. phandle = <0x59>;
  2786. };
  2787.  
  2788. can@25120000 {
  2789. compatible = "bosch,m_can";
  2790. reg = <0x00 0x25128000 0x00 0x200 0x00 0x25120000 0x00 0x8000>;
  2791. reg-names = "m_can\0message_ram";
  2792. interrupts = <0x00 0xa3 0x04 0x00 0xa4 0x04>;
  2793. interrupt-names = "int0\0int1";
  2794. pinctrl-names = "default";
  2795. pinctrl-0 = <0x52>;
  2796. clocks = <0x1f 0x0f 0x1f 0x0e>;
  2797. clock-names = "hclk\0cclk";
  2798. syscon-mraminit = <0x53 0x470>;
  2799. bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
  2800. status = "okay";
  2801. };
  2802.  
  2803. can@25130000 {
  2804. compatible = "bosch,m_can";
  2805. reg = <0x00 0x25138000 0x00 0x200 0x00 0x25130000 0x00 0x8000>;
  2806. reg-names = "m_can\0message_ram";
  2807. interrupts = <0x00 0xa7 0x04 0x00 0xa8 0x04>;
  2808. interrupt-names = "int0\0int1";
  2809. pinctrl-names = "default";
  2810. pinctrl-0 = <0x54>;
  2811. clocks = <0x1f 0x11 0x1f 0x10>;
  2812. clock-names = "hclk\0cclk";
  2813. syscon-mraminit = <0x53 0x474>;
  2814. bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
  2815. status = "okay";
  2816. };
  2817.  
  2818. can@25150000 {
  2819. compatible = "bosch,m_can";
  2820. reg = <0x00 0x25158000 0x00 0x200 0x00 0x25150000 0x00 0x8000>;
  2821. reg-names = "m_can\0message_ram";
  2822. interrupts = <0x00 0xab 0x04 0x00 0xac 0x04>;
  2823. interrupt-names = "int0\0int1";
  2824. pinctrl-names = "default";
  2825. pinctrl-0 = <0x55>;
  2826. clocks = <0x1f 0x13 0x1f 0x12>;
  2827. clock-names = "hclk\0cclk";
  2828. syscon-mraminit = <0x53 0x478>;
  2829. bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
  2830. status = "okay";
  2831. };
  2832.  
  2833. can@25160000 {
  2834. compatible = "bosch,m_can";
  2835. reg = <0x00 0x25168000 0x00 0x200 0x00 0x25160000 0x00 0x8000>;
  2836. reg-names = "m_can\0message_ram";
  2837. interrupts = <0x00 0xaf 0x04 0x00 0xb0 0x04>;
  2838. interrupt-names = "int0\0int1";
  2839. pinctrl-names = "default";
  2840. pinctrl-0 = <0x56>;
  2841. clocks = <0x1f 0x14 0x1f 0x47>;
  2842. clock-names = "hclk\0cclk";
  2843. syscon-mraminit = <0x53 0x47c>;
  2844. bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
  2845. status = "okay";
  2846. };
  2847.  
  2848. mailbox@24060000 {
  2849. compatible = "tesla,fsd-hw4-mailbox";
  2850. reg = <0x00 0x24060000 0x00 0x100>;
  2851. interrupts = <0x00 0x24b 0x04>;
  2852. #mbox-cells = <0x01>;
  2853. status = "okay";
  2854. phandle = <0x1d>;
  2855. };
  2856.  
  2857. mailbox@24070000 {
  2858. compatible = "tesla,fsd-hw4-mailbox";
  2859. reg = <0x00 0x24070000 0x00 0x100>;
  2860. interrupts = <0x00 0x24c 0x04>;
  2861. #mbox-cells = <0x01>;
  2862. status = "disabled";
  2863. };
  2864.  
  2865. mailbox@2A400000 {
  2866. compatible = "tesla,fsd-hw4-mailbox";
  2867. reg = <0x00 0x2a400000 0x00 0x100>;
  2868. interrupts = <0x00 0x24d 0x04>;
  2869. #mbox-cells = <0x01>;
  2870. status = "disabled";
  2871. };
  2872.  
  2873. mailbox@2A410000 {
  2874. compatible = "tesla,fsd-hw4-mailbox";
  2875. reg = <0x00 0x2a410000 0x00 0x100>;
  2876. interrupts = <0x00 0x24e 0x04>;
  2877. #mbox-cells = <0x01>;
  2878. status = "disabled";
  2879. };
  2880.  
  2881. smscan {
  2882. compatible = "tesla,fsd-smscan";
  2883. memory-region = <0x57>;
  2884. };
  2885.  
  2886. pcie-phy@7FC60000 {
  2887. compatible = "tesla,fsd-hw4-pcie-phy";
  2888. clocks = <0x58 0x2a 0x58 0x29 0x58 0x3c 0x58 0x48>;
  2889. clock-names = "pipe_pclk\0wrp_pclk\0scan_clk\0immortal_clk";
  2890. #phy-cells = <0x00>;
  2891. reg = <0x00 0x7fc60000 0x00 0x10000 0x00 0x7fc40000 0x00 0x10000>;
  2892. reg-names = "phy\0pcs";
  2893. tesla,pcie-sysreg = <0x59>;
  2894. lane-sel = <0x00>;
  2895. phy-mode = <0x00>;
  2896. status = "okay";
  2897. phandle = <0x5b>;
  2898. };
  2899.  
  2900. pcie-phy@7FC70000 {
  2901. compatible = "tesla,fsd-hw4-pcie-phy";
  2902. clocks = <0x58 0x30 0x58 0x31 0x58 0x3f 0x58 0x47>;
  2903. clock-names = "pipe_pclk\0wrp_pclk\0scan_clk\0immortal_clk";
  2904. #phy-cells = <0x00>;
  2905. reg = <0x00 0x7fc70000 0x00 0x10000 0x00 0x7fc50000 0x00 0x10000>;
  2906. reg-names = "phy\0pcs";
  2907. tesla,pcie-sysreg = <0x59>;
  2908. lane-sel = <0x02>;
  2909. phy-mode = <0x00>;
  2910. status = "disabled";
  2911. phandle = <0x5c>;
  2912. };
  2913.  
  2914. tcu_pcie@7FE00000 {
  2915. compatible = "arm,smmu-v3";
  2916. reg = <0x00 0x7fe00000 0x00 0x20000>;
  2917. interrupts = <0x00 0x15a 0x01 0x00 0x158 0x01 0x00 0x15c 0x01>;
  2918. interrupt-names = "eventq\0cmdq-sync\0gerror";
  2919. #iommu-cells = <0x01>;
  2920. dma-coherent;
  2921. status = "okay";
  2922. phandle = <0x5a>;
  2923. };
  2924.  
  2925. tcu_pcie_pmcg@7FE02000 {
  2926. compatible = "arm-smmu-v3-pmu";
  2927. reg = <0x00 0x7fe02000 0x00 0x1000 0x00 0x7fe22000 0x00 0xe00>;
  2928. interrupts = <0x00 0x15e 0x01>;
  2929. status = "disabled";
  2930. };
  2931.  
  2932. pcie@7F800000 {
  2933. compatible = "tesla,fsd-pcie-hw4";
  2934. clocks = <0x58 0x43 0x58 0x09 0x58 0x0a 0x58 0x0b 0x58 0x24>;
  2935. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  2936. #address-cells = <0x03>;
  2937. #size-cells = <0x02>;
  2938. device_type = "pci";
  2939. dma-coherent;
  2940. interrupts = <0x00 0x10a 0x04 0x00 0x103 0x04>;
  2941. interrupt-names = "intr\0sub_ctrl_intr";
  2942. num-lanes = <0x04>;
  2943. detect-link-rst;
  2944. user-ltssm;
  2945. msix-quirk;
  2946. mps = [02 00];
  2947. mrrs = [10 00];
  2948. reg = <0x00 0x7fc80000 0x00 0x1000 0x00 0x7f800000 0x00 0x1000 0x00 0x40000000 0x00 0x1000>;
  2949. reg-names = "elbi\0dbics\0config";
  2950. ranges = <0x82000000 0x00 0x40001000 0x00 0x40001000 0x00 0xffff000>;
  2951. tesla,pcie-sysreg = <0x59 0x508>;
  2952. iommu-map = <0x00 0x5a 0x00 0x10000>;
  2953. iommu-map-mask = <0x00>;
  2954. mode = "rc";
  2955. phys = <0x5b>;
  2956. phy-names = "pcie_phy0";
  2957. status = "disabled";
  2958. };
  2959.  
  2960. pcie_ep@7F800000 {
  2961. compatible = "tesla,fsd-pcie-hw4";
  2962. clocks = <0x58 0x43 0x58 0x09 0x58 0x0a 0x58 0x0b 0x58 0x24>;
  2963. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  2964. interrupts = <0x00 0x10a 0x04 0x00 0x103 0x04>;
  2965. interrupt-names = "intr\0sub_ctrl_intr";
  2966. reg = <0x00 0x7fc80000 0x00 0x1000 0x00 0x7f800000 0x00 0x1000 0x00 0x7f801000 0x00 0x80 0x00 0x40000000 0x00 0xffff000>;
  2967. reg-names = "elbi\0dbics\0dbics2\0config";
  2968. num-lanes = <0x04>;
  2969. mps = [02 00];
  2970. mrrs = [10 00];
  2971. num-ib-windows = <0x10>;
  2972. num-ob-windows = <0x10>;
  2973. tesla,pcie-sysreg = <0x59 0x508>;
  2974. iommus = <0x5a 0x00>;
  2975. mode = "ep";
  2976. dma-coherent;
  2977. detect-link-rst;
  2978. user-ltssm;
  2979. msix-quirk;
  2980. phys = <0x5b>;
  2981. phy-names = "pcie_phy0";
  2982. status = "disabled";
  2983. };
  2984.  
  2985. pcie@7F900000 {
  2986. compatible = "tesla,fsd-pcie-hw4";
  2987. clocks = <0x58 0x44 0x58 0x27 0x58 0x26 0x58 0x25 0x58 0x28>;
  2988. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  2989. #address-cells = <0x03>;
  2990. #size-cells = <0x02>;
  2991. device_type = "pci";
  2992. dma-coherent;
  2993. interrupts = <0x00 0x11b 0x04 0x00 0x114 0x04>;
  2994. interrupt-names = "intr\0sub_ctrl_intr";
  2995. num-lanes = <0x02>;
  2996. detect-link-rst;
  2997. user-ltssm;
  2998. msix-quirk;
  2999. mps = [02 00];
  3000. mrrs = [10 00];
  3001. reg = <0x00 0x7fc90000 0x00 0x1000 0x00 0x7f900000 0x00 0x1000 0x00 0x50000000 0x00 0x1000>;
  3002. reg-names = "elbi\0dbics\0config";
  3003. ranges = <0x82000000 0x00 0x50001000 0x00 0x50001000 0x00 0xffff000>;
  3004. tesla,pcie-sysreg = <0x59 0x50c>;
  3005. iommu-map = <0x00 0x5a 0x01 0x10000>;
  3006. iommu-map-mask = <0x00>;
  3007. mode = "rc";
  3008. phys = <0x5b>;
  3009. phy-names = "pcie_phy0";
  3010. status = "disabled";
  3011. };
  3012.  
  3013. pcie_ep@7F900000 {
  3014. compatible = "tesla,fsd-pcie-hw4";
  3015. clocks = <0x58 0x44 0x58 0x27 0x58 0x26 0x58 0x25 0x58 0x28>;
  3016. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  3017. interrupts = <0x00 0x11b 0x04 0x00 0x114 0x04>;
  3018. interrupt-names = "intr\0sub_ctrl_intr";
  3019. reg = <0x00 0x7fc90000 0x00 0x1000 0x00 0x7f900000 0x00 0x1000 0x00 0x7f901000 0x00 0x80 0x00 0x50000000 0x00 0xffff000>;
  3020. reg-names = "elbi\0dbics\0dbics2\0config";
  3021. num-lanes = <0x02>;
  3022. detect-link-rst;
  3023. user-ltssm;
  3024. msix-quirk;
  3025. mps = [02 00];
  3026. mrrs = [10 00];
  3027. num-ib-windows = <0x10>;
  3028. num-ob-windows = <0x10>;
  3029. tesla,pcie-sysreg = <0x59 0x50c>;
  3030. iommus = <0x5a 0x01>;
  3031. dma-coherent;
  3032. mode = "ep";
  3033. phys = <0x5b>;
  3034. phy-names = "pcie_phy0";
  3035. status = "disabled";
  3036. };
  3037.  
  3038. pcie@7FA00000 {
  3039. compatible = "tesla,fsd-pcie-hw4";
  3040. clocks = <0x58 0x45 0x58 0x0c 0x58 0x0d 0x58 0x0e 0x58 0x2b>;
  3041. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  3042. #address-cells = <0x03>;
  3043. #size-cells = <0x02>;
  3044. device_type = "pci";
  3045. dma-coherent;
  3046. interrupts = <0x00 0x13d 0x04 0x00 0x136 0x04>;
  3047. interrupt-names = "intr\0sub_ctrl_intr";
  3048. num-lanes = <0x02>;
  3049. mps = [02 00];
  3050. mrrs = [10 00];
  3051. msix-quirk;
  3052. reg = <0x00 0x7fca0000 0x00 0x1000 0x00 0x7fa00000 0x00 0x1000 0x00 0x60000000 0x00 0x1000>;
  3053. reg-names = "elbi\0dbics\0config";
  3054. ranges = <0x82000000 0x00 0x60001000 0x00 0x60001000 0x00 0xffff000>;
  3055. tesla,pcie-sysreg = <0x59 0x510>;
  3056. iommu-map = <0x00 0x5a 0x02 0x10000>;
  3057. iommu-map-mask = <0x00>;
  3058. mode = "rc";
  3059. phys = <0x5c>;
  3060. phy-names = "pcie_phy1";
  3061. status = "disabled";
  3062. };
  3063.  
  3064. pcie_ep@7FA00000 {
  3065. compatible = "tesla,fsd-pcie-hw4";
  3066. clocks = <0x58 0x45 0x58 0x0c 0x58 0x0d 0x58 0x0e 0x58 0x2b>;
  3067. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  3068. interrupts = <0x00 0x13d 0x04 0x00 0x136 0x04>;
  3069. interrupt-names = "intr\0sub_ctrl_intr";
  3070. reg = <0x00 0x7fca0000 0x00 0x1000 0x00 0x7fa00000 0x00 0x1000 0x00 0x7fa01000 0x00 0x80 0x00 0x60000000 0x00 0xffff000>;
  3071. reg-names = "elbi\0dbics\0dbics2\0config";
  3072. num-lanes = <0x02>;
  3073. mps = [02 00];
  3074. mrrs = [10 00];
  3075. msix-quirk;
  3076. num-ib-windows = <0x10>;
  3077. num-ob-windows = <0x10>;
  3078. tesla,pcie-sysreg = <0x59 0x510>;
  3079. iommus = <0x5a 0x02>;
  3080. mode = "ep";
  3081. dma-coherent;
  3082. phys = <0x5c>;
  3083. phy-names = "pcie_phy1";
  3084. status = "disabled";
  3085. };
  3086.  
  3087. pcie@7FB00000 {
  3088. compatible = "tesla,fsd-pcie-hw4";
  3089. clocks = <0x58 0x46 0x58 0x2c 0x58 0x2e 0x58 0x2f 0x58 0x2d>;
  3090. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  3091. #address-cells = <0x03>;
  3092. #size-cells = <0x02>;
  3093. device_type = "pci";
  3094. dma-coherent;
  3095. interrupts = <0x00 0x12c 0x04 0x00 0x125 0x04>;
  3096. interrupt-names = "intr\0sub_ctrl_intr";
  3097. num-lanes = <0x01>;
  3098. mps = [02 00];
  3099. mrrs = [10 00];
  3100. msix-quirk;
  3101. reg = <0x00 0x7fcb0000 0x00 0x1000 0x00 0x7fb00000 0x00 0x1000 0x00 0x70000000 0x00 0x1000>;
  3102. reg-names = "elbi\0dbics\0config";
  3103. ranges = <0x82000000 0x00 0x70001000 0x00 0x70001000 0x00 0x7fff000>;
  3104. tesla,pcie-sysreg = <0x59 0x514>;
  3105. iommu-map = <0x00 0x5a 0x03 0x10000>;
  3106. iommu-map-mask = <0x00>;
  3107. mode = "rc";
  3108. phys = <0x5c>;
  3109. phy-names = "pcie_phy1";
  3110. status = "disabled";
  3111. };
  3112.  
  3113. pcie_ep@7FB00000 {
  3114. compatible = "tesla,fsd-pcie-hw4";
  3115. clocks = <0x58 0x46 0x58 0x2c 0x58 0x2e 0x58 0x2f 0x58 0x2d>;
  3116. clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk\0apb_clk";
  3117. interrupts = <0x00 0x12c 0x04 0x00 0x125 0x04>;
  3118. interrupt-names = "intr\0sub_ctrl_intr";
  3119. reg = <0x00 0x7fcb0000 0x00 0x1000 0x00 0x7fb00000 0x00 0x1000 0x00 0x7fb01000 0x00 0x80 0x00 0x70000000 0x00 0x7fff000>;
  3120. reg-names = "elbi\0dbics\0dbics2\0config";
  3121. num-lanes = <0x01>;
  3122. mps = [02 00];
  3123. mrrs = [10 00];
  3124. msix-quirk;
  3125. num-ib-windows = <0x10>;
  3126. num-ob-windows = <0x10>;
  3127. tesla,pcie-sysreg = <0x59 0x514>;
  3128. iommus = <0x5a 0x03>;
  3129. mode = "ep";
  3130. dma-coherent;
  3131. phys = <0x5c>;
  3132. phy-names = "pcie_phy1";
  3133. status = "disabled";
  3134. };
  3135.  
  3136. dummy-codec {
  3137. compatible = "samsung,dummy-codec";
  3138. #sound-dai-cells = <0x01>;
  3139. status = "okay";
  3140. phandle = <0x60>;
  3141. };
  3142.  
  3143. tdm@250C0000 {
  3144. compatible = "samsung,exynos7-i2s";
  3145. reg = <0x00 0x250c0000 0x00 0x100>;
  3146. interrupts = <0x00 0xb6 0x04>;
  3147. dmas = <0x1e 0x0c 0x1e 0x0b 0x1e 0x0a>;
  3148. dma-names = "tx\0rx\0tx-sec";
  3149. #clock-cells = <0x01>;
  3150. #sound-dai-cells = <0x01>;
  3151. clocks = <0x1f 0x20 0x1f 0x20 0x1f 0x21>;
  3152. clock-names = "i2s_opclk0\0i2s_opclk1\0iis";
  3153. pinctrl-names = "default";
  3154. pinctrl-0 = <0x5d>;
  3155. samsung,sec-dai-id = <0x00>;
  3156. status = "okay";
  3157. phandle = <0x5f>;
  3158. };
  3159.  
  3160. tdm@250D0000 {
  3161. compatible = "samsung,exynos7-i2s";
  3162. reg = <0x00 0x250d0000 0x00 0x100>;
  3163. interrupts = <0x00 0xb7 0x04>;
  3164. dmas = <0x1e 0x0f 0x1e 0x0e 0x1e 0x0d>;
  3165. dma-names = "tx\0rx\0tx-sec";
  3166. #clock-cells = <0x01>;
  3167. #sound-dai-cells = <0x01>;
  3168. clocks = <0x1f 0x22 0x1f 0x22 0x1f 0x23>;
  3169. clock-names = "i2s_opclk0\0i2s_opclk1\0iis";
  3170. pinctrl-names = "default";
  3171. pinctrl-0 = <0x5e>;
  3172. samsung,sec-dai-id = <0x01>;
  3173. status = "okay";
  3174. phandle = <0x61>;
  3175. };
  3176.  
  3177. sound {
  3178. compatible = "tesla,fsd-hw4-sndcard";
  3179. status = "okay";
  3180. fsd,model = "fsd-i2s";
  3181. fsd,audio-routing = "Primary SPK1\0Mixer DAI TX\0Secondary SPK1\0Mixer DAI TX\0Primary SPK2\0Mixer DAI TX\0Secondary SPK2\0Mixer DAI TX\0Mixer DAI RX\0Primary MIC1\0Mixer DAI RX\0Primary MIC2";
  3182.  
  3183. primary-dai-link@0 {
  3184. link-name = "fsd-primary-0";
  3185. dai-format = "i2s";
  3186. fsd,bitclock-master = <0x5f>;
  3187. fsd,frame-master = <0x5f>;
  3188.  
  3189. cpu {
  3190. sound-dai = <0x5f 0x00>;
  3191. };
  3192.  
  3193. codec {
  3194. sound-dai = <0x60 0x00>;
  3195. };
  3196. };
  3197.  
  3198. secondary-dai-link@0 {
  3199. link-name = "fsd-secondary-0";
  3200. dai-format = "i2s";
  3201. fsd,bitclock-master = <0x5f>;
  3202. fsd,frame-master = <0x5f>;
  3203.  
  3204. cpu {
  3205. sound-dai = <0x5f 0x01>;
  3206. };
  3207.  
  3208. codec {
  3209. sound-dai = <0x60 0x00>;
  3210. };
  3211. };
  3212.  
  3213. primary-dai-link@1 {
  3214. link-name = "fsd-primary-1";
  3215. dai-format = "i2s";
  3216. fsd,bitclock-master = <0x61>;
  3217. fsd,frame-master = <0x61>;
  3218.  
  3219. cpu {
  3220. sound-dai = <0x61 0x00>;
  3221. };
  3222.  
  3223. codec {
  3224. sound-dai = <0x60 0x01>;
  3225. };
  3226. };
  3227.  
  3228. secondary-dai-link@1 {
  3229. link-name = "fsd-secondary-1";
  3230. dai-format = "i2s";
  3231. fsd,bitclock-master = <0x61>;
  3232. fsd,frame-master = <0x61>;
  3233.  
  3234. cpu {
  3235. sound-dai = <0x61 0x01>;
  3236. };
  3237.  
  3238. codec {
  3239. sound-dai = <0x60 0x01>;
  3240. };
  3241. };
  3242. };
  3243.  
  3244. mali0@27100000 {
  3245. compatible = "arm,mali-midgard";
  3246. reg = <0x00 0x27100000 0x00 0x5000>;
  3247. interrupts = <0x00 0x1ea 0x04 0x00 0x1eb 0x04 0x00 0x1ec 0x04>;
  3248. interrupt-names = "JOB\0MMU\0GPU";
  3249. clocks = <0x62 0x01>;
  3250. clock-names = "clk_gpu";
  3251. system-coherency = <0x01>;
  3252. status = "okay";
  3253. low-latency;
  3254. };
  3255.  
  3256. mali1@27500000 {
  3257. compatible = "arm,mali-midgard";
  3258. reg = <0x00 0x27500000 0x00 0x5000>;
  3259. interrupts = <0x00 0x1ee 0x04 0x00 0x1ef 0x04 0x00 0x1f0 0x04>;
  3260. interrupt-names = "JOB\0MMU\0GPU";
  3261. clocks = <0x63 0x01>;
  3262. clock-names = "clk_gpu";
  3263. system-coherency = <0x01>;
  3264. status = "okay";
  3265. low-latency;
  3266. };
  3267.  
  3268. tcu_csi@23200000 {
  3269. compatible = "arm,smmu-v3";
  3270. reg = <0x00 0x23200000 0x00 0x20000>;
  3271. interrupts = <0x00 0x21 0x01 0x00 0x23 0x01 0x00 0x25 0x01>;
  3272. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3273. #iommu-cells = <0x01>;
  3274. dma-coherent;
  3275. status = "okay";
  3276. phandle = <0x65>;
  3277. };
  3278.  
  3279. tcu_csi_pmcg@23202000 {
  3280. compatible = "arm-smmu-v3-pmu";
  3281. reg = <0x00 0x23202000 0x00 0x1000 0x00 0x23222000 0x00 0xe00>;
  3282. interrupts = <0x00 0x27 0x01>;
  3283. status = "disabled";
  3284. };
  3285.  
  3286. sysreg_cam_csi@23030000 {
  3287. compatible = "tesla,sysreg_cam_csi\0syscon";
  3288. reg = <0x00 0x23030000 0x00 0x500>;
  3289. reg-names = "sysreg_cam_csi";
  3290. phandle = <0x66>;
  3291. };
  3292.  
  3293. csis0@23040000 {
  3294. compatible = "tesla,fsd-hw4-csis";
  3295. reg = <0x00 0x23040000 0x00 0x5000 0x00 0x23080000 0x00 0x1000>;
  3296. interrupts = <0x00 0x30 0x04>;
  3297. clocks = <0x64 0x05 0x64 0x0a 0x64 0x1b>;
  3298. clock-names = "csis0-aclk\0csis0-phy-pclk\0csis0-pclk";
  3299. iommus = <0x65 0x00>;
  3300. syscon = <0x66>;
  3301. status = "okay";
  3302.  
  3303. ports {
  3304. #address-cells = <0x01>;
  3305. #size-cells = <0x00>;
  3306.  
  3307. port@0 {
  3308. reg = <0x00>;
  3309.  
  3310. endpoint@0 {
  3311. slave-mode;
  3312. bus-type = <0x01>;
  3313. bus-width = <0x03>;
  3314. clock-lanes = <0x00>;
  3315. data-lanes = <0x01 0x02 0x03>;
  3316. remote-endpoint = <0x67>;
  3317. phandle = <0x38>;
  3318. };
  3319. };
  3320.  
  3321. port@1 {
  3322. reg = <0x01>;
  3323.  
  3324. endpoint@1 {
  3325. slave-mode;
  3326. bus-type = <0x01>;
  3327. bus-width = <0x03>;
  3328. clock-lanes = <0x00>;
  3329. data-lanes = <0x01 0x02 0x03>;
  3330. remote-endpoint = <0x68>;
  3331. phandle = <0x39>;
  3332. };
  3333. };
  3334.  
  3335. port@2 {
  3336. reg = <0x02>;
  3337.  
  3338. endpoint@2 {
  3339. slave-mode;
  3340. bus-type = <0x01>;
  3341. bus-width = <0x03>;
  3342. clock-lanes = <0x00>;
  3343. data-lanes = <0x01 0x02 0x03>;
  3344. remote-endpoint = <0x69>;
  3345. phandle = <0x3a>;
  3346. };
  3347. };
  3348.  
  3349. port@3 {
  3350. reg = <0x03>;
  3351.  
  3352. endpoint@3 {
  3353. slave-mode;
  3354. bus-type = <0x01>;
  3355. bus-width = <0x03>;
  3356. clock-lanes = <0x00>;
  3357. data-lanes = <0x01 0x02 0x03>;
  3358. remote-endpoint = <0x6a>;
  3359. phandle = <0x3b>;
  3360. };
  3361. };
  3362.  
  3363. port@4 {
  3364. reg = <0x04>;
  3365.  
  3366. endpoint@4 {
  3367. slave-mode;
  3368. bus-type = <0x01>;
  3369. bus-width = <0x03>;
  3370. clock-lanes = <0x00>;
  3371. data-lanes = <0x01 0x02 0x03>;
  3372. remote-endpoint = <0x6b>;
  3373. phandle = <0x3c>;
  3374. };
  3375. };
  3376.  
  3377. port@5 {
  3378. reg = <0x05>;
  3379.  
  3380. endpoint@5 {
  3381. slave-mode;
  3382. bus-type = <0x01>;
  3383. bus-width = <0x03>;
  3384. clock-lanes = <0x00>;
  3385. data-lanes = <0x01 0x02 0x03>;
  3386. remote-endpoint = <0x6c>;
  3387. phandle = <0x3d>;
  3388. };
  3389. };
  3390.  
  3391. port@6 {
  3392. reg = <0x06>;
  3393.  
  3394. endpoint@6 {
  3395. slave-mode;
  3396. bus-type = <0x01>;
  3397. bus-width = <0x03>;
  3398. clock-lanes = <0x00>;
  3399. data-lanes = <0x01 0x02 0x03>;
  3400. remote-endpoint = <0x6d>;
  3401. phandle = <0x3e>;
  3402. };
  3403. };
  3404.  
  3405. port@7 {
  3406. reg = <0x07>;
  3407.  
  3408. endpoint@7 {
  3409. slave-mode;
  3410. bus-type = <0x01>;
  3411. bus-width = <0x03>;
  3412. clock-lanes = <0x00>;
  3413. data-lanes = <0x01 0x02 0x03>;
  3414. remote-endpoint = <0x6e>;
  3415. phandle = <0x3f>;
  3416. };
  3417. };
  3418. };
  3419. };
  3420.  
  3421. csis1@23050000 {
  3422. compatible = "tesla,fsd-hw4-csis";
  3423. reg = <0x00 0x23050000 0x00 0x5000 0x00 0x23090000 0x00 0x1000>;
  3424. interrupts = <0x00 0x34 0x04>;
  3425. clocks = <0x64 0x06 0x64 0x0b 0x64 0x07>;
  3426. clock-names = "csis1-aclk\0csis1-phy-pclk\0csis1-pclk";
  3427. iommus = <0x65 0x01>;
  3428. syscon = <0x66>;
  3429. status = "okay";
  3430.  
  3431. ports {
  3432. #address-cells = <0x01>;
  3433. #size-cells = <0x00>;
  3434.  
  3435. port@0 {
  3436. reg = <0x00>;
  3437.  
  3438. endpoint@0 {
  3439. slave-mode;
  3440. bus-type = <0x01>;
  3441. bus-width = <0x03>;
  3442. clock-lanes = <0x00>;
  3443. data-lanes = <0x01 0x02 0x03>;
  3444. remote-endpoint = <0x6f>;
  3445. phandle = <0x41>;
  3446. };
  3447. };
  3448.  
  3449. port@1 {
  3450. reg = <0x01>;
  3451.  
  3452. endpoint@1 {
  3453. slave-mode;
  3454. bus-type = <0x01>;
  3455. bus-width = <0x03>;
  3456. clock-lanes = <0x00>;
  3457. data-lanes = <0x01 0x02 0x03>;
  3458. remote-endpoint = <0x70>;
  3459. phandle = <0x42>;
  3460. };
  3461. };
  3462.  
  3463. port@2 {
  3464. reg = <0x02>;
  3465.  
  3466. endpoint@2 {
  3467. slave-mode;
  3468. bus-type = <0x01>;
  3469. bus-width = <0x03>;
  3470. clock-lanes = <0x00>;
  3471. data-lanes = <0x01 0x02 0x03>;
  3472. remote-endpoint = <0x71>;
  3473. phandle = <0x43>;
  3474. };
  3475. };
  3476.  
  3477. port@3 {
  3478. reg = <0x03>;
  3479.  
  3480. endpoint@3 {
  3481. slave-mode;
  3482. bus-type = <0x01>;
  3483. bus-width = <0x03>;
  3484. clock-lanes = <0x00>;
  3485. data-lanes = <0x01 0x02 0x03>;
  3486. remote-endpoint = <0x72>;
  3487. phandle = <0x44>;
  3488. };
  3489. };
  3490.  
  3491. port@4 {
  3492. reg = <0x04>;
  3493.  
  3494. endpoint@4 {
  3495. slave-mode;
  3496. bus-type = <0x01>;
  3497. bus-width = <0x03>;
  3498. clock-lanes = <0x00>;
  3499. data-lanes = <0x01 0x02 0x03>;
  3500. remote-endpoint = <0x73>;
  3501. phandle = <0x45>;
  3502. };
  3503. };
  3504.  
  3505. port@5 {
  3506. reg = <0x05>;
  3507.  
  3508. endpoint@5 {
  3509. slave-mode;
  3510. bus-type = <0x01>;
  3511. bus-width = <0x03>;
  3512. clock-lanes = <0x00>;
  3513. data-lanes = <0x01 0x02 0x03>;
  3514. remote-endpoint = <0x74>;
  3515. phandle = <0x46>;
  3516. };
  3517. };
  3518.  
  3519. port@6 {
  3520. reg = <0x06>;
  3521.  
  3522. endpoint@6 {
  3523. slave-mode;
  3524. bus-type = <0x01>;
  3525. bus-width = <0x03>;
  3526. clock-lanes = <0x00>;
  3527. data-lanes = <0x01 0x02 0x03>;
  3528. remote-endpoint = <0x75>;
  3529. phandle = <0x47>;
  3530. };
  3531. };
  3532.  
  3533. port@7 {
  3534. reg = <0x07>;
  3535.  
  3536. endpoint@7 {
  3537. slave-mode;
  3538. bus-type = <0x01>;
  3539. bus-width = <0x03>;
  3540. clock-lanes = <0x00>;
  3541. data-lanes = <0x01 0x02 0x03>;
  3542. remote-endpoint = <0x76>;
  3543. phandle = <0x48>;
  3544. };
  3545. };
  3546. };
  3547. };
  3548.  
  3549. csis2@23060000 {
  3550. compatible = "tesla,fsd-hw4-csis";
  3551. reg = <0x00 0x23060000 0x00 0x5000 0x00 0x230a0000 0x00 0x1000>;
  3552. interrupts = <0x00 0x38 0x04>;
  3553. clocks = <0x64 0x08 0x64 0x0c 0x64 0x09>;
  3554. clock-names = "csis2-aclk\0csis2-phy-pclk\0csis2-pclk";
  3555. iommus = <0x65 0x02>;
  3556. syscon = <0x66>;
  3557. status = "okay";
  3558.  
  3559. ports {
  3560. #address-cells = <0x01>;
  3561. #size-cells = <0x00>;
  3562.  
  3563. port@0 {
  3564. reg = <0x00>;
  3565.  
  3566. endpoint@0 {
  3567. slave-mode;
  3568. bus-type = <0x01>;
  3569. bus-width = <0x03>;
  3570. clock-lanes = <0x00>;
  3571. data-lanes = <0x01 0x02 0x03>;
  3572. remote-endpoint = <0x77>;
  3573. phandle = <0x4a>;
  3574. };
  3575. };
  3576.  
  3577. port@1 {
  3578. reg = <0x01>;
  3579.  
  3580. endpoint@1 {
  3581. slave-mode;
  3582. bus-type = <0x01>;
  3583. bus-width = <0x03>;
  3584. clock-lanes = <0x00>;
  3585. data-lanes = <0x01 0x02 0x03>;
  3586. remote-endpoint = <0x78>;
  3587. phandle = <0x4b>;
  3588. };
  3589. };
  3590.  
  3591. port@2 {
  3592. reg = <0x02>;
  3593.  
  3594. endpoint@2 {
  3595. slave-mode;
  3596. bus-type = <0x01>;
  3597. bus-width = <0x03>;
  3598. clock-lanes = <0x00>;
  3599. data-lanes = <0x01 0x02 0x03>;
  3600. remote-endpoint = <0x79>;
  3601. phandle = <0x4c>;
  3602. };
  3603. };
  3604.  
  3605. port@3 {
  3606. reg = <0x03>;
  3607.  
  3608. endpoint@3 {
  3609. slave-mode;
  3610. bus-type = <0x01>;
  3611. bus-width = <0x03>;
  3612. clock-lanes = <0x00>;
  3613. data-lanes = <0x01 0x02 0x03>;
  3614. remote-endpoint = <0x7a>;
  3615. phandle = <0x4d>;
  3616. };
  3617. };
  3618.  
  3619. port@4 {
  3620. reg = <0x04>;
  3621.  
  3622. endpoint@4 {
  3623. slave-mode;
  3624. bus-type = <0x01>;
  3625. bus-width = <0x03>;
  3626. clock-lanes = <0x00>;
  3627. data-lanes = <0x01 0x02 0x03>;
  3628. remote-endpoint = <0x7b>;
  3629. phandle = <0x4e>;
  3630. };
  3631. };
  3632.  
  3633. port@5 {
  3634. reg = <0x05>;
  3635.  
  3636. endpoint@5 {
  3637. slave-mode;
  3638. bus-type = <0x01>;
  3639. bus-width = <0x03>;
  3640. clock-lanes = <0x00>;
  3641. data-lanes = <0x01 0x02 0x03>;
  3642. remote-endpoint = <0x7c>;
  3643. phandle = <0x4f>;
  3644. };
  3645. };
  3646.  
  3647. port@6 {
  3648. reg = <0x06>;
  3649.  
  3650. endpoint@6 {
  3651. slave-mode;
  3652. bus-type = <0x01>;
  3653. bus-width = <0x03>;
  3654. clock-lanes = <0x00>;
  3655. data-lanes = <0x01 0x02 0x03>;
  3656. remote-endpoint = <0x7d>;
  3657. phandle = <0x50>;
  3658. };
  3659. };
  3660.  
  3661. port@7 {
  3662. reg = <0x07>;
  3663.  
  3664. endpoint@7 {
  3665. slave-mode;
  3666. bus-type = <0x01>;
  3667. bus-width = <0x03>;
  3668. clock-lanes = <0x00>;
  3669. data-lanes = <0x01 0x02 0x03>;
  3670. remote-endpoint = <0x7e>;
  3671. phandle = <0x51>;
  3672. };
  3673. };
  3674. };
  3675. };
  3676.  
  3677. tcu_isp0@22A00000 {
  3678. compatible = "arm,smmu-v3";
  3679. reg = <0x00 0x22a00000 0x00 0x20000>;
  3680. interrupts = <0x00 0x7a 0x01 0x00 0x78 0x01 0x00 0x7d 0x01>;
  3681. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3682. #iommu-cells = <0x01>;
  3683. dma-coherent;
  3684. status = "okay";
  3685. phandle = <0x80>;
  3686. };
  3687.  
  3688. tcu_isp1@22E00000 {
  3689. compatible = "arm,smmu-v3";
  3690. reg = <0x00 0x22e00000 0x00 0x20000>;
  3691. interrupts = <0x00 0x8e 0x01 0x00 0x8c 0x01 0x00 0x91 0x01>;
  3692. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3693. #iommu-cells = <0x01>;
  3694. dma-coherent;
  3695. status = "okay";
  3696. phandle = <0x82>;
  3697. };
  3698.  
  3699. isp@0x22840000 {
  3700. compatible = "arm,mali-c71";
  3701. reg = <0x00 0x22840000 0x00 0x20000>;
  3702. reg-names = "isp_reg";
  3703. interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04>;
  3704. interrupt-names = "CORE0\0CORE1\0CORE2\0CORE3\0MEM_ECC1\0MEM_ECC2";
  3705. clocks = <0x7f 0x01>;
  3706. clock-names = "clock_isp0";
  3707. iommus = <0x80 0x00>;
  3708. status = "okay";
  3709. };
  3710.  
  3711. isp@0x22C40000 {
  3712. compatible = "arm,mali-c71";
  3713. reg = <0x00 0x22c40000 0x00 0x20000>;
  3714. reg-names = "isp_reg";
  3715. interrupts = <0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04>;
  3716. interrupt-names = "CORE0\0CORE1\0CORE2\0CORE3\0MEM_ECC1\0MEM_ECC2";
  3717. clocks = <0x81 0x01>;
  3718. clock-names = "clock_isp1";
  3719. iommus = <0x82 0x00>;
  3720. status = "okay";
  3721. };
  3722.  
  3723. tcu_mfc0@23A00000 {
  3724. compatible = "arm,smmu-v3";
  3725. reg = <0x00 0x23a00000 0x00 0x20000>;
  3726. interrupts = <0x00 0xe3 0x01 0x00 0xe5 0x01 0x00 0xe7 0x01>;
  3727. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3728. #iommu-cells = <0x01>;
  3729. dma-coherent;
  3730. status = "okay";
  3731. phandle = <0x84>;
  3732. };
  3733.  
  3734. tcu_mfc0_pmcg@23A02000 {
  3735. compatible = "arm-smmu-v3-pmu";
  3736. reg = <0x00 0x23a02000 0x00 0x1000 0x00 0x23a22000 0x00 0xe00>;
  3737. interrupts = <0x00 0xe9 0x01>;
  3738. status = "disabled";
  3739. };
  3740.  
  3741. tcu_mfc1@23E00000 {
  3742. compatible = "arm,smmu-v3";
  3743. reg = <0x00 0x23e00000 0x00 0x20000>;
  3744. interrupts = <0x00 0xf6 0x01 0x00 0xf8 0x01 0x00 0xfa 0x01>;
  3745. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3746. #iommu-cells = <0x01>;
  3747. dma-coherent;
  3748. status = "okay";
  3749. phandle = <0x86>;
  3750. };
  3751.  
  3752. tcu_mfc1_pmcg@23E02000 {
  3753. compatible = "arm-smmu-v3-pmu";
  3754. reg = <0x00 0x23e02000 0x00 0x1000 0x00 0x23e22000 0x00 0xe00>;
  3755. interrupts = <0x00 0xfc 0x01>;
  3756. status = "disabled";
  3757. };
  3758.  
  3759. mfc0@23880000 {
  3760. compatible = "samsung,mfc-v12";
  3761. reg = <0x00 0x23880000 0x00 0xfe14>;
  3762. interrupts = <0x00 0xe1 0x04>;
  3763. clock-names = "mfc";
  3764. clocks = <0x83 0x09>;
  3765. iommus = <0x84 0x00>;
  3766. status = "okay";
  3767. };
  3768.  
  3769. mfc1@23C80000 {
  3770. compatible = "samsung,mfc-v12";
  3771. reg = <0x00 0x23c80000 0x00 0xfe14>;
  3772. interrupts = <0x00 0xf4 0x04>;
  3773. clock-names = "mfc";
  3774. clocks = <0x85 0x09>;
  3775. iommus = <0x86 0x00>;
  3776. status = "okay";
  3777. };
  3778.  
  3779. tcu_trip0@20200000 {
  3780. compatible = "arm,smmu-v3";
  3781. reg = <0x00 0x20200000 0x00 0x20000>;
  3782. interrupts = <0x00 0x194 0x01 0x00 0x196 0x01 0x00 0x198 0x01>;
  3783. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3784. #iommu-cells = <0x01>;
  3785. dma-coherent;
  3786. status = "okay";
  3787. phandle = <0x87>;
  3788. };
  3789.  
  3790. tcu_trip1@20600000 {
  3791. compatible = "arm,smmu-v3";
  3792. reg = <0x00 0x20600000 0x00 0x20000>;
  3793. interrupts = <0x00 0x1b9 0x01 0x00 0x1bb 0x01 0x00 0x1bd 0x01>;
  3794. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3795. #iommu-cells = <0x01>;
  3796. dma-coherent;
  3797. status = "okay";
  3798. phandle = <0x8b>;
  3799. };
  3800.  
  3801. tcu_trip2@20A00000 {
  3802. compatible = "arm,smmu-v3";
  3803. reg = <0x00 0x20a00000 0x00 0x20000>;
  3804. interrupts = <0x00 0x1de 0x01 0x00 0x1e0 0x01 0x00 0x1e2 0x01>;
  3805. interrupt-names = "eventq\0cmdq-sync\0gerror";
  3806. #iommu-cells = <0x01>;
  3807. dma-coherent;
  3808. status = "okay";
  3809. phandle = <0x8e>;
  3810. };
  3811.  
  3812. trip@13FFE000 {
  3813. compatible = "tesla,trip";
  3814. reg = <0x00 0x13ffe000 0x00 0x2000 0x00 0x10000000 0x00 0x3000000>;
  3815. interrupts = <0x00 0x17a 0x04 0x00 0x17b 0x04 0x00 0x17c 0x04 0x00 0x17d 0x04 0x00 0x17e 0x04 0x00 0x17f 0x04 0x00 0x180 0x04 0x00 0x181 0x04 0x00 0x182 0x04 0x00 0x183 0x04 0x00 0x184 0x04 0x00 0x185 0x04 0x00 0x186 0x04 0x00 0x187 0x04 0x00 0x188 0x04 0x00 0x189 0x04 0x00 0x18a 0x04 0x00 0x192 0x04>;
  3816. iommus = <0x87 0x00>;
  3817. #clock-cells = <0x01>;
  3818. clocks = <0x88 0x18>;
  3819. clock-names = "fout_pll_trip";
  3820. operating-points-v2 = <0x89>;
  3821. trip-supply = <0x8a>;
  3822. #cooling-cells = <0x02>;
  3823. status = "okay";
  3824. dma-coherent;
  3825. firmware = "trip0.fw";
  3826. phandle = <0x93>;
  3827. };
  3828.  
  3829. trip@17FFE000 {
  3830. compatible = "tesla,trip";
  3831. reg = <0x00 0x17ffe000 0x00 0x2000 0x00 0x14000000 0x00 0x3000000>;
  3832. interrupts = <0x00 0x19f 0x04 0x00 0x1a0 0x04 0x00 0x1a1 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x1a4 0x04 0x00 0x1a5 0x04 0x00 0x1a6 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x1aa 0x04 0x00 0x1ab 0x04 0x00 0x1ac 0x04 0x00 0x1ad 0x04 0x00 0x1ae 0x04 0x00 0x1af 0x04 0x00 0x1b7 0x04>;
  3833. iommus = <0x8b 0x00>;
  3834. #clock-cells = <0x01>;
  3835. clocks = <0x8c 0x18>;
  3836. clock-names = "fout_pll_trip";
  3837. operating-points-v2 = <0x8d>;
  3838. trip-supply = <0x8a>;
  3839. #cooling-cells = <0x02>;
  3840. status = "okay";
  3841. dma-coherent;
  3842. firmware = "trip1.fw";
  3843. phandle = <0x94>;
  3844. };
  3845.  
  3846. trip@1BFFE000 {
  3847. compatible = "tesla,trip";
  3848. reg = <0x00 0x1bffe000 0x00 0x2000 0x00 0x18000000 0x00 0x3000000>;
  3849. interrupts = <0x00 0x1c4 0x04 0x00 0x1c5 0x04 0x00 0x1c6 0x04 0x00 0x1c7 0x04 0x00 0x1c8 0x04 0x00 0x1c9 0x04 0x00 0x1ca 0x04 0x00 0x1cb 0x04 0x00 0x1cc 0x04 0x00 0x1cd 0x04 0x00 0x1ce 0x04 0x00 0x1cf 0x04 0x00 0x1d0 0x04 0x00 0x1d1 0x04 0x00 0x1d2 0x04 0x00 0x1d3 0x04 0x00 0x1d4 0x04 0x00 0x1dc 0x04>;
  3850. iommus = <0x8e 0x00>;
  3851. #clock-cells = <0x01>;
  3852. clocks = <0x8f 0x18>;
  3853. clock-names = "fout_pll_trip";
  3854. operating-points-v2 = <0x90>;
  3855. trip-supply = <0x8a>;
  3856. #cooling-cells = <0x02>;
  3857. status = "okay";
  3858. dma-coherent;
  3859. firmware = "trip2.fw";
  3860. phandle = <0x95>;
  3861. };
  3862.  
  3863. thermal-zones {
  3864.  
  3865. cpu-thermal {
  3866. polling-delay-passive = <0x64>;
  3867. polling-delay = <0x3e8>;
  3868. thermal-sensors = <0x91 0x00>;
  3869. };
  3870.  
  3871. trip0-thermal {
  3872. polling-delay-passive = <0x64>;
  3873. polling-delay = <0x3e8>;
  3874. thermal-sensors = <0x91 0x01>;
  3875. };
  3876.  
  3877. trip1-thermal {
  3878. polling-delay-passive = <0x64>;
  3879. polling-delay = <0x3e8>;
  3880. thermal-sensors = <0x91 0x02>;
  3881. };
  3882.  
  3883. trip2-thermal {
  3884. polling-delay-passive = <0x64>;
  3885. polling-delay = <0x3e8>;
  3886. thermal-sensors = <0x91 0x05>;
  3887. };
  3888.  
  3889. gpu-thermal {
  3890. polling-delay-passive = <0x64>;
  3891. polling-delay = <0x3e8>;
  3892. thermal-sensors = <0x91 0x03>;
  3893. };
  3894.  
  3895. other-thermal {
  3896. polling-delay-passive = <0x64>;
  3897. polling-delay = <0x3e8>;
  3898. thermal-sensors = <0x91 0x04>;
  3899. };
  3900.  
  3901. ddr-thermal {
  3902. polling-delay-passive = <0x64>;
  3903. polling-delay = <0x3e8>;
  3904. thermal-sensors = <0x91 0x06>;
  3905. };
  3906.  
  3907. whole-soc-thermal {
  3908. polling-delay-passive = <0x64>;
  3909. polling-delay = <0x3e8>;
  3910. thermal-sensors = <0x91 0x07>;
  3911.  
  3912. trips {
  3913.  
  3914. high-temperature {
  3915. temperature = <0x186a0>;
  3916. hysteresis = <0x1b58>;
  3917. type = "passive";
  3918. phandle = <0x92>;
  3919. };
  3920.  
  3921. critical-temperature {
  3922. temperature = <0x19a28>;
  3923. hysteresis = <0x00>;
  3924. type = "critical";
  3925. };
  3926. };
  3927.  
  3928. cooling-maps {
  3929.  
  3930. throttle-cpu-clusters-012 {
  3931. trip = <0x92>;
  3932. cooling-device = <0x02 0x02 0x02>;
  3933. };
  3934.  
  3935. throttle-trip-0 {
  3936. trip = <0x92>;
  3937. cooling-device = <0x93 0x03 0x03>;
  3938. };
  3939.  
  3940. throttle-trip-1 {
  3941. trip = <0x92>;
  3942. cooling-device = <0x94 0x03 0x03>;
  3943. };
  3944.  
  3945. throttle-trip-2 {
  3946. trip = <0x92>;
  3947. cooling-device = <0x95 0x03 0x03>;
  3948. };
  3949. };
  3950. };
  3951. };
  3952.  
  3953. tripmem@180000000 {
  3954. compatible = "tesla,tripmem";
  3955. memory-region = <0x96>;
  3956. ecc;
  3957. status = "okay";
  3958. };
  3959.  
  3960. tripmem@170000000 {
  3961. compatible = "tesla,tripmem";
  3962. memory-region = <0x97>;
  3963. ecc;
  3964. status = "okay";
  3965. dma-coherent;
  3966. };
  3967.  
  3968. ethernet@7f700000 {
  3969. compatible = "tesla,dwc-qos-ethernet-4.21";
  3970. reg = <0x00 0x7f700000 0x00 0x10000 0x00 0x7fcc0000 0x00 0x1000>;
  3971. reg-names = "stmmaceth\0sgmii_phy";
  3972. interrupts = <0x00 0x14b 0x04>;
  3973. clocks = <0x2c 0x58 0x11 0x58 0x39 0x58 0x33 0x58 0x36 0x58 0x32>;
  3974. clock-names = "ptp_ref\0master_bus\0slave_bus\0tx\0rx\0eqos_div_aclk";
  3975. iommus = <0x5a 0x04>;
  3976. dma-coherent;
  3977. phy-ref-clock-mux = <0x59 0x53c 0x03>;
  3978. rx-clock-mux = <0x58 0x1000 0x01>;
  3979. tx-clock-mux = <0x58 0x1004 0x01>;
  3980. status = "okay";
  3981. mac-mode = [00];
  3982. phy-mode = "sgmii";
  3983. phy-drive-strength = <0x07>;
  3984. local-mac-address = [45 54 48 30 4d 43];
  3985. use-phy = "NONE_PHY";
  3986. enable-extended-ipg;
  3987. extended-ipg-val = <0x01>;
  3988. snps,mtl-rx-config = <0x98>;
  3989. snps,mtl-tx-config = <0x99>;
  3990.  
  3991. fixed-link {
  3992. speed = <0x3e8>;
  3993. full-duplex;
  3994. };
  3995.  
  3996. rx-queues-config {
  3997. snps,rx-queues-to-use = <0x01>;
  3998. phandle = <0x98>;
  3999.  
  4000. queue0 {
  4001. };
  4002. };
  4003.  
  4004. tx-queues-config {
  4005. snps,tx-queues-to-use = <0x01>;
  4006. phandle = <0x99>;
  4007.  
  4008. queue0 {
  4009. };
  4010. };
  4011. };
  4012.  
  4013. ethernet@25300000 {
  4014. compatible = "tesla,dwc-qos-ethernet-4.21";
  4015. reg = <0x00 0x25300000 0x00 0x10000>;
  4016. reg-names = "stmmaceth";
  4017. interrupts = <0x00 0xce 0x04>;
  4018. clocks = <0x2c 0x1f 0x40 0x1f 0x41 0x1f 0x42 0x1f 0x45 0x1f 0x3e 0x1f 0x49 0x1f 0x48 0x1f 0x4a>;
  4019. clock-names = "ptp_ref\0master_bus\0slave_bus\0tx\0rx\0eqos_div_aclk\0eqos_rxclk_mux\0eqos_phyrxclk\0dout_peric_rgmii_clk";
  4020. rx-clock-skew = <0x53 0x10 0x01>;
  4021. iommus = <0x2b 0x02>;
  4022. dma-coherent;
  4023. status = "okay";
  4024. phy-mode = [00];
  4025. pinctrl-names = "default";
  4026. pinctrl-0 = <0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0>;
  4027. local-mac-address = [45 54 48 31 4d 43];
  4028. use-phy = "NONE_PHY";
  4029. snps,mtl-rx-config = <0xa1>;
  4030. snps,mtl-tx-config = <0xa2>;
  4031.  
  4032. fixed-link {
  4033. speed = <0x3e8>;
  4034. full-duplex;
  4035. };
  4036.  
  4037. rx-queues-config {
  4038. snps,enable-pfc;
  4039. snps,rx-queues-to-use = <0x02>;
  4040. phandle = <0xa1>;
  4041.  
  4042. queue0 {
  4043. snps,priority = <0x01>;
  4044. };
  4045.  
  4046. queue1 {
  4047. snps,priority = <0x02>;
  4048. };
  4049. };
  4050.  
  4051. tx-queues-config {
  4052. snps,tx-queues-to-use = <0x02>;
  4053. snps,tx-sched-wrr;
  4054. phandle = <0xa2>;
  4055.  
  4056. queue0 {
  4057. snps,priority = <0x00>;
  4058. };
  4059.  
  4060. queue1 {
  4061. snps,priority = <0x01>;
  4062. };
  4063. };
  4064. };
  4065.  
  4066. ufs0@25200000 {
  4067. compatible = "tesla,fsd-hw4-ufs";
  4068. reg = <0x00 0x25200000 0x00 0x200 0x00 0x25201100 0x00 0x200 0x00 0x25280000 0x00 0x8000 0x00 0x25220000 0x00 0x100 0x00 0x25204000 0x00 0x800>;
  4069. reg-names = "hci\0vs_hci\0unipro\0ufsp\0ufs_phy";
  4070. interrupts = <0x00 0xcd 0x04>;
  4071. pinctrl-names = "default";
  4072. pinctrl-0 = <0xa3 0xa4 0xa5>;
  4073. clocks = <0x1f 0x32 0x1f 0x35>;
  4074. clock-names = "core_clk\0sclk_unipro_main";
  4075. freq-table-hz = <0x00 0x00 0x00 0x00>;
  4076. pclk-freq-avail-range = <0x16e3600 0x7ed6b40>;
  4077. ufs,pwr-local-l2-timer = <0x1f40 0x6d60 0x4e20>;
  4078. ufs,pwr-remote-l2-timer = <0x2ee0 0x7d00 0x3e80>;
  4079. ufs,ufs_addr_bus_width = <0x24>;
  4080. ufs,pwr-attr-mode = "FAST";
  4081. ufs,pwr-attr-lane = <0x02>;
  4082. ufs,pwr-attr-gear = <0x03>;
  4083. ufs,pwr-attr-hs-series = "HS_rate_b";
  4084. ufs-rx-adv-fine-gran-sup_en = <0x01>;
  4085. ufs-rx-adv-fine-gran-step = <0x03>;
  4086. ufs-rx-adv-min-activate-time-cap = <0x03>;
  4087. ufs-pa-granularity = <0x06>;
  4088. ufs-pa-tacctivate = <0x03>;
  4089. ufs-pa-hibern8time = <0x02>;
  4090. ufs-prdt-size-bit = <0x0c>;
  4091. iommus = <0x2b 0x03>;
  4092. status = "okay";
  4093. };
  4094.  
  4095. edac@21870000 {
  4096. compatible = "tesla,fsd-edac";
  4097. reg = <0x00 0x21870000 0x00 0x1000>;
  4098. interrupts = <0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x40 0x04 0x00 0x41 0x04>;
  4099. channel_id = <0x00>;
  4100. status = "okay";
  4101. };
  4102.  
  4103. edac@21970000 {
  4104. compatible = "tesla,fsd-edac";
  4105. reg = <0x00 0x21970000 0x00 0x1000>;
  4106. interrupts = <0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x42 0x04 0x00 0x43 0x04>;
  4107. channel_id = <0x01>;
  4108. status = "okay";
  4109. };
  4110.  
  4111. edac@21a70000 {
  4112. compatible = "tesla,fsd-edac";
  4113. reg = <0x00 0x21a70000 0x00 0x1000>;
  4114. interrupts = <0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x48 0x04 0x00 0x49 0x04>;
  4115. channel_id = <0x02>;
  4116. status = "okay";
  4117. };
  4118.  
  4119. edac@21b70000 {
  4120. compatible = "tesla,fsd-edac";
  4121. reg = <0x00 0x21b70000 0x00 0x1000>;
  4122. interrupts = <0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x4a 0x04 0x00 0x4b 0x04>;
  4123. channel_id = <0x03>;
  4124. status = "okay";
  4125. };
  4126.  
  4127. edac@21c70000 {
  4128. compatible = "tesla,fsd-edac";
  4129. reg = <0x00 0x21c70000 0x00 0x1000>;
  4130. interrupts = <0x00 0x4c 0x04 0x00 0x4d 0x04 0x00 0x50 0x04 0x00 0x51 0x04>;
  4131. channel_id = <0x04>;
  4132. status = "okay";
  4133. };
  4134.  
  4135. edac@21d70000 {
  4136. compatible = "tesla,fsd-edac";
  4137. reg = <0x00 0x21d70000 0x00 0x1000>;
  4138. interrupts = <0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x52 0x04 0x00 0x53 0x04>;
  4139. channel_id = <0x05>;
  4140. status = "okay";
  4141. };
  4142.  
  4143. edac@21e70000 {
  4144. compatible = "tesla,fsd-edac";
  4145. reg = <0x00 0x21e70000 0x00 0x1000>;
  4146. interrupts = <0x00 0x54 0x04 0x00 0x55 0x04 0x00 0x58 0x04 0x00 0x59 0x04>;
  4147. channel_id = <0x06>;
  4148. status = "okay";
  4149. };
  4150.  
  4151. edac@21f70000 {
  4152. compatible = "tesla,fsd-edac";
  4153. reg = <0x00 0x21f70000 0x00 0x1000>;
  4154. interrupts = <0x00 0x56 0x04 0x00 0x57 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04>;
  4155. channel_id = <0x07>;
  4156. status = "okay";
  4157. };
  4158.  
  4159. mailbox@10080000 {
  4160. compatible = "tesla,scs-mailbox-client";
  4161. reg = <0x00 0x10080000 0x00 0x200>;
  4162. mboxes = <0x1d 0x00 0x1d 0x00>;
  4163. mbox-names = "scs_lo\0scs_hi";
  4164. status = "okay";
  4165. };
  4166.  
  4167. scs_flash_v2 {
  4168. compatible = "tesla,fsd-scs-flash";
  4169. memory-region = <0xa6>;
  4170. status = "okay";
  4171. };
  4172.  
  4173. mailbox@10090000 {
  4174. compatible = "tesla,sms-mailbox-client";
  4175. reg = <0x00 0x10090000 0x00 0x200>;
  4176. mboxes = <0x1d 0x00 0x1d 0x00>;
  4177. mbox-names = "sms_lo\0sms_hi";
  4178. status = "okay";
  4179. };
  4180. };
  4181.  
  4182. pps {
  4183. compatible = "pps-gpio";
  4184. gpios = <0x32 0x04 0x00>;
  4185. pinctrl-names = "default";
  4186. pinctrl-0 = <0xa7>;
  4187. status = "okay";
  4188. };
  4189.  
  4190. pci-epf {
  4191. vendor_id = [1e 3c];
  4192. device_id = [1c 1c];
  4193. msi_interrupts = [02];
  4194. };
  4195.  
  4196. firmware {
  4197. #address-cells = <0x02>;
  4198. #size-cells = <0x02>;
  4199. ranges;
  4200.  
  4201. tesla {
  4202. board_version = "TURBO_BOARD_VERSION_TOKEN_STRING";
  4203. turbo_a_b = "TURBO_A_B_TOKEN_STRING";
  4204. otp_chip_id = "TURBO_OTP_CHIP_ID_32_TOKEN_STRING";
  4205. soc_id = "TURBO_SOC_ID_TOKEN_STRING";
  4206. bootfrom = "BOOTFROM_TOKEN_STRING";
  4207. bootxfrom = "BOOTXFROM_TOKEN_STRING";
  4208. ap_warm_reset = "AP_WARM_RESET_STRING";
  4209. bootblock_version = "BOOTBLOCK_VERSION_TOKEN_STRING";
  4210. coreboot_version = "COREBOOT_VERSION_TOKEN_STRING";
  4211. coreboot_extra_version = "COREBOOT_EXTRA_VERSION_TOKEN_STRING";
  4212. coreboot_build = "COREBOOT_BUILD_TOKEN_LONG_STRING";
  4213. board_pcba_version = "BOARD_PCBA_VERSION_TOKEN_STRING";
  4214. sssbl1_build_git_hash = "SSSBL1_BUILD_GIT_HASH_TOKEN_STRING_1234567890";
  4215. sgkbl1_build_git_hash = "SGKBL1_BUILD_GIT_HASH_TOKEN_STRING_1234567890";
  4216. ddr_vendor = "DDR_VENDOR_TOKEN_STRING";
  4217. bootx_bl1_data_ver = "BOOTX_BL1_DATA_VER_STRING";
  4218. hw_minor = "TURBO_HW_MINOR_TOKEN_STRING";
  4219. bootx_boot_rom_ver = "BOOTX_BOOT_ROM_VER_STRING";
  4220. turbo_hpm_asv = "TURBO_OTP_HPM_ASV";
  4221. };
  4222.  
  4223. coreboot {
  4224. compatible = "coreboot";
  4225. reg = <0x00 0xfffda000 0x00 0x2000 0x00 0xfffda000 0x00 0x24000>;
  4226. };
  4227. };
  4228.  
  4229. chosen {
  4230. stdout-path = "/soc/serial@250A0000";
  4231. linux,initrd-start = <0xe0000000>;
  4232. linux,initrd-end = <0xe073118c>;
  4233. bootargs = "console=ttySAC0,115200n8 clk_ignore_unused earlycon root=/dev/ram0 max_loop=1 s3c2410_wdt.reset_interrupt=1";
  4234. };
  4235.  
  4236. memory@80000000 {
  4237. device_type = "memory";
  4238. reg = <0x00 0x80000000 0x03 0x80000000>;
  4239. };
  4240. };
  4241.  
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