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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity modul2 is
port ( X : in STD_LOGIC;
		 CE : in STD_LOGIC;
		 CLK : in STD_LOGIC;
		 CLR : in STD_LOGIC;
		 Y : out  STD_LOGIC);
end modul2;

architecture Behavioral of modul2 is

signal intQ : STD_LOGIC_VECTOR (2 downto 0);
signal intD : STD_LOGIC_VECTOR (2 downto 0);
signal intX : STD_LOGIC_VECTOR (3 downto 0);

begin

FDCE_a : FDCE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => intQ(2), -- Data output
C => CLK, -- Clock input
CE => CE, -- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => intD(2) -- Data input
);

FDCE_b : FDCE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => intQ(1), -- Data output
C => CLK, -- Clock input
CE => CE, -- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => intD(1) -- Data input
);


FDCE_c : FDCE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => intQ(0), -- Data output
C => CLK, -- Clock input
CE => CE, -- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => intD(0) -- Data input
);

intX(3 downto 1) <= intQ;
intX(0) <= X;

with intX select
intD <= "001" when "0000",
		"000" when "0001",
		"010" when "0011",
		"011" when "0101",
		"100" when "0111",
		"101" when "1001",
		"110" when "1011",
		"000" when others;

Y <= '1' when intQ = "110"
	else '0';


end Behavioral;