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  1. ----------------------------------------------------------------------------------
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4.  
  5. -- Uncomment the following library declaration if using
  6. -- arithmetic functions with Signed or Unsigned values
  7. --use IEEE.NUMERIC_STD.ALL;
  8.  
  9. -- Uncomment the following library declaration if instantiating
  10. -- any Xilinx primitives in this code.
  11. library UNISIM;
  12. use UNISIM.VComponents.all;
  13.  
  14. entity modul2 is
  15. port ( X : in STD_LOGIC;
  16.          CE : in STD_LOGIC;
  17.          CLK : in STD_LOGIC;
  18.          CLR : in STD_LOGIC;
  19.          Y : out  STD_LOGIC);
  20. end modul2;
  21.  
  22. architecture Behavioral of modul2 is
  23.  
  24. signal intQ : STD_LOGIC_VECTOR (2 downto 0);
  25. signal intD : STD_LOGIC_VECTOR (2 downto 0);
  26. signal intX : STD_LOGIC_VECTOR (3 downto 0);
  27.  
  28. begin
  29.  
  30. FDCE_a : FDCE
  31. generic map (
  32. INIT => '0') -- Initial value of register ('0' or '1')
  33. port map (
  34. Q => intQ(2), -- Data output
  35. C => CLK, -- Clock input
  36. CE => CE, -- Clock enable input
  37. CLR => CLR, -- Asynchronous clear input
  38. D => intD(2) -- Data input
  39. );
  40.  
  41. FDCE_b : FDCE
  42. generic map (
  43. INIT => '0') -- Initial value of register ('0' or '1')
  44. port map (
  45. Q => intQ(1), -- Data output
  46. C => CLK, -- Clock input
  47. CE => CE, -- Clock enable input
  48. CLR => CLR, -- Asynchronous clear input
  49. D => intD(1) -- Data input
  50. );
  51.  
  52.  
  53. FDCE_c : FDCE
  54. generic map (
  55. INIT => '0') -- Initial value of register ('0' or '1')
  56. port map (
  57. Q => intQ(0), -- Data output
  58. C => CLK, -- Clock input
  59. CE => CE, -- Clock enable input
  60. CLR => CLR, -- Asynchronous clear input
  61. D => intD(0) -- Data input
  62. );
  63.  
  64. intX(3 downto 1) <= intQ;
  65. intX(0) <= X;
  66.  
  67. with intX select
  68. intD <= "001" when "0000",
  69.         "000" when "0001",
  70.         "010" when "0011",
  71.         "011" when "0101",
  72.         "100" when "0111",
  73.         "101" when "1001",
  74.         "110" when "1011", 
  75.         "000" when others;
  76.  
  77. Y <= '1' when intQ = "110"
  78.     else '0';
  79.  
  80.  
  81. end Behavioral;
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