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-- Company:
-- Engineer:
--
-- Create Date: 03/21/2019 10:25:30 AM
-- Design Name:
-- Module Name: sum_8b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sum_8b is
    Port ( x    : in STD_LOGIC_VECTOR (7 downto 0);
           y    : in STD_LOGIC_VECTOR (7 downto 0);
           tin  : in STD_LOGIC;
           s    : out STD_LOGIC_VECTOR (7 downto 0);
           tout : out STD_LOGIC);
end sum_8b;

architecture Behavioral of sum_8b is

signal p : std_logic_vector (3 downto 0) := "0000";
signal g : std_logic_vector (3 downto 0) := "0000";
signal t : std_logic_vector (3 downto 0) := "0000";

begin

    sum_10: entity WORK.sum_2b port map (
                    x => x (1 downto 0),
                    y => y (1 downto 0),
                    t => tin,
                    s => s (1 downto 0),
                    p => p(0),
                    g => g(0));

    sum_32: entity WORK.sum_2b port map (
                    x => x (3 downto 2),
                    y => y (3 downto 2),
                    t => t(0),
                    s => s (3 downto 2),
                    p => p(1),
                    g => g(1));

    sum_54: entity WORK.sum_2b port map (
                    x => x (5 downto 4),
                    y => y (5 downto 4),
                    t => t(1),
                    s => s (5 downto 4),
                    p => p(2),
                    g => g(2));

    sum_76: entity WORK.sum_2b port map (
                    x => x (7 downto 6),
                    y => y (7 downto 6),
                    t => t(2),
                    s => s (7 downto 6),
                    p => p(3),
                    g => g(3));

    gen_t0: entity WORK.gen_t port map(
                    p => p,
                    g => g,
                    t0 => tin,
                    t => t);

end Behavioral;