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AlvarEriksson

TCB2 cbmem_c

AlvarEriksson
Nov 7th, 2022
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  4. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 bootblock starting (log level: 7)...
  5. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x604000.
  6. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 6
  7. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  8. [INFO ] CBFS: mcache @0xfe002e00 built for 17 files, used 0x374 of 0x4000 bytes
  9. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x65d0 in mcache @0xfe002e2c
  10. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  11.  
  12.  
  13. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 romstage starting (log level: 7)...
  14. [DEBUG] Enabling VR PS2 mode: VNN VCC
  15. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  16. [INFO ] CBFS: Found 'spd.bin' @0x39c00 size 0x400 in mcache @0xfe002f98
  17. [DEBUG] ram_id=2, total_spds: 4
  18. [DEBUG] pm1_sts: a100 pm1_en: 0100 pm1_cnt: 00001c00
  19. [DEBUG] gpe0_sts: 01020000 gpe0_en: 00000000 tco_sts: 00000000
  20. [DEBUG] prsts: 04450900 gen_pmcon1: 00001038 gen_pmcon2: 00000200
  21. [DEBUG] prev_sleep_state = S5
  22. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  23. [INFO ] CBFS: Found 'mrc.bin' @0x19adc0 size 0x11218 in mcache @0xfe0030f0
  24. BayTrail-MD MRC wrapper v5
  25. Training for Memory Down designs.
  26. Applying weaker ODT settings. DRAM ODT is 120.
  27. [DEBUG] CBMEM:
  28. [DEBUG] IMD: root @ 0x7afff000 254 entries.
  29. [DEBUG] IMD: root @ 0x7affec00 62 entries.
  30. [DEBUG] FMAP: area RO_VPD found @ 600000 (16384 bytes)
  31. [ERROR] init_vpd_rdev: No RW_VPD FMAP section.
  32. [DEBUG] External stage cache:
  33. [DEBUG] IMD: root @ 0x7b7ff000 254 entries.
  34. [DEBUG] IMD: root @ 0x7b7fec00 62 entries.
  35. [INFO ] MRC v0.97
  36. [INFO ] 2 channels of DDR3 @ 1333MHz
  37. [DEBUG] CBMEM entry for DIMM info: 0x7afdb000
  38. [DEBUG] MRC Wrapper returned 0
  39. [DEBUG] MRC data at 0xfe00965f 5719 bytes
  40. [DEBUG] SMM Memory Map
  41. [DEBUG] SMRAM : 0x7b000000 0x800000
  42. [DEBUG] Subregion 0: 0x7b000000 0x700000
  43. [DEBUG] Subregion 1: 0x7b700000 0x100000
  44. [DEBUG] Subregion 2: 0x7b800000 0x0
  45. [DEBUG] Normal boot
  46. [INFO ] CBFS: Found 'fallback/postcar' @0x51580 size 0x566c in mcache @0xfe003080
  47. [DEBUG] Loading module at 0x7afcd000 with entry 0x7afcd031. filesize: 0x52e0 memsize: 0xb618
  48. [DEBUG] Processing 211 relocs. Offset value of 0x78fcd000
  49. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  50.  
  51.  
  52. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 postcar starting (log level: 7)...
  53. [DEBUG] Normal boot
  54. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  55. [INFO ] CBFS: Found 'fallback/ramstage' @0x1ff40 size 0x1937f in mcache @0x7afdd0dc
  56. [DEBUG] Loading module at 0x7af7a000 with entry 0x7af7a000. filesize: 0x3a978 memsize: 0x51390
  57. [DEBUG] Processing 3521 relocs. Offset value of 0x76f7a000
  58. [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
  59.  
  60.  
  61. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 ramstage starting (log level: 7)...
  62. [DEBUG] Normal boot
  63. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  64. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6700 size 0x19800 in mcache @0x7afdd0ac
  65. [DEBUG] microcode: sig=0x30678 pf=0x8 revision=0x838
  66. [DEBUG] BYT: cpuid 00030678 cpus 2 rid 0e step C0
  67. [DEBUG] msr(17) = 000c000090341f4b
  68. [DEBUG] msr(ce) = 0000060000001a00
  69. [DEBUG] ModPHY init entry
  70. [DEBUG] SOC B0 and later ModPhy Table programming
  71. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  72. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  73. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  74. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  75. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  76. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  77. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  78. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  79. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  80. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  81. [DEBUG] ModPHY init done
  82. [DEBUG] Tri-state TDO and TMS
  83. [DEBUG] Initializing sideband SCC registers.
  84. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 2 / 0 ms
  85. [INFO ] Enumerating buses...
  86. [DEBUG] Root Device scanning...
  87. [DEBUG] CPU_CLUSTER: 0 enabled
  88. [DEBUG] DOMAIN: 0000 enabled
  89. [DEBUG] DOMAIN: 0000 scanning...
  90. [DEBUG] PCI: pci_scan_bus for bus 00
  91. [DEBUG] PCI: 00:00.0 [8086/0f00] enabled
  92. [DEBUG] PCI: 00:02.0 [8086/0f31] enabled
  93. [DEBUG] PCI: 00:10.0: Disabling device: 10.0
  94. [DEBUG] Power management CAP offset 0x80.
  95. [DEBUG] PCI: 00:11.0: Disabling device: 11.0
  96. [DEBUG] Power management CAP offset 0x80.
  97. [DEBUG] PCI: 00:12.0 [8086/0f16] enabled
  98. [INFO ] PCI: Static device PCI: 00:13.0 not found, disabling it.
  99. [DEBUG] PCI: 00:14.0 [8086/0f35] enabled
  100. [DEBUG] PCI: 00:15.0 [8086/0f28] enabled
  101. [DEBUG] PCI: 00:17.0 [8086/0f50] enabled
  102. [DEBUG] PCI: 00:18.0 [8086/0f40] enabled
  103. [DEBUG] PCI: 00:18.1 [8086/0f41] enabled
  104. [DEBUG] PCI: 00:18.2 [8086/0f42] enabled
  105. [DEBUG] PCI: 00:18.3: Disabling device: 18.3
  106. [DEBUG] Power management CAP offset 0x80.
  107. [DEBUG] PCI: 00:18.4: Disabling device: 18.4
  108. [DEBUG] Power management CAP offset 0x80.
  109. [DEBUG] PCI: 00:18.5: Disabling device: 18.5
  110. [DEBUG] Power management CAP offset 0x80.
  111. [DEBUG] PCI: 00:18.5 [8086/0f45] disabled
  112. [DEBUG] PCI: 00:18.6: Disabling device: 18.6
  113. [DEBUG] Power management CAP offset 0x80.
  114. [DEBUG] PCI: 00:18.6 [8086/0f46] disabled
  115. [DEBUG] PCI: 00:18.7: Disabling device: 18.7
  116. [DEBUG] Power management CAP offset 0x80.
  117. [DEBUG] PCI: 00:1a.0: Disabling device: 1a.0
  118. [DEBUG] PCI: 00:1b.0 [8086/0f04] enabled
  119. [DEBUG] PCI: 00:1c.0 [8086/0f48] enabled
  120. [DEBUG] No PCIe device present.
  121. [WARN ] reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
  122. [DEBUG] PCI: 00:1c.1: Disabling device: 1c.1
  123. [DEBUG] Power management CAP offset 0xa0.
  124. [DEBUG] PCI: 00:1c.1 [8086/0f4a] disabled
  125. [DEBUG] PCI: 00:1c.2: Disabling device: 1c.2
  126. [DEBUG] Power management CAP offset 0xa0.
  127. [DEBUG] PCI: 00:1c.3: Disabling device: 1c.3
  128. [DEBUG] Power management CAP offset 0xa0.
  129. [DEBUG] PCI: 00:1d.0 [8086/0f34] enabled
  130. [DEBUG] PCI: 00:1e.0 [8086/0f06] enabled
  131. [DEBUG] PCI: 00:1e.1: Disabling device: 1e.1
  132. [DEBUG] Power management CAP offset 0x80.
  133. [DEBUG] PCI: 00:1e.2: Disabling device: 1e.2
  134. [DEBUG] Power management CAP offset 0x80.
  135. [DEBUG] PCI: 00:1e.3: Disabling device: 1e.3
  136. [DEBUG] Power management CAP offset 0x80.
  137. [DEBUG] PCI: 00:1e.4: Disabling device: 1e.4
  138. [DEBUG] Power management CAP offset 0x80.
  139. [DEBUG] PCI: 00:1e.4 [8086/0f0c] disabled
  140. [DEBUG] PCI: 00:1e.5: Disabling device: 1e.5
  141. [DEBUG] Power management CAP offset 0x80.
  142. [DEBUG] PCI: 00:1e.5 [8086/0f0e] disabled
  143. [DEBUG] PCI: 00:1f.0 [8086/0f1c] enabled
  144. [DEBUG] PCI: 00:1f.3: Disabling device: 1f.3
  145. [DEBUG] Power management CAP offset 0x50.
  146. [WARN ] PCI: Leftover static devices:
  147. [WARN ] PCI: 00:10.0
  148. [WARN ] PCI: 00:11.0
  149. [WARN ] PCI: 00:13.0
  150. [WARN ] PCI: 00:18.3
  151. [WARN ] PCI: 00:18.4
  152. [WARN ] PCI: 00:18.7
  153. [WARN ] PCI: 00:1a.0
  154. [WARN ] PCI: 00:1c.2
  155. [WARN ] PCI: 00:1c.3
  156. [WARN ] PCI: 00:1e.1
  157. [WARN ] PCI: 00:1e.2
  158. [WARN ] PCI: 00:1e.3
  159. [WARN ] PCI: 00:1f.3
  160. [WARN ] PCI: Check your devicetree.cb.
  161. [DEBUG] PCI: 00:1c.0 scanning...
  162. [DEBUG] PCI: pci_scan_bus for bus 01
  163. [DEBUG] PCI: 01:00.0 [8086/08b1] enabled
  164. [INFO ] Enabling Common Clock Configuration
  165. [INFO ] ASPM: Enabled L1
  166. [INFO ] PCIe: Max_Payload_Size adjusted to 128
  167. [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
  168. [DEBUG] PCI: 00:1f.0 scanning...
  169. [DEBUG] PNP: 0c31.0 enabled
  170. [DEBUG] PNP: 00ff.1 enabled
  171. [DEBUG] PNP: 00ff.0 enabled
  172. [DEBUG] PNP: 00ff.0 scanning...
  173. [DEBUG] scan_bus: bus PNP: 00ff.0 finished in 0 msecs
  174. [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
  175. [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 50 msecs
  176. [DEBUG] scan_bus: bus Root Device finished in 50 msecs
  177. [INFO ] done
  178. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 51 / 0 ms
  179. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  180. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  181. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  182. [INFO ] Manufacturer: ef
  183. [INFO ] SF: Detected ef 6017 with sector size 0x1000, total 0x800000
  184. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  185. [DEBUG] found VGA at PCI: 00:02.0
  186. [DEBUG] Setting up VGA for PCI: 00:02.0
  187. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  188. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  189. [INFO ] Allocating resources...
  190. [INFO ] Reading resources...
  191. [INFO ] Available memory above 4GB: 2048M
  192. [ERROR] PNP: 00ff.1 missing read_resources
  193. [INFO ] Done reading resources.
  194. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  195. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  196. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  197. [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  198. [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  199. [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  200. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  201. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  202. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  203. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  204. [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  205. [DEBUG] update_constraints: PNP: 00ff.0 00 base 00000800 limit 000009fe io (fixed)
  206. [INFO ] DOMAIN: 0000: Resource ranges:
  207. [INFO ] * Base: 1000, Size: f000, Tag: 100
  208. [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x1007] limit: 1007 io
  209. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  210. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
  211. [DEBUG] update_constraints: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
  212. [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
  213. [DEBUG] update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7affffff mem (fixed)
  214. [DEBUG] update_constraints: PCI: 00:00.0 02 base 7b000000 limit 7b7fffff mem (fixed)
  215. [DEBUG] update_constraints: PCI: 00:00.0 03 base 7b800000 limit 7fffffff mem (fixed)
  216. [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 17fffffff mem (fixed)
  217. [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
  218. [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
  219. [DEBUG] update_constraints: PCI: 00:15.0 a8 base 20000000 limit 200fffff mem (fixed)
  220. [DEBUG] update_constraints: PCI: 00:1f.0 feb base feb00000 limit febfffff mem (fixed)
  221. [DEBUG] update_constraints: PCI: 00:1f.0 44 base fed03000 limit fed033ff mem (fixed)
  222. [DEBUG] update_constraints: PCI: 00:1f.0 4c base fed0c000 limit fed0ffff mem (fixed)
  223. [DEBUG] update_constraints: PCI: 00:1f.0 50 base fed08000 limit fed083ff mem (fixed)
  224. [DEBUG] update_constraints: PCI: 00:1f.0 54 base fed01000 limit fed013ff mem (fixed)
  225. [DEBUG] update_constraints: PCI: 00:1f.0 58 base fef00000 limit feffffff mem (fixed)
  226. [DEBUG] update_constraints: PCI: 00:1f.0 5c base fed05000 limit fed057ff mem (fixed)
  227. [DEBUG] update_constraints: PCI: 00:1f.0 f0 base fed1c000 limit fed1c3ff mem (fixed)
  228. [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
  229. [INFO ] DOMAIN: 0000: Resource ranges:
  230. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  231. [INFO ] * Base: f0000000, Size: eb00000, Tag: 200
  232. [INFO ] * Base: fec00000, Size: 101000, Tag: 200
  233. [INFO ] * Base: fed02000, Size: 1000, Tag: 200
  234. [INFO ] * Base: fed04000, Size: 1000, Tag: 200
  235. [INFO ] * Base: fed06000, Size: 2000, Tag: 200
  236. [INFO ] * Base: fed09000, Size: 3000, Tag: 200
  237. [INFO ] * Base: fed10000, Size: c000, Tag: 200
  238. [INFO ] * Base: fed1d000, Size: 23000, Tag: 200
  239. [INFO ] * Base: fed45000, Size: 1bb000, Tag: 200
  240. [INFO ] * Base: ff000000, Size: 1000000, Tag: 200
  241. [INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
  242. [DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  243. [DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
  244. [DEBUG] PCI: 00:15.0 10 * [0x90400000 - 0x905fffff] limit: 905fffff mem
  245. [DEBUG] PCI: 00:1c.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
  246. [DEBUG] PCI: 00:14.0 10 * [0x90700000 - 0x9070ffff] limit: 9070ffff mem
  247. [DEBUG] PCI: 00:18.0 10 * [0x90710000 - 0x90713fff] limit: 90713fff mem
  248. [DEBUG] PCI: 00:1b.0 10 * [0x90714000 - 0x90717fff] limit: 90717fff mem
  249. [DEBUG] PCI: 00:1e.0 10 * [0x90718000 - 0x9071bfff] limit: 9071bfff mem
  250. [DEBUG] PCI: 00:12.0 10 * [0x9071c000 - 0x9071cfff] limit: 9071cfff mem
  251. [DEBUG] PCI: 00:12.0 14 * [0x9071d000 - 0x9071dfff] limit: 9071dfff mem
  252. [DEBUG] PCI: 00:15.0 14 * [0x9071e000 - 0x9071efff] limit: 9071efff mem
  253. [DEBUG] PCI: 00:17.0 10 * [0x9071f000 - 0x9071ffff] limit: 9071ffff mem
  254. [DEBUG] PCI: 00:17.0 14 * [0x90720000 - 0x90720fff] limit: 90720fff mem
  255. [DEBUG] PCI: 00:18.0 14 * [0x90721000 - 0x90721fff] limit: 90721fff mem
  256. [DEBUG] PCI: 00:18.1 10 * [0x90722000 - 0x90722fff] limit: 90722fff mem
  257. [DEBUG] PCI: 00:18.1 14 * [0x90723000 - 0x90723fff] limit: 90723fff mem
  258. [DEBUG] PCI: 00:18.2 10 * [0x90724000 - 0x90724fff] limit: 90724fff mem
  259. [DEBUG] PCI: 00:18.2 14 * [0x90725000 - 0x90725fff] limit: 90725fff mem
  260. [DEBUG] PCI: 00:1e.0 14 * [0x90726000 - 0x90726fff] limit: 90726fff mem
  261. [DEBUG] PCI: 00:1d.0 10 * [0x90727000 - 0x907273ff] limit: 907273ff mem
  262. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
  263. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
  264. [INFO ] PCI: 00:1c.0: Resource ranges:
  265. [INFO ] * Base: 90600000, Size: 100000, Tag: 200
  266. [DEBUG] PCI: 01:00.0 10 * [0x90600000 - 0x90601fff] limit: 90601fff mem
  267. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
  268. [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  269. [ERROR] PCI: 00:00.0 missing set_resources
  270. [DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem
  271. [DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem
  272. [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x0000000000001007] size 0x00000008 gran 0x03 io
  273. [DEBUG] PCI: 00:12.0 10 <- [0x000000009071c000 - 0x000000009071cfff] size 0x00001000 gran 0x0c mem
  274. [DEBUG] PCI: 00:12.0 14 <- [0x000000009071d000 - 0x000000009071dfff] size 0x00001000 gran 0x0c mem
  275. [DEBUG] PCI: 00:14.0 10 <- [0x0000000090700000 - 0x000000009070ffff] size 0x00010000 gran 0x10 mem64
  276. [DEBUG] PCI: 00:15.0 10 <- [0x0000000090400000 - 0x00000000905fffff] size 0x00200000 gran 0x15 mem
  277. [DEBUG] PCI: 00:15.0 14 <- [0x000000009071e000 - 0x000000009071efff] size 0x00001000 gran 0x0c mem
  278. [DEBUG] PCI: 00:17.0 10 <- [0x000000009071f000 - 0x000000009071ffff] size 0x00001000 gran 0x0c mem
  279. [DEBUG] PCI: 00:17.0 14 <- [0x0000000090720000 - 0x0000000090720fff] size 0x00001000 gran 0x0c mem
  280. [DEBUG] PCI: 00:18.0 10 <- [0x0000000090710000 - 0x0000000090713fff] size 0x00004000 gran 0x0e mem
  281. [DEBUG] PCI: 00:18.0 14 <- [0x0000000090721000 - 0x0000000090721fff] size 0x00001000 gran 0x0c mem
  282. [DEBUG] PCI: 00:18.1 10 <- [0x0000000090722000 - 0x0000000090722fff] size 0x00001000 gran 0x0c mem
  283. [DEBUG] PCI: 00:18.1 14 <- [0x0000000090723000 - 0x0000000090723fff] size 0x00001000 gran 0x0c mem
  284. [DEBUG] PCI: 00:18.2 10 <- [0x0000000090724000 - 0x0000000090724fff] size 0x00001000 gran 0x0c mem
  285. [DEBUG] PCI: 00:18.2 14 <- [0x0000000090725000 - 0x0000000090725fff] size 0x00001000 gran 0x0c mem
  286. [DEBUG] PCI: 00:1b.0 10 <- [0x0000000090714000 - 0x0000000090717fff] size 0x00004000 gran 0x0e mem64
  287. [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
  288. [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  289. [DEBUG] PCI: 00:1c.0 20 <- [0x0000000090600000 - 0x00000000906fffff] size 0x00100000 gran 0x14 bus 01 mem
  290. [DEBUG] PCI: 01:00.0 10 <- [0x0000000090600000 - 0x0000000090601fff] size 0x00002000 gran 0x0d mem64
  291. [DEBUG] PCI: 00:1d.0 10 <- [0x0000000090727000 - 0x00000000907273ff] size 0x00000400 gran 0x0a mem
  292. [DEBUG] PCI: 00:1e.0 10 <- [0x0000000090718000 - 0x000000009071bfff] size 0x00004000 gran 0x0e mem
  293. [DEBUG] PCI: 00:1e.0 14 <- [0x0000000090726000 - 0x0000000090726fff] size 0x00001000 gran 0x0c mem
  294. [INFO ] Done setting resources.
  295. [INFO ] Done allocating resources.
  296. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
  297. [INFO ] Enabling resources...
  298. [DEBUG] PCI: 00:02.0 subsystem <- 8086/0f31
  299. [DEBUG] PCI: 00:02.0 cmd <- 03
  300. [DEBUG] PCI: 00:12.0 subsystem <- 8086/0f16
  301. [DEBUG] PCI: 00:12.0 cmd <- 106
  302. [DEBUG] PCI: 00:14.0 subsystem <- 8086/0f35
  303. [DEBUG] PCI: 00:14.0 cmd <- 102
  304. [DEBUG] PCI: 00:15.0 subsystem <- 8086/0f28
  305. [DEBUG] PCI: 00:15.0 cmd <- 102
  306. [DEBUG] PCI: 00:17.0 subsystem <- 8086/0f50
  307. [DEBUG] PCI: 00:17.0 cmd <- 106
  308. [DEBUG] PCI: 00:18.0 subsystem <- 8086/0f40
  309. [DEBUG] PCI: 00:18.0 cmd <- 106
  310. [DEBUG] PCI: 00:18.1 subsystem <- 8086/0f41
  311. [DEBUG] PCI: 00:18.1 cmd <- 102
  312. [DEBUG] PCI: 00:18.2 subsystem <- 8086/0f42
  313. [DEBUG] PCI: 00:18.2 cmd <- 102
  314. [DEBUG] PCI: 00:1b.0 subsystem <- 8086/0f04
  315. [DEBUG] PCI: 00:1b.0 cmd <- 102
  316. [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
  317. [DEBUG] PCI: 00:1c.0 subsystem <- 8086/0f48
  318. [DEBUG] PCI: 00:1c.0 cmd <- 106
  319. [DEBUG] PCI: 00:1d.0 subsystem <- 8086/0f34
  320. [DEBUG] PCI: 00:1d.0 cmd <- 102
  321. [DEBUG] PCI: 00:1e.0 subsystem <- 8086/0f06
  322. [DEBUG] PCI: 00:1e.0 cmd <- 106
  323. [DEBUG] PCI: 01:00.0 cmd <- 02
  324. [INFO ] done.
  325. [DEBUG] Applying SOC Thermal settings for DPTF.
  326. [INFO ] Initializing devices...
  327. [DEBUG] Root Device init
  328. [DEBUG] mainboard_ec_init
  329. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000001
  330. [DEBUG] Chrome EC: UHEPI not supported
  331. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  332. [DEBUG] Root Device init finished in 1 msecs
  333. [DEBUG] CPU_CLUSTER: 0 init
  334. [DEBUG] MTRR: Physical address space:
  335. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  336. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  337. [DEBUG] 0x00000000000c0000 - 0x000000007b7fffff size 0x7b740000 type 6
  338. [DEBUG] 0x000000007b800000 - 0x000000007fffffff size 0x04800000 type 0
  339. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  340. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  341. [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
  342. [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
  343. [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
  344. [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
  345. [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
  346. [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
  347. [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
  348. [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
  349. [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
  350. [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
  351. [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
  352. [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
  353. [DEBUG] CPU physical address size: 36 bits
  354. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
  355. [DEBUG] MTRR: UC selected as default type.
  356. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
  357. [DEBUG] MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
  358. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
  359. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
  360. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
  361.  
  362. [DEBUG] MTRR check
  363. [DEBUG] Fixed MTRRs : Enabled
  364. [DEBUG] Variable MTRRs: Enabled
  365.  
  366. [INFO ] Turbo is available but hidden
  367. [INFO ] Turbo is available and visible
  368. [DEBUG] Setting up SMI for CPU
  369. [INFO ] Will perform SMM setup.
  370. [INFO ] CPU: Intel(R) Celeron(R) CPU N2840 @ 2.16GHz.
  371. [INFO ] LAPIC 0x0 in XAPIC mode.
  372. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  373. [DEBUG] Processing 18 relocs. Offset value of 0x00030000
  374. [DEBUG] Attempting to start 1 APs
  375. [DEBUG] Waiting for 10ms after sending INIT.
  376. [DEBUG] Waiting for SIPI to complete...
  377. [DEBUG] done.
  378. [DEBUG] Waiting for SIPI to complete...
  379. [DEBUG] done.
  380. [INFO ] LAPIC 0x2 in XAPIC mode.
  381. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000838
  382. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
  383. [DEBUG] Processing 11 relocs. Offset value of 0x00038000
  384. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  385. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  386. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  387. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  388. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7af91cd6
  389. [DEBUG] Installing permanent SMM handler to 0x7b000000
  390. [DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
  391. [DEBUG] HANDLER [0x7b6fb000-0x7b6ff048]
  392.  
  393. [DEBUG] CPU 0
  394. [DEBUG] ss0 [0x7b6fac00-0x7b6fb000]
  395. [DEBUG] stub0 [0x7b6f3000-0x7b6f31e0]
  396.  
  397. [DEBUG] CPU 1
  398. [DEBUG] ss1 [0x7b6fa800-0x7b6fac00]
  399. [DEBUG] stub1 [0x7b6f2c00-0x7b6f2de0]
  400.  
  401. [DEBUG] stacks [0x7b000000-0x7b001000]
  402. [DEBUG] Loading module at 0x7b6fb000 with entry 0x7b6fbaff. filesize: 0x3f38 memsize: 0x4048
  403. [DEBUG] Processing 236 relocs. Offset value of 0x7b6fb000
  404. [DEBUG] Loading module at 0x7b6f3000 with entry 0x7b6f3000. filesize: 0x1e0 memsize: 0x1e0
  405. [DEBUG] Processing 11 relocs. Offset value of 0x7b6f3000
  406. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  407. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  408. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  409. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
  410. [DEBUG] SMM Module: placing smm entry code at 7b6f2c00, cpu # 0x1
  411. [DEBUG] SMM Module: stub loaded at 7b6f3000. Will call 0x7b6fbaff
  412. [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1
  413. [DEBUG] WAK USB PWRBTN GPE0a_STS: CORE_GPIO_0 SUS_GPIO_1
  414. [DEBUG] ALT_GPIO_SMI: CORE_GPIO_0 SUS_GPIO_1
  415. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eb000, cpu = 0
  416. [DEBUG] Relocation complete.
  417. [INFO ] microcode: Update skipped, already up-to-date
  418. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eac00, cpu = 1
  419. [DEBUG] Relocation complete.
  420. [INFO ] microcode: Update skipped, already up-to-date
  421. [INFO ] Initializing CPU #0
  422. [DEBUG] CPU: vendor Intel device 30678
  423. [DEBUG] CPU: family 06, model 37, stepping 08
  424. [DEBUG] Init BayTrail core.
  425. [DEBUG] VMX status: enabled
  426. [DEBUG] IA32_FEATURE_CONTROL status: locked
  427. [INFO ] CPU #0 initialized
  428. [INFO ] Initializing CPU #1
  429. [DEBUG] CPU: vendor Intel device 30678
  430. [DEBUG] CPU: family 06, model 37, stepping 08
  431. [DEBUG] Init BayTrail core.
  432. [INFO ] Turbo is available and visible
  433. [DEBUG] VMX status: enabled
  434. [DEBUG] IA32_FEATURE_CONTROL status: locked
  435. [INFO ] CPU #1 initialized
  436. [INFO ] bsp_do_flight_plan done after 0 msecs.
  437. [DEBUG] Enabling SMIs.
  438. [DEBUG] GPIO_ROUT = 00024000
  439. [DEBUG] ALT_GPIO_SMI = 00000080
  440. [DEBUG] CPU_CLUSTER: 0 init finished in 10 msecs
  441. [DEBUG] PCI: 00:02.0 init
  442. [INFO ] CBFS: Found 'vbt.bin' @0x50d40 size 0x48e in mcache @0x7afdd228
  443. [INFO ] Found a VBT of 4608 bytes after decompression
  444. [INFO ] GMA: Found VBT in CBFS
  445. [INFO ] GMA: Found valid VBT in CBFS
  446. [INFO ] GFX: Pre VBIOS Init
  447. [INFO ] GFX: Power Management Init
  448. [INFO ] GFX: Initialize PIPEA
  449. [INFO ] GFX: Post VBIOS Init
  450. [DEBUG] PCI: 00:02.0 init finished in 1 msecs
  451. [DEBUG] PCI: 00:12.0 init
  452. [DEBUG] Overriding SD Card controller caps.
  453. [DEBUG] PCI: 00:12.0 init finished in 0 msecs
  454. [DEBUG] PCI: 00:14.0 init
  455. [INFO ] USB: Route ports to XHCI controller
  456. [DEBUG] PCI: 00:14.0 init finished in 0 msecs
  457. [DEBUG] PCI: 00:15.0 init
  458. [DEBUG] LPE Audio codec clock set to 25MHz.
  459. [DEBUG] PCI: 00:15.0 init finished in 0 msecs
  460. [DEBUG] PCI: 00:17.0 init
  461. [DEBUG] eMMC init
  462. [DEBUG] PCI: 00:17.0 init finished in 0 msecs
  463. [DEBUG] PCI: 00:18.0 init
  464. [DEBUG] PCI: 00:18.0 init finished in 0 msecs
  465. [DEBUG] PCI: 00:18.1 init
  466. [DEBUG] Releasing I2C device from reset.
  467. [DEBUG] PCI: 00:18.1 init finished in 0 msecs
  468. [DEBUG] PCI: 00:18.2 init
  469. [DEBUG] Releasing I2C device from reset.
  470. [DEBUG] PCI: 00:18.2 init finished in 0 msecs
  471. [DEBUG] PCI: 00:1b.0 init
  472. [DEBUG] codec mask = 4
  473. [DEBUG] HDA: Initializing codec #2
  474. [DEBUG] HDA: codec viddid: 80862882
  475. [DEBUG] HDA: verb loaded.
  476. [DEBUG] PCI: 00:1b.0 init finished in 3 msecs
  477. [DEBUG] PCI: 00:1c.0 init
  478. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs
  479. [DEBUG] PCI: 00:1d.0 init
  480. [DEBUG] PCI: 00:1d.0: Disabling device: 1d.0
  481. [DEBUG] Power management CAP offset 0x70.
  482. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs
  483. [DEBUG] PCI: 00:1e.0 init
  484. [DEBUG] PCI: 00:1e.0 init finished in 0 msecs
  485. [DEBUG] PCI: 00:1f.0 init
  486. [DEBUG] RTC Init
  487. [DEBUG] Disabling slp_x stretching.
  488. [DEBUG] PCI: 00:1f.0 init finished in 0 msecs
  489. [DEBUG] PCI: 01:00.0 init
  490. [DEBUG] PCI: 01:00.0 init finished in 0 msecs
  491. [DEBUG] PNP: 00ff.0 init
  492. [DEBUG] Google Chrome EC: Initializing
  493. [DEBUG] Google Chrome EC: version:
  494. [DEBUG] ro: swanky_v1.6.197-c5a86fe
  495. [DEBUG] rw: swanky_v1.6.205-92b7845
  496. [DEBUG] running image: 2
  497. [INFO ] CBFS: Found 'ecrw.hash' @0x50cc0 size 0x20 in mcache @0x7afdd204
  498. [DEBUG] ChromeEC SW Sync: Expected hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  499. [DEBUG] ChromeEC: Getting hash:
  500. [DEBUG] ChromeEC SW Sync: current EC_RW hash: 4439807613e3c0d01e43ed9468f5d96bd644cab9ac0b9e3eb38549b1d2373f3d
  501. [DEBUG] ChromeEC SW Sync: EC_RW is up to date
  502. [DEBUG] PNP: 00ff.0 init finished in 3 msecs
  503. [INFO ] Devices initialized
  504. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 21 / 0 ms
  505. [DEBUG] FMAP: area SMMSTORE found @ 5c0000 (262144 bytes)
  506. [DEBUG] smm store: 4 # blocks with size 0x10000
  507. [INFO ] SMMSTORE: Setting up SMI handler
  508. [INFO ] Found TPM SLB9635 TT 1.2 by Infineon
  509. [DEBUG] TPM: Startup
  510. [DEBUG] TPM: command 0x99 returned 0x0
  511. [DEBUG] TPM: Asserting physical presence
  512. [DEBUG] TPM: command 0x4000000a returned 0x0
  513. [DEBUG] TPM: command 0x65 returned 0x0
  514. [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1
  515. [INFO ] TPM: setup succeeded
  516. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 8 / 0 ms
  517. [INFO ] Finalize devices...
  518. [INFO ] Devices finalized
  519. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x3a040 size 0x3eca in mcache @0x7afdd1b8
  520. [WARN ] CBFS: 'fallback/slic' not found.
  521. [INFO ] ACPI: Writing ACPI tables at 7af2a000.
  522. [DEBUG] ACPI: * FACS
  523. [DEBUG] ACPI: * DSDT
  524. [DEBUG] ACPI: * FADT
  525. [DEBUG] SCI is IRQ9
  526. [DEBUG] ACPI: added table 1/32, length now 40
  527. [DEBUG] ACPI: * SSDT
  528. [INFO ] Turbo is available and visible
  529. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4b status 0x1f4b
  530. [DEBUG] PSS: 2166MHz power 7000 control 0x1a41 status 0x1a41
  531. [DEBUG] PSS: 1999MHz power 6312 control 0x1840 status 0x1840
  532. [DEBUG] PSS: 1833MHz power 5649 control 0x163c status 0x163c
  533. [DEBUG] PSS: 1666MHz power 5016 control 0x1439 status 0x1439
  534. [DEBUG] PSS: 1499MHz power 4412 control 0x1236 status 0x1236
  535. [DEBUG] PSS: 1333MHz power 3827 control 0x1032 status 0x1032
  536. [DEBUG] PSS: 1166MHz power 3268 control 0xe2f status 0xe2f
  537. [DEBUG] PSS: 999MHz power 2733 control 0xc2c status 0xc2c
  538. [DEBUG] PSS: 833MHz power 2220 control 0xa28 status 0xa28
  539. [DEBUG] PSS: 666MHz power 1729 control 0x825 status 0x825
  540. [DEBUG] PSS: 499MHz power 1263 control 0x621 status 0x621
  541. [INFO ] Turbo is available and visible
  542. [DEBUG] PSS: 2167MHz power 7000 control 0x1f4b status 0x1f4b
  543. [DEBUG] PSS: 2166MHz power 7000 control 0x1a41 status 0x1a41
  544. [DEBUG] PSS: 1999MHz power 6312 control 0x1840 status 0x1840
  545. [DEBUG] PSS: 1833MHz power 5649 control 0x163c status 0x163c
  546. [DEBUG] PSS: 1666MHz power 5016 control 0x1439 status 0x1439
  547. [DEBUG] PSS: 1499MHz power 4412 control 0x1236 status 0x1236
  548. [DEBUG] PSS: 1333MHz power 3827 control 0x1032 status 0x1032
  549. [DEBUG] PSS: 1166MHz power 3268 control 0xe2f status 0xe2f
  550. [DEBUG] PSS: 999MHz power 2733 control 0xc2c status 0xc2c
  551. [DEBUG] PSS: 833MHz power 2220 control 0xa28 status 0xa28
  552. [DEBUG] PSS: 666MHz power 1729 control 0x825 status 0x825
  553. [DEBUG] PSS: 499MHz power 1263 control 0x621 status 0x621
  554. [DEBUG] PPI: Pending OS request: 0x8f51dff0 (0x5f16d77e)
  555. [DEBUG] PPI: OS response: CMD 0x3f48bfc2 = 0x9fb9fe20
  556. [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
  557. [ERROR] PS2K: Bad resp from EC. Vivaldi disabled!
  558. [DEBUG] ACPI: added table 2/32, length now 44
  559. [DEBUG] ACPI: * MCFG
  560. [DEBUG] ACPI: added table 3/32, length now 48
  561. [DEBUG] ACPI: * TCPA
  562. [DEBUG] TCPA log created at 0x7af1a000
  563. [DEBUG] ACPI: added table 4/32, length now 52
  564. [DEBUG] ACPI: * MADT
  565. [DEBUG] ACPI: added table 5/32, length now 56
  566. [DEBUG] current = 7af2f2f0
  567. [DEBUG] ACPI: * HPET
  568. [DEBUG] ACPI: added table 6/32, length now 60
  569. [INFO ] ACPI: done.
  570. [DEBUG] ACPI tables: 21296 bytes.
  571. [DEBUG] smbios_write_tables: 7af12000
  572. [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-4.18.1'
  573. [INFO ] Create SMBIOS type 16
  574. [INFO ] Create SMBIOS type 17
  575. [INFO ] Create SMBIOS type 20
  576. [INFO ] Root Device (Google Swanky)
  577. [INFO ] PCI: 01:00.0 (unknown)
  578. [DEBUG] SMBIOS tables: 966 bytes.
  579. [DEBUG] Writing table forward entry at 0x00000500
  580. [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum a4e9
  581. [DEBUG] Writing coreboot table at 0x7af4e000
  582. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  583. [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
  584. [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
  585. [DEBUG] 3. 0000000000100000-000000001fffffff: RAM
  586. [DEBUG] 4. 0000000020000000-00000000200fffff: RESERVED
  587. [DEBUG] 5. 0000000020100000-000000007af11fff: RAM
  588. [DEBUG] 6. 000000007af12000-000000007af79fff: CONFIGURATION TABLES
  589. [DEBUG] 7. 000000007af7a000-000000007afcbfff: RAMSTAGE
  590. [DEBUG] 8. 000000007afcc000-000000007affffff: CONFIGURATION TABLES
  591. [DEBUG] 9. 000000007b000000-000000007fffffff: RESERVED
  592. [DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
  593. [DEBUG] 11. 00000000feb00000-00000000febfffff: RESERVED
  594. [DEBUG] 12. 00000000fed01000-00000000fed01fff: RESERVED
  595. [DEBUG] 13. 00000000fed03000-00000000fed03fff: RESERVED
  596. [DEBUG] 14. 00000000fed05000-00000000fed05fff: RESERVED
  597. [DEBUG] 15. 00000000fed08000-00000000fed08fff: RESERVED
  598. [DEBUG] 16. 00000000fed0c000-00000000fed0ffff: RESERVED
  599. [DEBUG] 17. 00000000fed1c000-00000000fed1cfff: RESERVED
  600. [DEBUG] 18. 00000000fed40000-00000000fed44fff: RESERVED
  601. [DEBUG] 19. 00000000fef00000-00000000feffffff: RESERVED
  602. [DEBUG] 20. 0000000100000000-000000017fffffff: RAM
  603. [DEBUG] Wrote coreboot table at: 0x7af4e000, 0x52c bytes, checksum 2b51
  604. [DEBUG] coreboot table: 1348 bytes.
  605. [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
  606. [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
  607. [DEBUG] CONSOLE 2. 0x7afde000 0x00020000
  608. [DEBUG] RO MCACHE 3. 0x7afdd000 0x00000374
  609. [DEBUG] TIME STAMP 4. 0x7afdc000 0x00000910
  610. [DEBUG] MEM INFO 5. 0x7afdb000 0x00000768
  611. [DEBUG] MRC DATA 6. 0x7afd9000 0x0000166b
  612. [DEBUG] AFTER CAR 7. 0x7afcc000 0x0000d000
  613. [DEBUG] RAMSTAGE 8. 0x7af79000 0x00053000
  614. [DEBUG] SMM BACKUP 9. 0x7af69000 0x00010000
  615. [DEBUG] IGD OPREGION10. 0x7af66000 0x00002e13
  616. [DEBUG] SMM COMBUFFER11. 0x7af56000 0x00010000
  617. [DEBUG] COREBOOT 12. 0x7af4e000 0x00008000
  618. [DEBUG] ACPI 13. 0x7af2a000 0x00024000
  619. [DEBUG] TCPA TCGLOG14. 0x7af1a000 0x00010000
  620. [DEBUG] SMBIOS 15. 0x7af12000 0x00008000
  621. [DEBUG] IMD small region:
  622. [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
  623. [DEBUG] VPD 1. 0x7affeb40 0x000000bf
  624. [DEBUG] FMAP 2. 0x7affea00 0x00000134
  625. [DEBUG] POWER STATE 3. 0x7affe9e0 0x00000020
  626. [DEBUG] ROMSTAGE 4. 0x7affe9c0 0x00000004
  627. [DEBUG] ROMSTG STCK 5. 0x7affe920 0x00000088
  628. [DEBUG] ACPI GNVS 6. 0x7affe820 0x000000e8
  629. [DEBUG] TPM PPI 7. 0x7affe6c0 0x0000015a
  630. [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 4 / 0 ms
  631. [INFO ] CBFS: Found 'fallback/payload' @0x56c40 size 0xc7760 in mcache @0x7afdd2c4
  632. [DEBUG] Checking segment from ROM address 0xffe5ae6c
  633. [DEBUG] Checking segment from ROM address 0xffe5ae88
  634. [DEBUG] Loading segment from ROM address 0xffe5ae6c
  635. [DEBUG] code (compression=1)
  636. [DEBUG] New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xffe5aea4 filesize 0xc7728
  637. [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000c7728
  638. [DEBUG] using LZMA
  639. [DEBUG] Loading segment from ROM address 0xffe5ae88
  640. [DEBUG] Entry Point 0x00801626
  641. [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 260 / 0 ms
  642. [DEBUG] Applying perf/power settings.
  643. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
  644. [DEBUG] Jumping to boot code at 0x00801626(0x7af4e000)
  645.  
  646.  
  647. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 bootblock starting (log level: 7)...
  648. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x604000.
  649. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 6
  650. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  651. [INFO ] CBFS: mcache @0xfe002e00 built for 17 files, used 0x374 of 0x4000 bytes
  652. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x65d0 in mcache @0xfe002e2c
  653. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  654.  
  655.  
  656. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 romstage starting (log level: 7)...
  657. [DEBUG] Enabling VR PS2 mode: VNN VCC
  658. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  659. [INFO ] CBFS: Found 'spd.bin' @0x39c00 size 0x400 in mcache @0xfe002f98
  660. [DEBUG] ram_id=2, total_spds: 4
  661. [DEBUG] pm1_sts: a000 pm1_en: 0100 pm1_cnt: 00001400
  662. [DEBUG] gpe0_sts: 01010000 gpe0_en: 00032000 tco_sts: 00000000
  663. [DEBUG] prsts: 04450900 gen_pmcon1: 00201038 gen_pmcon2: 00000000
  664. [DEBUG] prev_sleep_state = S3
  665. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  666. [INFO ] CBFS: Found 'mrc.bin' @0x19adc0 size 0x11218 in mcache @0xfe0030f0
  667. BayTrail-MD MRC wrapper v5
  668. Training for Memory Down designs.
  669. Applying weaker ODT settings. DRAM ODT is 120.
  670. [INFO ] MRC v0.97
  671. [INFO ] 2 channels of DDR3 @ 1333MHz
  672. [DEBUG] MRC Wrapper returned 0
  673. [DEBUG] MRC data at 0xfe00965f 5719 bytes
  674. [DEBUG] SMM Memory Map
  675. [DEBUG] SMRAM : 0x7b000000 0x800000
  676. [DEBUG] Subregion 0: 0x7b000000 0x700000
  677. [DEBUG] Subregion 1: 0x7b700000 0x100000
  678. [DEBUG] Subregion 2: 0x7b800000 0x0
  679. [DEBUG] S3 Resume
  680. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  681.  
  682.  
  683. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 postcar starting (log level: 7)...
  684. [DEBUG] S3 Resume
  685. [DEBUG] Jumping to image.
  686.  
  687.  
  688. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 ramstage starting (log level: 7)...
  689. [DEBUG] S3 Resume
  690. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  691. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6700 size 0x19800 in mcache @0x7afdd0ac
  692. [DEBUG] microcode: sig=0x30678 pf=0x8 revision=0x838
  693. [DEBUG] BYT: cpuid 00030678 cpus 2 rid 0e step C0
  694. [DEBUG] msr(17) = 000c000090341f4b
  695. [DEBUG] msr(ce) = 0000060000001a00
  696. [DEBUG] ModPHY init entry
  697. [DEBUG] SOC B0 and later ModPhy Table programming
  698. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  699. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  700. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  701. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  702. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  703. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  704. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  705. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  706. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  707. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  708. [DEBUG] ModPHY init done
  709. [DEBUG] Tri-state TDO and TMS
  710. [DEBUG] Initializing sideband SCC registers.
  711. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 2 / 0 ms
  712. [INFO ] Enumerating buses...
  713. [DEBUG] Root Device scanning...
  714. [DEBUG] CPU_CLUSTER: 0 enabled
  715. [DEBUG] DOMAIN: 0000 enabled
  716. [DEBUG] DOMAIN: 0000 scanning...
  717. [DEBUG] PCI: pci_scan_bus for bus 00
  718. [DEBUG] PCI: 00:00.0 [8086/0f00] enabled
  719. [DEBUG] PCI: 00:02.0 [8086/0f31] enabled
  720. [DEBUG] PCI: 00:10.0: Disabling device: 10.0
  721. [DEBUG] Power management CAP offset 0x80.
  722. [DEBUG] PCI: 00:11.0: Disabling device: 11.0
  723. [DEBUG] Power management CAP offset 0x80.
  724. [DEBUG] PCI: 00:12.0 [8086/0f16] enabled
  725. [INFO ] PCI: Static device PCI: 00:13.0 not found, disabling it.
  726. [DEBUG] PCI: 00:14.0 [8086/0f35] enabled
  727. [DEBUG] PCI: 00:15.0 [8086/0f28] enabled
  728. [DEBUG] PCI: 00:17.0 [8086/0f50] enabled
  729. [DEBUG] PCI: 00:18.0 [8086/0f40] enabled
  730. [DEBUG] PCI: 00:18.1 [8086/0f41] enabled
  731. [DEBUG] PCI: 00:18.2 [8086/0f42] enabled
  732. [DEBUG] PCI: 00:18.3: Disabling device: 18.3
  733. [DEBUG] Power management CAP offset 0x80.
  734. [DEBUG] PCI: 00:18.4: Disabling device: 18.4
  735. [DEBUG] Power management CAP offset 0x80.
  736. [DEBUG] PCI: 00:18.5: Disabling device: 18.5
  737. [DEBUG] Power management CAP offset 0x80.
  738. [DEBUG] PCI: 00:18.5 [8086/0f45] disabled
  739. [DEBUG] PCI: 00:18.6: Disabling device: 18.6
  740. [DEBUG] Power management CAP offset 0x80.
  741. [DEBUG] PCI: 00:18.6 [8086/0f46] disabled
  742. [DEBUG] PCI: 00:18.7: Disabling device: 18.7
  743. [DEBUG] Power management CAP offset 0x80.
  744. [DEBUG] PCI: 00:1a.0: Disabling device: 1a.0
  745. [DEBUG] PCI: 00:1b.0 [8086/0f04] enabled
  746. [DEBUG] PCI: 00:1c.0 [8086/0f48] enabled
  747. [DEBUG] No PCIe device present.
  748. [WARN ] reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
  749. [DEBUG] PCI: 00:1c.1: Disabling device: 1c.1
  750. [DEBUG] Power management CAP offset 0xa0.
  751. [DEBUG] PCI: 00:1c.1 [8086/0f4a] disabled
  752. [DEBUG] PCI: 00:1c.2: Disabling device: 1c.2
  753. [DEBUG] Power management CAP offset 0xa0.
  754. [DEBUG] PCI: 00:1c.3: Disabling device: 1c.3
  755. [DEBUG] Power management CAP offset 0xa0.
  756. [DEBUG] PCI: 00:1d.0 [8086/0f34] enabled
  757. [DEBUG] PCI: 00:1e.0 [8086/0f06] enabled
  758. [DEBUG] PCI: 00:1e.1: Disabling device: 1e.1
  759. [DEBUG] Power management CAP offset 0x80.
  760. [DEBUG] PCI: 00:1e.2: Disabling device: 1e.2
  761. [DEBUG] Power management CAP offset 0x80.
  762. [DEBUG] PCI: 00:1e.3: Disabling device: 1e.3
  763. [DEBUG] Power management CAP offset 0x80.
  764. [DEBUG] PCI: 00:1e.4: Disabling device: 1e.4
  765. [DEBUG] Power management CAP offset 0x80.
  766. [DEBUG] PCI: 00:1e.4 [8086/0f0c] disabled
  767. [DEBUG] PCI: 00:1e.5: Disabling device: 1e.5
  768. [DEBUG] Power management CAP offset 0x80.
  769. [DEBUG] PCI: 00:1e.5 [8086/0f0e] disabled
  770. [DEBUG] PCI: 00:1f.0 [8086/0f1c] enabled
  771. [DEBUG] PCI: 00:1f.3: Disabling device: 1f.3
  772. [DEBUG] Power management CAP offset 0x50.
  773. [WARN ] PCI: Leftover static devices:
  774. [WARN ] PCI: 00:10.0
  775. [WARN ] PCI: 00:11.0
  776. [WARN ] PCI: 00:13.0
  777. [WARN ] PCI: 00:18.3
  778. [WARN ] PCI: 00:18.4
  779. [WARN ] PCI: 00:18.7
  780. [WARN ] PCI: 00:1a.0
  781. [WARN ] PCI: 00:1c.2
  782. [WARN ] PCI: 00:1c.3
  783. [WARN ] PCI: 00:1e.1
  784. [WARN ] PCI: 00:1e.2
  785. [WARN ] PCI: 00:1e.3
  786. [WARN ] PCI: 00:1f.3
  787. [WARN ] PCI: Check your devicetree.cb.
  788. [DEBUG] PCI: 00:1c.0 scanning...
  789. [DEBUG] PCI: pci_scan_bus for bus 01
  790. [DEBUG] PCI: 01:00.0 [8086/08b1] enabled
  791. [INFO ] Enabling Common Clock Configuration
  792. [INFO ] ASPM: Enabled L1
  793. [INFO ] PCIe: Max_Payload_Size adjusted to 128
  794. [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
  795. [DEBUG] PCI: 00:1f.0 scanning...
  796. [DEBUG] PNP: 0c31.0 enabled
  797. [DEBUG] PNP: 00ff.1 enabled
  798. [DEBUG] PNP: 00ff.0 enabled
  799. [DEBUG] PNP: 00ff.0 scanning...
  800. [DEBUG] scan_bus: bus PNP: 00ff.0 finished in 0 msecs
  801. [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
  802. [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 50 msecs
  803. [DEBUG] scan_bus: bus Root Device finished in 50 msecs
  804. [INFO ] done
  805. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 51 / 0 ms
  806. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  807. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  808. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  809. [INFO ] Manufacturer: ef
  810. [INFO ] SF: Detected ef 6017 with sector size 0x1000, total 0x800000
  811. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  812. [DEBUG] found VGA at PCI: 00:02.0
  813. [DEBUG] Setting up VGA for PCI: 00:02.0
  814. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  815. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  816. [INFO ] Allocating resources...
  817. [INFO ] Reading resources...
  818. [INFO ] Available memory above 4GB: 2048M
  819. [ERROR] PNP: 00ff.1 missing read_resources
  820. [INFO ] Done reading resources.
  821. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  822. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  823. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  824. [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  825. [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  826. [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  827. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  828. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  829. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  830. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  831. [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  832. [DEBUG] update_constraints: PNP: 00ff.0 00 base 00000800 limit 000009fe io (fixed)
  833. [INFO ] DOMAIN: 0000: Resource ranges:
  834. [INFO ] * Base: 1000, Size: f000, Tag: 100
  835. [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x1007] limit: 1007 io
  836. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  837. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
  838. [DEBUG] update_constraints: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
  839. [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
  840. [DEBUG] update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7affffff mem (fixed)
  841. [DEBUG] update_constraints: PCI: 00:00.0 02 base 7b000000 limit 7b7fffff mem (fixed)
  842. [DEBUG] update_constraints: PCI: 00:00.0 03 base 7b800000 limit 7fffffff mem (fixed)
  843. [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 17fffffff mem (fixed)
  844. [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
  845. [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
  846. [DEBUG] update_constraints: PCI: 00:15.0 a8 base 20000000 limit 200fffff mem (fixed)
  847. [DEBUG] update_constraints: PCI: 00:1f.0 feb base feb00000 limit febfffff mem (fixed)
  848. [DEBUG] update_constraints: PCI: 00:1f.0 44 base fed03000 limit fed033ff mem (fixed)
  849. [DEBUG] update_constraints: PCI: 00:1f.0 4c base fed0c000 limit fed0ffff mem (fixed)
  850. [DEBUG] update_constraints: PCI: 00:1f.0 50 base fed08000 limit fed083ff mem (fixed)
  851. [DEBUG] update_constraints: PCI: 00:1f.0 54 base fed01000 limit fed013ff mem (fixed)
  852. [DEBUG] update_constraints: PCI: 00:1f.0 58 base fef00000 limit feffffff mem (fixed)
  853. [DEBUG] update_constraints: PCI: 00:1f.0 5c base fed05000 limit fed057ff mem (fixed)
  854. [DEBUG] update_constraints: PCI: 00:1f.0 f0 base fed1c000 limit fed1c3ff mem (fixed)
  855. [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
  856. [INFO ] DOMAIN: 0000: Resource ranges:
  857. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  858. [INFO ] * Base: f0000000, Size: eb00000, Tag: 200
  859. [INFO ] * Base: fec00000, Size: 101000, Tag: 200
  860. [INFO ] * Base: fed02000, Size: 1000, Tag: 200
  861. [INFO ] * Base: fed04000, Size: 1000, Tag: 200
  862. [INFO ] * Base: fed06000, Size: 2000, Tag: 200
  863. [INFO ] * Base: fed09000, Size: 3000, Tag: 200
  864. [INFO ] * Base: fed10000, Size: c000, Tag: 200
  865. [INFO ] * Base: fed1d000, Size: 23000, Tag: 200
  866. [INFO ] * Base: fed45000, Size: 1bb000, Tag: 200
  867. [INFO ] * Base: ff000000, Size: 1000000, Tag: 200
  868. [INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
  869. [DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  870. [DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
  871. [DEBUG] PCI: 00:15.0 10 * [0x90400000 - 0x905fffff] limit: 905fffff mem
  872. [DEBUG] PCI: 00:1c.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
  873. [DEBUG] PCI: 00:14.0 10 * [0x90700000 - 0x9070ffff] limit: 9070ffff mem
  874. [DEBUG] PCI: 00:18.0 10 * [0x90710000 - 0x90713fff] limit: 90713fff mem
  875. [DEBUG] PCI: 00:1b.0 10 * [0x90714000 - 0x90717fff] limit: 90717fff mem
  876. [DEBUG] PCI: 00:1e.0 10 * [0x90718000 - 0x9071bfff] limit: 9071bfff mem
  877. [DEBUG] PCI: 00:12.0 10 * [0x9071c000 - 0x9071cfff] limit: 9071cfff mem
  878. [DEBUG] PCI: 00:12.0 14 * [0x9071d000 - 0x9071dfff] limit: 9071dfff mem
  879. [DEBUG] PCI: 00:15.0 14 * [0x9071e000 - 0x9071efff] limit: 9071efff mem
  880. [DEBUG] PCI: 00:17.0 10 * [0x9071f000 - 0x9071ffff] limit: 9071ffff mem
  881. [DEBUG] PCI: 00:17.0 14 * [0x90720000 - 0x90720fff] limit: 90720fff mem
  882. [DEBUG] PCI: 00:18.0 14 * [0x90721000 - 0x90721fff] limit: 90721fff mem
  883. [DEBUG] PCI: 00:18.1 10 * [0x90722000 - 0x90722fff] limit: 90722fff mem
  884. [DEBUG] PCI: 00:18.1 14 * [0x90723000 - 0x90723fff] limit: 90723fff mem
  885. [DEBUG] PCI: 00:18.2 10 * [0x90724000 - 0x90724fff] limit: 90724fff mem
  886. [DEBUG] PCI: 00:18.2 14 * [0x90725000 - 0x90725fff] limit: 90725fff mem
  887. [DEBUG] PCI: 00:1e.0 14 * [0x90726000 - 0x90726fff] limit: 90726fff mem
  888. [DEBUG] PCI: 00:1d.0 10 * [0x90727000 - 0x907273ff] limit: 907273ff mem
  889. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
  890. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
  891. [INFO ] PCI: 00:1c.0: Resource ranges:
  892. [INFO ] * Base: 90600000, Size: 100000, Tag: 200
  893. [DEBUG] PCI: 01:00.0 10 * [0x90600000 - 0x90601fff] limit: 90601fff mem
  894. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
  895. [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  896. [ERROR] PCI: 00:00.0 missing set_resources
  897. [DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem
  898. [DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem
  899. [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x0000000000001007] size 0x00000008 gran 0x03 io
  900. [DEBUG] PCI: 00:12.0 10 <- [0x000000009071c000 - 0x000000009071cfff] size 0x00001000 gran 0x0c mem
  901. [DEBUG] PCI: 00:12.0 14 <- [0x000000009071d000 - 0x000000009071dfff] size 0x00001000 gran 0x0c mem
  902. [DEBUG] PCI: 00:14.0 10 <- [0x0000000090700000 - 0x000000009070ffff] size 0x00010000 gran 0x10 mem64
  903. [DEBUG] PCI: 00:15.0 10 <- [0x0000000090400000 - 0x00000000905fffff] size 0x00200000 gran 0x15 mem
  904. [DEBUG] PCI: 00:15.0 14 <- [0x000000009071e000 - 0x000000009071efff] size 0x00001000 gran 0x0c mem
  905. [DEBUG] PCI: 00:17.0 10 <- [0x000000009071f000 - 0x000000009071ffff] size 0x00001000 gran 0x0c mem
  906. [DEBUG] PCI: 00:17.0 14 <- [0x0000000090720000 - 0x0000000090720fff] size 0x00001000 gran 0x0c mem
  907. [DEBUG] PCI: 00:18.0 10 <- [0x0000000090710000 - 0x0000000090713fff] size 0x00004000 gran 0x0e mem
  908. [DEBUG] PCI: 00:18.0 14 <- [0x0000000090721000 - 0x0000000090721fff] size 0x00001000 gran 0x0c mem
  909. [DEBUG] PCI: 00:18.1 10 <- [0x0000000090722000 - 0x0000000090722fff] size 0x00001000 gran 0x0c mem
  910. [DEBUG] PCI: 00:18.1 14 <- [0x0000000090723000 - 0x0000000090723fff] size 0x00001000 gran 0x0c mem
  911. [DEBUG] PCI: 00:18.2 10 <- [0x0000000090724000 - 0x0000000090724fff] size 0x00001000 gran 0x0c mem
  912. [DEBUG] PCI: 00:18.2 14 <- [0x0000000090725000 - 0x0000000090725fff] size 0x00001000 gran 0x0c mem
  913. [DEBUG] PCI: 00:1b.0 10 <- [0x0000000090714000 - 0x0000000090717fff] size 0x00004000 gran 0x0e mem64
  914. [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
  915. [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  916. [DEBUG] PCI: 00:1c.0 20 <- [0x0000000090600000 - 0x00000000906fffff] size 0x00100000 gran 0x14 bus 01 mem
  917. [DEBUG] PCI: 01:00.0 10 <- [0x0000000090600000 - 0x0000000090601fff] size 0x00002000 gran 0x0d mem64
  918. [DEBUG] PCI: 00:1d.0 10 <- [0x0000000090727000 - 0x00000000907273ff] size 0x00000400 gran 0x0a mem
  919. [DEBUG] PCI: 00:1e.0 10 <- [0x0000000090718000 - 0x000000009071bfff] size 0x00004000 gran 0x0e mem
  920. [DEBUG] PCI: 00:1e.0 14 <- [0x0000000090726000 - 0x0000000090726fff] size 0x00001000 gran 0x0c mem
  921. [INFO ] Done setting resources.
  922. [INFO ] Done allocating resources.
  923. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
  924. [INFO ] Enabling resources...
  925. [DEBUG] PCI: 00:02.0 subsystem <- 8086/0f31
  926. [DEBUG] PCI: 00:02.0 cmd <- 03
  927. [DEBUG] PCI: 00:12.0 subsystem <- 8086/0f16
  928. [DEBUG] PCI: 00:12.0 cmd <- 106
  929. [DEBUG] PCI: 00:14.0 subsystem <- 8086/0f35
  930. [DEBUG] PCI: 00:14.0 cmd <- 102
  931. [DEBUG] PCI: 00:15.0 subsystem <- 8086/0f28
  932. [DEBUG] PCI: 00:15.0 cmd <- 102
  933. [DEBUG] PCI: 00:17.0 subsystem <- 8086/0f50
  934. [DEBUG] PCI: 00:17.0 cmd <- 106
  935. [DEBUG] PCI: 00:18.0 subsystem <- 8086/0f40
  936. [DEBUG] PCI: 00:18.0 cmd <- 106
  937. [DEBUG] PCI: 00:18.1 subsystem <- 8086/0f41
  938. [DEBUG] PCI: 00:18.1 cmd <- 102
  939. [DEBUG] PCI: 00:18.2 subsystem <- 8086/0f42
  940. [DEBUG] PCI: 00:18.2 cmd <- 102
  941. [DEBUG] PCI: 00:1b.0 subsystem <- 8086/0f04
  942. [DEBUG] PCI: 00:1b.0 cmd <- 102
  943. [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
  944. [DEBUG] PCI: 00:1c.0 subsystem <- 8086/0f48
  945. [DEBUG] PCI: 00:1c.0 cmd <- 106
  946. [DEBUG] PCI: 00:1d.0 subsystem <- 8086/0f34
  947. [DEBUG] PCI: 00:1d.0 cmd <- 102
  948. [DEBUG] PCI: 00:1e.0 subsystem <- 8086/0f06
  949. [DEBUG] PCI: 00:1e.0 cmd <- 106
  950. [DEBUG] PCI: 01:00.0 cmd <- 02
  951. [INFO ] done.
  952. [DEBUG] Applying SOC Thermal settings for DPTF.
  953. [INFO ] Initializing devices...
  954. [DEBUG] Root Device init
  955. [DEBUG] mainboard_ec_init
  956. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
  957. [DEBUG] Chrome EC: UHEPI not supported
  958. [DEBUG] Chrome EC: Set SCI mask to 0x00000000040609fb
  959. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  960. [DEBUG] Root Device init finished in 2 msecs
  961. [DEBUG] CPU_CLUSTER: 0 init
  962. [DEBUG] MTRR: Physical address space:
  963. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  964. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  965. [DEBUG] 0x00000000000c0000 - 0x000000007b7fffff size 0x7b740000 type 6
  966. [DEBUG] 0x000000007b800000 - 0x000000007fffffff size 0x04800000 type 0
  967. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  968. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  969. [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
  970. [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
  971. [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
  972. [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
  973. [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
  974. [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
  975. [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
  976. [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
  977. [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
  978. [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
  979. [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
  980. [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
  981. [DEBUG] CPU physical address size: 36 bits
  982. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
  983. [DEBUG] MTRR: UC selected as default type.
  984. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
  985. [DEBUG] MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
  986. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
  987. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
  988. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
  989.  
  990. [DEBUG] MTRR check
  991. [DEBUG] Fixed MTRRs : Enabled
  992. [DEBUG] Variable MTRRs: Enabled
  993.  
  994. [INFO ] Turbo is available but hidden
  995. [INFO ] Turbo is available and visible
  996. [DEBUG] Setting up SMI for CPU
  997. [INFO ] Will perform SMM setup.
  998. [INFO ] CPU: Intel(R) Celeron(R) CPU N2840 @ 2.16GHz.
  999. [INFO ] LAPIC 0x0 in XAPIC mode.
  1000. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  1001. [DEBUG] Processing 18 relocs. Offset value of 0x00030000
  1002. [DEBUG] Attempting to start 1 APs
  1003. [DEBUG] Waiting for 10ms after sending INIT.
  1004. [DEBUG] Waiting for SIPI to complete...
  1005. [DEBUG] done.
  1006. [DEBUG] Waiting for SIPI to complete...
  1007. [DEBUG] done.
  1008. [INFO ] LAPIC 0x2 in XAPIC mode.
  1009. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000838
  1010. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
  1011. [DEBUG] Processing 11 relocs. Offset value of 0x00038000
  1012. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1013. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1014. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1015. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  1016. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7af91cd6
  1017. [DEBUG] Installing permanent SMM handler to 0x7b000000
  1018. [DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
  1019. [DEBUG] HANDLER [0x7b6fb000-0x7b6ff048]
  1020.  
  1021. [DEBUG] CPU 0
  1022. [DEBUG] ss0 [0x7b6fac00-0x7b6fb000]
  1023. [DEBUG] stub0 [0x7b6f3000-0x7b6f31e0]
  1024.  
  1025. [DEBUG] CPU 1
  1026. [DEBUG] ss1 [0x7b6fa800-0x7b6fac00]
  1027. [DEBUG] stub1 [0x7b6f2c00-0x7b6f2de0]
  1028.  
  1029. [DEBUG] stacks [0x7b000000-0x7b001000]
  1030. [DEBUG] Loading module at 0x7b6fb000 with entry 0x7b6fbaff. filesize: 0x3f38 memsize: 0x4048
  1031. [DEBUG] Processing 236 relocs. Offset value of 0x7b6fb000
  1032. [DEBUG] Loading module at 0x7b6f3000 with entry 0x7b6f3000. filesize: 0x1e0 memsize: 0x1e0
  1033. [DEBUG] Processing 11 relocs. Offset value of 0x7b6f3000
  1034. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1035. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1036. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1037. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
  1038. [DEBUG] SMM Module: placing smm entry code at 7b6f2c00, cpu # 0x1
  1039. [DEBUG] SMM Module: stub loaded at 7b6f3000. Will call 0x7b6fbaff
  1040. [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1
  1041. [DEBUG] WAK USB GPE0a_STS: CORE_GPIO_0 SUS_GPIO_0
  1042. [DEBUG] ALT_GPIO_SMI: CORE_GPIO_0 SUS_GPIO_1 SUS_GPIO_0
  1043. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eb000, cpu = 0
  1044. [DEBUG] Relocation complete.
  1045. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eac00, cpu = 1
  1046. [INFO ] microcode: Update skipped, already up-to-date
  1047. [DEBUG] Relocation complete.
  1048. [INFO ] microcode: Update skipped, already up-to-date
  1049. [INFO ] Initializing CPU #0
  1050. [DEBUG] CPU: vendor Intel device 30678
  1051. [DEBUG] CPU: family 06, model 37, stepping 08
  1052. [DEBUG] Init BayTrail core.
  1053. [DEBUG] VMX status: enabled
  1054. [DEBUG] IA32_FEATURE_CONTROL status: locked
  1055. [INFO ] CPU #0 initialized
  1056. [INFO ] Initializing CPU #1
  1057. [DEBUG] CPU: vendor Intel device 30678
  1058. [DEBUG] CPU: family 06, model 37, stepping 08
  1059. [DEBUG] Init BayTrail core.
  1060. [INFO ] Turbo is available and visible
  1061. [DEBUG] VMX status: enabled
  1062. [DEBUG] IA32_FEATURE_CONTROL status: locked
  1063. [INFO ] CPU #1 initialized
  1064. [INFO ] bsp_do_flight_plan done after 0 msecs.
  1065. [DEBUG] Enabling SMIs.
  1066. [DEBUG] GPIO_ROUT = 00024000
  1067. [DEBUG] ALT_GPIO_SMI = 00000080
  1068. [DEBUG] CPU_CLUSTER: 0 init finished in 10 msecs
  1069. [DEBUG] PCI: 00:02.0 init
  1070. [INFO ] GFX: Pre VBIOS Init
  1071. [INFO ] GFX: Power Management Init
  1072. [INFO ] GFX: Initialize PIPEA
  1073. [INFO ] GFX: Post VBIOS Init
  1074. [DEBUG] PCI: 00:02.0 init finished in 0 msecs
  1075. [DEBUG] PCI: 00:12.0 init
  1076. [DEBUG] Overriding SD Card controller caps.
  1077. [DEBUG] PCI: 00:12.0 init finished in 0 msecs
  1078. [DEBUG] PCI: 00:14.0 init
  1079. [INFO ] USB: Route ports to XHCI controller
  1080. [DEBUG] PCI: 00:14.0 init finished in 0 msecs
  1081. [DEBUG] PCI: 00:15.0 init
  1082. [DEBUG] LPE Audio codec clock set to 25MHz.
  1083. [DEBUG] PCI: 00:15.0 init finished in 0 msecs
  1084. [DEBUG] PCI: 00:17.0 init
  1085. [DEBUG] eMMC init
  1086. [DEBUG] PCI: 00:17.0 init finished in 0 msecs
  1087. [DEBUG] PCI: 00:18.0 init
  1088. [ERROR] Null dereference at eip: 0x7af7d196
  1089. [DEBUG] PCI: 00:18.0 init finished in 0 msecs
  1090. [DEBUG] PCI: 00:18.1 init
  1091. [DEBUG] Releasing I2C device from reset.
  1092. [ERROR] Null dereference at eip: 0x7af7d196
  1093. [DEBUG] PCI: 00:18.1 init finished in 0 msecs
  1094. [DEBUG] PCI: 00:18.2 init
  1095. [DEBUG] Releasing I2C device from reset.
  1096. [ERROR] Null dereference at eip: 0x7af7d196
  1097. [DEBUG] PCI: 00:18.2 init finished in 0 msecs
  1098. [DEBUG] PCI: 00:1b.0 init
  1099. [DEBUG] codec mask = 4
  1100. [DEBUG] HDA: Initializing codec #2
  1101. [DEBUG] HDA: codec viddid: 80862882
  1102. [DEBUG] HDA: verb loaded.
  1103. [DEBUG] PCI: 00:1b.0 init finished in 3 msecs
  1104. [DEBUG] PCI: 00:1c.0 init
  1105. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs
  1106. [DEBUG] PCI: 00:1d.0 init
  1107. [DEBUG] PCI: 00:1d.0: Disabling device: 1d.0
  1108. [DEBUG] Power management CAP offset 0x70.
  1109. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs
  1110. [DEBUG] PCI: 00:1e.0 init
  1111. [DEBUG] PCI: 00:1e.0 init finished in 0 msecs
  1112. [DEBUG] PCI: 00:1f.0 init
  1113. [DEBUG] Disabling slp_x stretching.
  1114. [DEBUG] PCI: 00:1f.0 init finished in 0 msecs
  1115. [DEBUG] PCI: 01:00.0 init
  1116. [DEBUG] PCI: 01:00.0 init finished in 0 msecs
  1117. [DEBUG] PNP: 00ff.0 init
  1118. [DEBUG] Google Chrome EC: Initializing
  1119. [DEBUG] Google Chrome EC: version:
  1120. [DEBUG] ro: swanky_v1.6.197-c5a86fe
  1121. [DEBUG] rw: swanky_v1.6.205-92b7845
  1122. [DEBUG] running image: 2
  1123. [DEBUG] PNP: 00ff.0 init finished in 1 msecs
  1124. [INFO ] Devices initialized
  1125. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 20 / 0 ms
  1126. [DEBUG] FMAP: area SMMSTORE found @ 5c0000 (262144 bytes)
  1127. [DEBUG] smm store: 4 # blocks with size 0x10000
  1128. [INFO ] SMMSTORE: Setting up SMI handler
  1129. [INFO ] Found TPM SLB9635 TT 1.2 by Infineon
  1130. [INFO ] TPM: Handle S3 resume.
  1131. [DEBUG] TPM: Resume
  1132. [DEBUG] TPM: command 0x99 returned 0x0
  1133. [INFO ] TPM: setup succeeded
  1134. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 5 / 0 ms
  1135. [INFO ] Finalize devices...
  1136. [INFO ] Devices finalized
  1137. [DEBUG] Trying to find the wakeup vector...
  1138. [DEBUG] Looking on 0x000f0000 for valid checksum
  1139. [DEBUG] Checksum 1 passed
  1140. [DEBUG] Checksum 2 passed all OK
  1141. [DEBUG] RSDP found at 0x000f0000
  1142. [DEBUG] RSDT found at 0x7af2a030 ends at 0x7af2a06c
  1143. [DEBUG] FADT found at 0x7af2e170
  1144. [DEBUG] FACS found at 0x7af2a240
  1145. [DEBUG] OS waking vector is 0x000981f0
  1146. [DEBUG] Applying perf/power settings.
  1147. [DEBUG] BS: BS_OS_RESUME entry times (exec / console): 1 / 0 ms
  1148.  
  1149.  
  1150. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 bootblock starting (log level: 7)...
  1151. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x604000.
  1152. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 6
  1153. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  1154. [INFO ] CBFS: mcache @0xfe002e00 built for 17 files, used 0x374 of 0x4000 bytes
  1155. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x65d0 in mcache @0xfe002e2c
  1156. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  1157.  
  1158.  
  1159. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 romstage starting (log level: 7)...
  1160. [DEBUG] Enabling VR PS2 mode: VNN VCC
  1161. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  1162. [INFO ] CBFS: Found 'spd.bin' @0x39c00 size 0x400 in mcache @0xfe002f98
  1163. [DEBUG] ram_id=2, total_spds: 4
  1164. [DEBUG] pm1_sts: a000 pm1_en: 0100 pm1_cnt: 00001400
  1165. [DEBUG] gpe0_sts: 00020000 gpe0_en: 00032000 tco_sts: 00000000
  1166. [DEBUG] prsts: 04450900 gen_pmcon1: 00201038 gen_pmcon2: 00000000
  1167. [DEBUG] prev_sleep_state = S3
  1168. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  1169. [INFO ] CBFS: Found 'mrc.bin' @0x19adc0 size 0x11218 in mcache @0xfe0030f0
  1170. BayTrail-MD MRC wrapper v5
  1171. Training for Memory Down designs.
  1172. Applying weaker ODT settings. DRAM ODT is 120.
  1173. [INFO ] MRC v0.97
  1174. [INFO ] 2 channels of DDR3 @ 1333MHz
  1175. [DEBUG] MRC Wrapper returned 0
  1176. [DEBUG] MRC data at 0xfe00965f 5719 bytes
  1177. [DEBUG] SMM Memory Map
  1178. [DEBUG] SMRAM : 0x7b000000 0x800000
  1179. [DEBUG] Subregion 0: 0x7b000000 0x700000
  1180. [DEBUG] Subregion 1: 0x7b700000 0x100000
  1181. [DEBUG] Subregion 2: 0x7b800000 0x0
  1182. [DEBUG] S3 Resume
  1183. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  1184.  
  1185.  
  1186. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 postcar starting (log level: 7)...
  1187. [DEBUG] S3 Resume
  1188. [DEBUG] Jumping to image.
  1189.  
  1190.  
  1191. [NOTE ] coreboot-4.18-156-g8a76e170c64-MrChromebox-4.18.1 Thu Oct 27 13:24:50 UTC 2022 ramstage starting (log level: 7)...
  1192. [DEBUG] S3 Resume
  1193. [DEBUG] FMAP: area COREBOOT found @ 604200 (2080256 bytes)
  1194. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x6700 size 0x19800 in mcache @0x7afdd0ac
  1195. [DEBUG] microcode: sig=0x30678 pf=0x8 revision=0x838
  1196. [DEBUG] BYT: cpuid 00030678 cpus 2 rid 0e step C0
  1197. [DEBUG] msr(17) = 000c000090341f4b
  1198. [DEBUG] msr(ce) = 0000060000001a00
  1199. [DEBUG] ModPHY init entry
  1200. [DEBUG] SOC B0 and later ModPhy Table programming
  1201. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1202. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1203. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1204. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1205. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1206. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1207. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1208. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1209. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1210. [DEBUG] Polling bit3 of R_PCH_PMC_MTPMC1 = 8
  1211. [DEBUG] ModPHY init done
  1212. [DEBUG] Tri-state TDO and TMS
  1213. [DEBUG] Initializing sideband SCC registers.
  1214. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 2 / 0 ms
  1215. [INFO ] Enumerating buses...
  1216. [DEBUG] Root Device scanning...
  1217. [DEBUG] CPU_CLUSTER: 0 enabled
  1218. [DEBUG] DOMAIN: 0000 enabled
  1219. [DEBUG] DOMAIN: 0000 scanning...
  1220. [DEBUG] PCI: pci_scan_bus for bus 00
  1221. [DEBUG] PCI: 00:00.0 [8086/0f00] enabled
  1222. [DEBUG] PCI: 00:02.0 [8086/0f31] enabled
  1223. [DEBUG] PCI: 00:10.0: Disabling device: 10.0
  1224. [DEBUG] Power management CAP offset 0x80.
  1225. [DEBUG] PCI: 00:11.0: Disabling device: 11.0
  1226. [DEBUG] Power management CAP offset 0x80.
  1227. [DEBUG] PCI: 00:12.0 [8086/0f16] enabled
  1228. [INFO ] PCI: Static device PCI: 00:13.0 not found, disabling it.
  1229. [DEBUG] PCI: 00:14.0 [8086/0f35] enabled
  1230. [DEBUG] PCI: 00:15.0 [8086/0f28] enabled
  1231. [DEBUG] PCI: 00:17.0 [8086/0f50] enabled
  1232. [DEBUG] PCI: 00:18.0 [8086/0f40] enabled
  1233. [DEBUG] PCI: 00:18.1 [8086/0f41] enabled
  1234. [DEBUG] PCI: 00:18.2 [8086/0f42] enabled
  1235. [DEBUG] PCI: 00:18.3: Disabling device: 18.3
  1236. [DEBUG] Power management CAP offset 0x80.
  1237. [DEBUG] PCI: 00:18.4: Disabling device: 18.4
  1238. [DEBUG] Power management CAP offset 0x80.
  1239. [DEBUG] PCI: 00:18.5: Disabling device: 18.5
  1240. [DEBUG] Power management CAP offset 0x80.
  1241. [DEBUG] PCI: 00:18.5 [8086/0f45] disabled
  1242. [DEBUG] PCI: 00:18.6: Disabling device: 18.6
  1243. [DEBUG] Power management CAP offset 0x80.
  1244. [DEBUG] PCI: 00:18.6 [8086/0f46] disabled
  1245. [DEBUG] PCI: 00:18.7: Disabling device: 18.7
  1246. [DEBUG] Power management CAP offset 0x80.
  1247. [DEBUG] PCI: 00:1a.0: Disabling device: 1a.0
  1248. [DEBUG] PCI: 00:1b.0 [8086/0f04] enabled
  1249. [DEBUG] PCI: 00:1c.0 [8086/0f48] enabled
  1250. [DEBUG] No PCIe device present.
  1251. [WARN ] reg_script_run_step: POLL timeout waiting for 0x328 to be 0x1000000, got 0x0
  1252. [DEBUG] PCI: 00:1c.1: Disabling device: 1c.1
  1253. [DEBUG] Power management CAP offset 0xa0.
  1254. [DEBUG] PCI: 00:1c.1 [8086/0f4a] disabled
  1255. [DEBUG] PCI: 00:1c.2: Disabling device: 1c.2
  1256. [DEBUG] Power management CAP offset 0xa0.
  1257. [DEBUG] PCI: 00:1c.3: Disabling device: 1c.3
  1258. [DEBUG] Power management CAP offset 0xa0.
  1259. [DEBUG] PCI: 00:1d.0 [8086/0f34] enabled
  1260. [DEBUG] PCI: 00:1e.0 [8086/0f06] enabled
  1261. [DEBUG] PCI: 00:1e.1: Disabling device: 1e.1
  1262. [DEBUG] Power management CAP offset 0x80.
  1263. [DEBUG] PCI: 00:1e.2: Disabling device: 1e.2
  1264. [DEBUG] Power management CAP offset 0x80.
  1265. [DEBUG] PCI: 00:1e.3: Disabling device: 1e.3
  1266. [DEBUG] Power management CAP offset 0x80.
  1267. [DEBUG] PCI: 00:1e.4: Disabling device: 1e.4
  1268. [DEBUG] Power management CAP offset 0x80.
  1269. [DEBUG] PCI: 00:1e.4 [8086/0f0c] disabled
  1270. [DEBUG] PCI: 00:1e.5: Disabling device: 1e.5
  1271. [DEBUG] Power management CAP offset 0x80.
  1272. [DEBUG] PCI: 00:1e.5 [8086/0f0e] disabled
  1273. [DEBUG] PCI: 00:1f.0 [8086/0f1c] enabled
  1274. [DEBUG] PCI: 00:1f.3: Disabling device: 1f.3
  1275. [DEBUG] Power management CAP offset 0x50.
  1276. [WARN ] PCI: Leftover static devices:
  1277. [WARN ] PCI: 00:10.0
  1278. [WARN ] PCI: 00:11.0
  1279. [WARN ] PCI: 00:13.0
  1280. [WARN ] PCI: 00:18.3
  1281. [WARN ] PCI: 00:18.4
  1282. [WARN ] PCI: 00:18.7
  1283. [WARN ] PCI: 00:1a.0
  1284. [WARN ] PCI: 00:1c.2
  1285. [WARN ] PCI: 00:1c.3
  1286. [WARN ] PCI: 00:1e.1
  1287. [WARN ] PCI: 00:1e.2
  1288. [WARN ] PCI: 00:1e.3
  1289. [WARN ] PCI: 00:1f.3
  1290. [WARN ] PCI: Check your devicetree.cb.
  1291. [DEBUG] PCI: 00:1c.0 scanning...
  1292. [DEBUG] PCI: pci_scan_bus for bus 01
  1293. [DEBUG] PCI: 01:00.0 [8086/08b1] enabled
  1294. [INFO ] Enabling Common Clock Configuration
  1295. [INFO ] ASPM: Enabled L1
  1296. [INFO ] PCIe: Max_Payload_Size adjusted to 128
  1297. [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
  1298. [DEBUG] PCI: 00:1f.0 scanning...
  1299. [DEBUG] PNP: 0c31.0 enabled
  1300. [DEBUG] PNP: 00ff.1 enabled
  1301. [DEBUG] PNP: 00ff.0 enabled
  1302. [DEBUG] PNP: 00ff.0 scanning...
  1303. [DEBUG] scan_bus: bus PNP: 00ff.0 finished in 0 msecs
  1304. [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
  1305. [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 50 msecs
  1306. [DEBUG] scan_bus: bus Root Device finished in 50 msecs
  1307. [INFO ] done
  1308. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 51 / 0 ms
  1309. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  1310. [DEBUG] FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
  1311. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  1312. [INFO ] Manufacturer: ef
  1313. [INFO ] SF: Detected ef 6017 with sector size 0x1000, total 0x800000
  1314. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  1315. [DEBUG] found VGA at PCI: 00:02.0
  1316. [DEBUG] Setting up VGA for PCI: 00:02.0
  1317. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  1318. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  1319. [INFO ] Allocating resources...
  1320. [INFO ] Reading resources...
  1321. [INFO ] Available memory above 4GB: 2048M
  1322. [ERROR] PNP: 00ff.1 missing read_resources
  1323. [INFO ] Done reading resources.
  1324. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  1325. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  1326. [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  1327. [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  1328. [DEBUG] PCI: 01:00.0 10 * [0x0 - 0x1fff] mem
  1329. [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  1330. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  1331. [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  1332. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  1333. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  1334. [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  1335. [DEBUG] update_constraints: PNP: 00ff.0 00 base 00000800 limit 000009fe io (fixed)
  1336. [INFO ] DOMAIN: 0000: Resource ranges:
  1337. [INFO ] * Base: 1000, Size: f000, Tag: 100
  1338. [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x1007] limit: 1007 io
  1339. [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  1340. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
  1341. [DEBUG] update_constraints: PCI: 00:00.0 27 base e0000000 limit efffffff mem (fixed)
  1342. [DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
  1343. [DEBUG] update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7affffff mem (fixed)
  1344. [DEBUG] update_constraints: PCI: 00:00.0 02 base 7b000000 limit 7b7fffff mem (fixed)
  1345. [DEBUG] update_constraints: PCI: 00:00.0 03 base 7b800000 limit 7fffffff mem (fixed)
  1346. [DEBUG] update_constraints: PCI: 00:00.0 04 base 100000000 limit 17fffffff mem (fixed)
  1347. [DEBUG] update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
  1348. [DEBUG] update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
  1349. [DEBUG] update_constraints: PCI: 00:15.0 a8 base 20000000 limit 200fffff mem (fixed)
  1350. [DEBUG] update_constraints: PCI: 00:1f.0 feb base feb00000 limit febfffff mem (fixed)
  1351. [DEBUG] update_constraints: PCI: 00:1f.0 44 base fed03000 limit fed033ff mem (fixed)
  1352. [DEBUG] update_constraints: PCI: 00:1f.0 4c base fed0c000 limit fed0ffff mem (fixed)
  1353. [DEBUG] update_constraints: PCI: 00:1f.0 50 base fed08000 limit fed083ff mem (fixed)
  1354. [DEBUG] update_constraints: PCI: 00:1f.0 54 base fed01000 limit fed013ff mem (fixed)
  1355. [DEBUG] update_constraints: PCI: 00:1f.0 58 base fef00000 limit feffffff mem (fixed)
  1356. [DEBUG] update_constraints: PCI: 00:1f.0 5c base fed05000 limit fed057ff mem (fixed)
  1357. [DEBUG] update_constraints: PCI: 00:1f.0 f0 base fed1c000 limit fed1c3ff mem (fixed)
  1358. [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
  1359. [INFO ] DOMAIN: 0000: Resource ranges:
  1360. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  1361. [INFO ] * Base: f0000000, Size: eb00000, Tag: 200
  1362. [INFO ] * Base: fec00000, Size: 101000, Tag: 200
  1363. [INFO ] * Base: fed02000, Size: 1000, Tag: 200
  1364. [INFO ] * Base: fed04000, Size: 1000, Tag: 200
  1365. [INFO ] * Base: fed06000, Size: 2000, Tag: 200
  1366. [INFO ] * Base: fed09000, Size: 3000, Tag: 200
  1367. [INFO ] * Base: fed10000, Size: c000, Tag: 200
  1368. [INFO ] * Base: fed1d000, Size: 23000, Tag: 200
  1369. [INFO ] * Base: fed45000, Size: 1bb000, Tag: 200
  1370. [INFO ] * Base: ff000000, Size: 1000000, Tag: 200
  1371. [INFO ] * Base: 180000000, Size: e80000000, Tag: 100200
  1372. [DEBUG] PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  1373. [DEBUG] PCI: 00:02.0 10 * [0x90000000 - 0x903fffff] limit: 903fffff mem
  1374. [DEBUG] PCI: 00:15.0 10 * [0x90400000 - 0x905fffff] limit: 905fffff mem
  1375. [DEBUG] PCI: 00:1c.0 20 * [0x90600000 - 0x906fffff] limit: 906fffff mem
  1376. [DEBUG] PCI: 00:14.0 10 * [0x90700000 - 0x9070ffff] limit: 9070ffff mem
  1377. [DEBUG] PCI: 00:18.0 10 * [0x90710000 - 0x90713fff] limit: 90713fff mem
  1378. [DEBUG] PCI: 00:1b.0 10 * [0x90714000 - 0x90717fff] limit: 90717fff mem
  1379. [DEBUG] PCI: 00:1e.0 10 * [0x90718000 - 0x9071bfff] limit: 9071bfff mem
  1380. [DEBUG] PCI: 00:12.0 10 * [0x9071c000 - 0x9071cfff] limit: 9071cfff mem
  1381. [DEBUG] PCI: 00:12.0 14 * [0x9071d000 - 0x9071dfff] limit: 9071dfff mem
  1382. [DEBUG] PCI: 00:15.0 14 * [0x9071e000 - 0x9071efff] limit: 9071efff mem
  1383. [DEBUG] PCI: 00:17.0 10 * [0x9071f000 - 0x9071ffff] limit: 9071ffff mem
  1384. [DEBUG] PCI: 00:17.0 14 * [0x90720000 - 0x90720fff] limit: 90720fff mem
  1385. [DEBUG] PCI: 00:18.0 14 * [0x90721000 - 0x90721fff] limit: 90721fff mem
  1386. [DEBUG] PCI: 00:18.1 10 * [0x90722000 - 0x90722fff] limit: 90722fff mem
  1387. [DEBUG] PCI: 00:18.1 14 * [0x90723000 - 0x90723fff] limit: 90723fff mem
  1388. [DEBUG] PCI: 00:18.2 10 * [0x90724000 - 0x90724fff] limit: 90724fff mem
  1389. [DEBUG] PCI: 00:18.2 14 * [0x90725000 - 0x90725fff] limit: 90725fff mem
  1390. [DEBUG] PCI: 00:1e.0 14 * [0x90726000 - 0x90726fff] limit: 90726fff mem
  1391. [DEBUG] PCI: 00:1d.0 10 * [0x90727000 - 0x907273ff] limit: 907273ff mem
  1392. [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
  1393. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff
  1394. [INFO ] PCI: 00:1c.0: Resource ranges:
  1395. [INFO ] * Base: 90600000, Size: 100000, Tag: 200
  1396. [DEBUG] PCI: 01:00.0 10 * [0x90600000 - 0x90601fff] limit: 90601fff mem
  1397. [DEBUG] PCI: 00:1c.0 mem: base: 90600000 size: 100000 align: 20 gran: 20 limit: 906fffff done
  1398. [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  1399. [ERROR] PCI: 00:00.0 missing set_resources
  1400. [DEBUG] PCI: 00:02.0 10 <- [0x0000000090000000 - 0x00000000903fffff] size 0x00400000 gran 0x16 mem
  1401. [DEBUG] PCI: 00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem
  1402. [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x0000000000001007] size 0x00000008 gran 0x03 io
  1403. [DEBUG] PCI: 00:12.0 10 <- [0x000000009071c000 - 0x000000009071cfff] size 0x00001000 gran 0x0c mem
  1404. [DEBUG] PCI: 00:12.0 14 <- [0x000000009071d000 - 0x000000009071dfff] size 0x00001000 gran 0x0c mem
  1405. [DEBUG] PCI: 00:14.0 10 <- [0x0000000090700000 - 0x000000009070ffff] size 0x00010000 gran 0x10 mem64
  1406. [DEBUG] PCI: 00:15.0 10 <- [0x0000000090400000 - 0x00000000905fffff] size 0x00200000 gran 0x15 mem
  1407. [DEBUG] PCI: 00:15.0 14 <- [0x000000009071e000 - 0x000000009071efff] size 0x00001000 gran 0x0c mem
  1408. [DEBUG] PCI: 00:17.0 10 <- [0x000000009071f000 - 0x000000009071ffff] size 0x00001000 gran 0x0c mem
  1409. [DEBUG] PCI: 00:17.0 14 <- [0x0000000090720000 - 0x0000000090720fff] size 0x00001000 gran 0x0c mem
  1410. [DEBUG] PCI: 00:18.0 10 <- [0x0000000090710000 - 0x0000000090713fff] size 0x00004000 gran 0x0e mem
  1411. [DEBUG] PCI: 00:18.0 14 <- [0x0000000090721000 - 0x0000000090721fff] size 0x00001000 gran 0x0c mem
  1412. [DEBUG] PCI: 00:18.1 10 <- [0x0000000090722000 - 0x0000000090722fff] size 0x00001000 gran 0x0c mem
  1413. [DEBUG] PCI: 00:18.1 14 <- [0x0000000090723000 - 0x0000000090723fff] size 0x00001000 gran 0x0c mem
  1414. [DEBUG] PCI: 00:18.2 10 <- [0x0000000090724000 - 0x0000000090724fff] size 0x00001000 gran 0x0c mem
  1415. [DEBUG] PCI: 00:18.2 14 <- [0x0000000090725000 - 0x0000000090725fff] size 0x00001000 gran 0x0c mem
  1416. [DEBUG] PCI: 00:1b.0 10 <- [0x0000000090714000 - 0x0000000090717fff] size 0x00004000 gran 0x0e mem64
  1417. [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
  1418. [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  1419. [DEBUG] PCI: 00:1c.0 20 <- [0x0000000090600000 - 0x00000000906fffff] size 0x00100000 gran 0x14 bus 01 mem
  1420. [DEBUG] PCI: 01:00.0 10 <- [0x0000000090600000 - 0x0000000090601fff] size 0x00002000 gran 0x0d mem64
  1421. [DEBUG] PCI: 00:1d.0 10 <- [0x0000000090727000 - 0x00000000907273ff] size 0x00000400 gran 0x0a mem
  1422. [DEBUG] PCI: 00:1e.0 10 <- [0x0000000090718000 - 0x000000009071bfff] size 0x00004000 gran 0x0e mem
  1423. [DEBUG] PCI: 00:1e.0 14 <- [0x0000000090726000 - 0x0000000090726fff] size 0x00001000 gran 0x0c mem
  1424. [INFO ] Done setting resources.
  1425. [INFO ] Done allocating resources.
  1426. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms
  1427. [INFO ] Enabling resources...
  1428. [DEBUG] PCI: 00:02.0 subsystem <- 8086/0f31
  1429. [DEBUG] PCI: 00:02.0 cmd <- 03
  1430. [DEBUG] PCI: 00:12.0 subsystem <- 8086/0f16
  1431. [DEBUG] PCI: 00:12.0 cmd <- 106
  1432. [DEBUG] PCI: 00:14.0 subsystem <- 8086/0f35
  1433. [DEBUG] PCI: 00:14.0 cmd <- 102
  1434. [DEBUG] PCI: 00:15.0 subsystem <- 8086/0f28
  1435. [DEBUG] PCI: 00:15.0 cmd <- 102
  1436. [DEBUG] PCI: 00:17.0 subsystem <- 8086/0f50
  1437. [DEBUG] PCI: 00:17.0 cmd <- 106
  1438. [DEBUG] PCI: 00:18.0 subsystem <- 8086/0f40
  1439. [DEBUG] PCI: 00:18.0 cmd <- 106
  1440. [DEBUG] PCI: 00:18.1 subsystem <- 8086/0f41
  1441. [DEBUG] PCI: 00:18.1 cmd <- 102
  1442. [DEBUG] PCI: 00:18.2 subsystem <- 8086/0f42
  1443. [DEBUG] PCI: 00:18.2 cmd <- 102
  1444. [DEBUG] PCI: 00:1b.0 subsystem <- 8086/0f04
  1445. [DEBUG] PCI: 00:1b.0 cmd <- 102
  1446. [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013
  1447. [DEBUG] PCI: 00:1c.0 subsystem <- 8086/0f48
  1448. [DEBUG] PCI: 00:1c.0 cmd <- 106
  1449. [DEBUG] PCI: 00:1d.0 subsystem <- 8086/0f34
  1450. [DEBUG] PCI: 00:1d.0 cmd <- 102
  1451. [DEBUG] PCI: 00:1e.0 subsystem <- 8086/0f06
  1452. [DEBUG] PCI: 00:1e.0 cmd <- 106
  1453. [DEBUG] PCI: 01:00.0 cmd <- 02
  1454. [INFO ] done.
  1455. [DEBUG] Applying SOC Thermal settings for DPTF.
  1456. [INFO ] Initializing devices...
  1457. [DEBUG] Root Device init
  1458. [DEBUG] mainboard_ec_init
  1459. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
  1460. [DEBUG] Chrome EC: UHEPI not supported
  1461. [DEBUG] Chrome EC: Set SCI mask to 0x00000000040609fb
  1462. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  1463. [DEBUG] Root Device init finished in 3 msecs
  1464. [DEBUG] CPU_CLUSTER: 0 init
  1465. [DEBUG] MTRR: Physical address space:
  1466. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  1467. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  1468. [DEBUG] 0x00000000000c0000 - 0x000000007b7fffff size 0x7b740000 type 6
  1469. [DEBUG] 0x000000007b800000 - 0x000000007fffffff size 0x04800000 type 0
  1470. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  1471. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  1472. [DEBUG] 0x0000000100000000 - 0x000000017fffffff size 0x80000000 type 6
  1473. [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606
  1474. [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606
  1475. [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
  1476. [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606
  1477. [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606
  1478. [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606
  1479. [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606
  1480. [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606
  1481. [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606
  1482. [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606
  1483. [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606
  1484. [DEBUG] CPU physical address size: 36 bits
  1485. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/5.
  1486. [DEBUG] MTRR: UC selected as default type.
  1487. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
  1488. [DEBUG] MTRR: 1 base 0x000000007b800000 mask 0x0000000fff800000 type 0
  1489. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
  1490. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000000ff0000000 type 1
  1491. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000000f80000000 type 6
  1492.  
  1493. [DEBUG] MTRR check
  1494. [DEBUG] Fixed MTRRs : Enabled
  1495. [DEBUG] Variable MTRRs: Enabled
  1496.  
  1497. [INFO ] Turbo is available but hidden
  1498. [INFO ] Turbo is available and visible
  1499. [DEBUG] Setting up SMI for CPU
  1500. [INFO ] Will perform SMM setup.
  1501. [INFO ] CPU: Intel(R) Celeron(R) CPU N2840 @ 2.16GHz.
  1502. [INFO ] LAPIC 0x0 in XAPIC mode.
  1503. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  1504. [DEBUG] Processing 18 relocs. Offset value of 0x00030000
  1505. [DEBUG] Attempting to start 1 APs
  1506. [DEBUG] Waiting for 10ms after sending INIT.
  1507. [DEBUG] Waiting for SIPI to complete...
  1508. [DEBUG] done.
  1509. [DEBUG] Waiting for SIPI to complete...
  1510. [DEBUG] done.
  1511. [INFO ] LAPIC 0x2 in XAPIC mode.
  1512. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000838
  1513. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
  1514. [DEBUG] Processing 11 relocs. Offset value of 0x00038000
  1515. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1516. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1517. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1518. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  1519. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7af91cd6
  1520. [DEBUG] Installing permanent SMM handler to 0x7b000000
  1521. [DEBUG] FX_SAVE [0x7b6ffc00-0x7b700000]
  1522. [DEBUG] HANDLER [0x7b6fb000-0x7b6ff048]
  1523.  
  1524. [DEBUG] CPU 0
  1525. [DEBUG] ss0 [0x7b6fac00-0x7b6fb000]
  1526. [DEBUG] stub0 [0x7b6f3000-0x7b6f31e0]
  1527.  
  1528. [DEBUG] CPU 1
  1529. [DEBUG] ss1 [0x7b6fa800-0x7b6fac00]
  1530. [DEBUG] stub1 [0x7b6f2c00-0x7b6f2de0]
  1531.  
  1532. [DEBUG] stacks [0x7b000000-0x7b001000]
  1533. [DEBUG] Loading module at 0x7b6fb000 with entry 0x7b6fbaff. filesize: 0x3f38 memsize: 0x4048
  1534. [DEBUG] Processing 236 relocs. Offset value of 0x7b6fb000
  1535. [DEBUG] Loading module at 0x7b6f3000 with entry 0x7b6f3000. filesize: 0x1e0 memsize: 0x1e0
  1536. [DEBUG] Processing 11 relocs. Offset value of 0x7b6f3000
  1537. [DEBUG] smm_module_setup_stub: stack_top = 0x7b001000
  1538. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  1539. [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
  1540. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x700000
  1541. [DEBUG] SMM Module: placing smm entry code at 7b6f2c00, cpu # 0x1
  1542. [DEBUG] SMM Module: stub loaded at 7b6f3000. Will call 0x7b6fbaff
  1543. [DEBUG] Initializing Southbridge SMI...SMI_STS: PM1
  1544. [DEBUG] WAK USB GPE0a_STS: CORE_GPIO_0 SUS_GPIO_1
  1545. [DEBUG] ALT_GPIO_SMI: CORE_GPIO_0 SUS_GPIO_1
  1546. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eb000, cpu = 0
  1547. [DEBUG] Relocation complete.
  1548. [INFO ] microcode: Update skipped, already up-to-date
  1549. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b6eac00, cpu = 1
  1550. [DEBUG] Relocation complete.
  1551. [INFO ] microcode: Update skipped, already up-to-date
  1552. [INFO ] Initializing CPU #0
  1553. [DEBUG] CPU: vendor Intel device 30678
  1554. [DEBUG] CPU: family 06, model 37, stepping 08
  1555. [DEBUG] Init BayTrail core.
  1556. [DEBUG] VMX status: enabled
  1557. [DEBUG] IA32_FEATURE_CONTROL status: locked
  1558. [INFO ] CPU #0 initialized
  1559. [INFO ] Initializing CPU #1
  1560. [DEBUG] CPU: vendor Intel device 30678
  1561. [DEBUG] CPU: family 06, model 37, stepping 08
  1562. [DEBUG] Init BayTrail core.
  1563. [INFO ] Turbo is available and visible
  1564. [DEBUG] VMX status: enabled
  1565. [DEBUG] IA32_FEATURE_CONTROL status: locked
  1566. [INFO ] CPU #1 initialized
  1567. [INFO ] bsp_do_flight_plan done after 0 msecs.
  1568. [DEBUG] Enabling SMIs.
  1569. [DEBUG] GPIO_ROUT = 00024000
  1570. [DEBUG] ALT_GPIO_SMI = 00000080
  1571. [DEBUG] CPU_CLUSTER: 0 init finished in 10 msecs
  1572. [DEBUG] PCI: 00:02.0 init
  1573. [INFO ] GFX: Pre VBIOS Init
  1574. [INFO ] GFX: Power Management Init
  1575. [INFO ] GFX: Initialize PIPEA
  1576. [INFO ] GFX: Post VBIOS Init
  1577. [DEBUG] PCI: 00:02.0 init finished in 0 msecs
  1578. [DEBUG] PCI: 00:12.0 init
  1579. [DEBUG] Overriding SD Card controller caps.
  1580. [DEBUG] PCI: 00:12.0 init finished in 0 msecs
  1581. [DEBUG] PCI: 00:14.0 init
  1582. [INFO ] USB: Route ports to XHCI controller
  1583. [DEBUG] PCI: 00:14.0 init finished in 0 msecs
  1584. [DEBUG] PCI: 00:15.0 init
  1585. [DEBUG] LPE Audio codec clock set to 25MHz.
  1586. [DEBUG] PCI: 00:15.0 init finished in 0 msecs
  1587. [DEBUG] PCI: 00:17.0 init
  1588. [DEBUG] eMMC init
  1589. [DEBUG] PCI: 00:17.0 init finished in 0 msecs
  1590. [DEBUG] PCI: 00:18.0 init
  1591. [ERROR] Null dereference at eip: 0x7af7d196
  1592. [DEBUG] PCI: 00:18.0 init finished in 0 msecs
  1593. [DEBUG] PCI: 00:18.1 init
  1594. [DEBUG] Releasing I2C device from reset.
  1595. [ERROR] Null dereference at eip: 0x7af7d196
  1596. [DEBUG] PCI: 00:18.1 init finished in 0 msecs
  1597. [DEBUG] PCI: 00:18.2 init
  1598. [DEBUG] Releasing I2C device from reset.
  1599. [ERROR] Null dereference at eip: 0x7af7d196
  1600. [DEBUG] PCI: 00:18.2 init finished in 0 msecs
  1601. [DEBUG] PCI: 00:1b.0 init
  1602. [DEBUG] codec mask = 4
  1603. [DEBUG] HDA: Initializing codec #2
  1604. [DEBUG] HDA: codec viddid: 80862882
  1605. [DEBUG] HDA: verb loaded.
  1606. [DEBUG] PCI: 00:1b.0 init finished in 3 msecs
  1607. [DEBUG] PCI: 00:1c.0 init
  1608. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs
  1609. [DEBUG] PCI: 00:1d.0 init
  1610. [DEBUG] PCI: 00:1d.0: Disabling device: 1d.0
  1611. [DEBUG] Power management CAP offset 0x70.
  1612. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs
  1613. [DEBUG] PCI: 00:1e.0 init
  1614. [DEBUG] PCI: 00:1e.0 init finished in 0 msecs
  1615. [DEBUG] PCI: 00:1f.0 init
  1616. [DEBUG] Disabling slp_x stretching.
  1617. [DEBUG] PCI: 00:1f.0 init finished in 0 msecs
  1618. [DEBUG] PCI: 01:00.0 init
  1619. [DEBUG] PCI: 01:00.0 init finished in 0 msecs
  1620. [DEBUG] PNP: 00ff.0 init
  1621. [DEBUG] Google Chrome EC: Initializing
  1622. [DEBUG] Google Chrome EC: version:
  1623. [DEBUG] ro: swanky_v1.6.197-c5a86fe
  1624. [DEBUG] rw: swanky_v1.6.205-92b7845
  1625. [DEBUG] running image: 2
  1626. [DEBUG] PNP: 00ff.0 init finished in 2 msecs
  1627. [INFO ] Devices initialized
  1628. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 21 / 0 ms
  1629. [DEBUG] FMAP: area SMMSTORE found @ 5c0000 (262144 bytes)
  1630. [DEBUG] smm store: 4 # blocks with size 0x10000
  1631. [INFO ] SMMSTORE: Setting up SMI handler
  1632. [INFO ] Found TPM SLB9635 TT 1.2 by Infineon
  1633. [INFO ] TPM: Handle S3 resume.
  1634. [DEBUG] TPM: Resume
  1635. [DEBUG] TPM: command 0x99 returned 0x0
  1636. [INFO ] TPM: setup succeeded
  1637. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 5 / 0 ms
  1638. [INFO ] Finalize devices...
  1639. [INFO ] Devices finalized
  1640. [DEBUG] Trying to find the wakeup vector...
  1641. [DEBUG] Looking on 0x000f0000 for valid checksum
  1642. [DEBUG] Checksum 1 passed
  1643. [DEBUG] Checksum 2 passed all OK
  1644. [DEBUG] RSDP found at 0x000f0000
  1645. [DEBUG] RSDT found at 0x7af2a030 ends at 0x7af2a06c
  1646. [DEBUG] FADT found at 0x7af2e170
  1647. [DEBUG] FACS found at 0x7af2a240
  1648. [DEBUG] OS waking vector is 0x000981f0
  1649. [DEBUG] Applying perf/power settings.
  1650. [DEBUG] BS: BS_OS_RESUME entry times (exec / console): 1 / 0 ms
  1651.  
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