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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    07:27:40 01/12/2019
  6. -- Design Name:
  7. -- Module Name:    A1 - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity A1 is
  33.     Port ( Clk : in  STD_LOGIC;
  34.            x : in  STD_LOGIC;
  35.            T : in  STD_LOGIC;
  36.            R : in  STD_LOGIC;
  37.            z1 : out  STD_LOGIC;
  38.            z2 : out  STD_LOGIC;
  39.               wyQ1 : out  STD_LOGIC;
  40.               wyQ2 : out  STD_LOGIC);
  41. end A1;
  42.  
  43. architecture Behavioral of A1 is
  44. component divider is
  45.     Port ( Clk : in STD_LOGIC;
  46.             Clk_div : inout STD_LOGIC := '0');
  47. end component divider;
  48.  
  49. component impuls is
  50.     Port ( Clk_div, T : in STD_LOGIC;
  51.                 C : buffer STD_LOGIC);
  52. end component impuls;
  53.  
  54. component NAND4 is
  55.     Port (a,b,c,d : in STD_LOGIC:='1';
  56.             z : out STD_LOGIC);
  57. end component NAND4;
  58.  
  59. component FFD is
  60.     Port (D, C, R : in STD_LOGIC;
  61.             Q, nQ : out STD_LOGIC);
  62. end component FFD;
  63.  
  64. signal Clk_div,C, nx, Q1,Q2,nQ1,nQ2,v1,v2,v3,v4,v5,v6,v7,v8, D1,D2 : STD_LOGIC;
  65.  
  66. begin
  67.  
  68. ------------------------------------------ Divider, impuls, X
  69. c1: divider port map (Clk, Clk_div);
  70. c2: impuls port map (Clk_div, T, C);
  71. b0: NAND4 port map (a => x, z => nx);
  72.  
  73. ------------------------------------------ D1
  74. b1: NAND4 port map (nQ1, nQ2, nx, '1', v1);
  75. b2: NAND4 port map (nQ1, Q2, x, '1', v2);
  76. b3: NAND4 port map (Q1, nQ2, '1', '1', v3);
  77. b4: NAND4 port map (v1, v2, v3, '1', D1);
  78.  
  79. ------------------------------------------ D2
  80. b5: NAND4 port map (nQ2, x, '1', '1', v5);
  81. b6: NAND4 port map (Q1, nQ2, '1', '1', v6);
  82. b7: NAND4 port map (Q1, nx, '1', '1', v7);
  83. b8: NAND4 port map (v5, v6, v7, '1', D2);
  84.  
  85. ------------------------------------------ FFD
  86. p1: FFD port map ( D1, C, R, Q1, nQ1);
  87. p2: FFD port map ( D2, C, R, Q2, nQ2);
  88.  
  89. ------------------------------------------ output
  90. b9: NAND4 port map ( nQ1, Q2, '1', '1', z1);
  91. b10: NAND4 port map ( Q1, nQ2, '1', '1', z2);
  92.  
  93.  
  94. ------------------------------------------ state
  95. wyQ1 <= Q1;
  96. wyQ2 <= Q2;
  97.  
  98. end Behavioral;
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