----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    07:27:40 01/12/2019
-- Design Name:
-- Module Name:    A1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity A1 is
    Port ( Clk : in  STD_LOGIC;
           x : in  STD_LOGIC;
           T : in  STD_LOGIC;
           R : in  STD_LOGIC;
           z1 : out  STD_LOGIC;
           z2 : out  STD_LOGIC;
			  wyQ1 : out  STD_LOGIC;
			  wyQ2 : out  STD_LOGIC);
end A1;

architecture Behavioral of A1 is
component divider is
	Port ( Clk : in STD_LOGIC;
			Clk_div : inout STD_LOGIC := '0');
end component divider;

component impuls is
	Port ( Clk_div, T : in STD_LOGIC;
				C : buffer STD_LOGIC);
end component impuls;

component NAND4 is
	Port (a,b,c,d : in STD_LOGIC:='1';
			z : out STD_LOGIC);
end component NAND4;

component FFD is
	Port (D, C, R : in STD_LOGIC;
			Q, nQ : out STD_LOGIC);
end component FFD;

signal Clk_div,C, nx, Q1,Q2,nQ1,nQ2,v1,v2,v3,v4,v5,v6,v7,v8, D1,D2 : STD_LOGIC;

begin

------------------------------------------ Divider, impuls, X
c1: divider port map (Clk, Clk_div);
c2: impuls port map (Clk_div, T, C);
b0: NAND4 port map (a => x, z => nx);

------------------------------------------ D1
b1: NAND4 port map (nQ1, nQ2, nx, '1', v1);
b2: NAND4 port map (nQ1, Q2, x, '1', v2);
b3: NAND4 port map (Q1, nQ2, '1', '1', v3);
b4: NAND4 port map (v1, v2, v3, '1', D1);

------------------------------------------ D2
b5: NAND4 port map (nQ2, x, '1', '1', v5);
b6: NAND4 port map (Q1, nQ2, '1', '1', v6);
b7: NAND4 port map (Q1, nx, '1', '1', v7);
b8: NAND4 port map (v5, v6, v7, '1', D2);

------------------------------------------ FFD
p1: FFD port map ( D1, C, R, Q1, nQ1);
p2: FFD port map ( D2, C, R, Q2, nQ2);

------------------------------------------ output
b9: NAND4 port map ( nQ1, Q2, '1', '1', z1);
b10: NAND4 port map ( Q1, nQ2, '1', '1', z2);


------------------------------------------ state
wyQ1 <= Q1;
wyQ2 <= Q2;

end Behavioral;