Guest User

Untitled

a guest
Dec 2nd, 2013
72
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. Timing constraint: TS_rx_clk_in_n = PERIOD TIMEGRP "rx_clk_in_n" 246 MHz HIGH
  2. 50%;
  3. For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  4.  
  5. 72955 paths analyzed, 24062 endpoints analyzed, 67 failing endpoints
  6. 67 timing errors detected. (67 setup errors, 0 hold errors, 0 component switching limit errors)
  7. Minimum period is 4.750ns.
  8. --------------------------------------------------------------------------------
  9. Slack: -0.685ns (requirement - (data path - clock path skew + uncertainty))
  10. Source: axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram (RAM)
  11. Destination: axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42 (FF)
  12. Requirement: 4.065ns
  13. Data Path Delay: 4.323ns (Levels of Logic = 1)
  14. Clock Path Skew: -0.392ns (1.342 - 1.734)
  15. Source Clock: clk rising at 0.000ns
  16. Destination Clock: clk rising at 4.065ns
  17. Clock Uncertainty: 0.035ns
  18.  
  19. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  20. Total System Jitter (TSJ): 0.070ns
  21. Total Input Jitter (TIJ): 0.000ns
  22. Discrete Jitter (DJ): 0.000ns
  23. Phase Error (PE): 0.000ns
  24.  
  25. Maximum Data Path at Slow Process Corner: axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram to axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42
  26. Location Delay type Delay(ns) Physical Resource
  27. Logical Resource(s)
  28. ------------------------------------------------- -------------------
  29. RAMB36_X2Y20.DOBDO10 Trcko_DOB 2.454 axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram
  30. axi_dmac_1/axi_dmac_1/i_request_arb/i_fifo/Mram_ram
  31. SLICE_X32Y101.B4 net (fanout=1) 0.985 axi_dmac_1/axi_dmac_1/i_request_arb/dest_fifo_data<42>
  32. SLICE_X32Y101.BMUX Tilo 0.374 axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/bwd_data<43>
  33. axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/Mmux_bwd_data_s371
  34. SLICE_X32Y99.AX net (fanout=2) 0.494 axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/bwd_data_s<42>
  35. SLICE_X32Y99.CLK Tdick 0.016 axi_dmac_1_fifo_rd_dout<42>
  36. axi_dmac_1/axi_dmac_1/i_request_arb/i_dest_slice/fwd_data_42
  37. ------------------------------------------------- ---------------------------
  38. Total 4.323ns (2.844ns logic, 1.479ns route)
  39. (65.8% logic, 34.2% route)
RAW Paste Data