Manioc

impressora

Nov 23rd, 2018
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  1. // DESCRIPTION: Verilator: Systemverilog example module
  2. // with interface to switch buttons, LEDs, LCD and register display
  3.  
  4. parameter NINSTR_BITS = 32;
  5. parameter NBITS_TOP = 8, NREGS_TOP = 32;
  6. module top(input  logic clk_2,
  7.            input  logic [NBITS_TOP-1:0] SWI,
  8.            output logic [NBITS_TOP-1:0] LED,
  9.            output logic [NBITS_TOP-1:0] SEG,
  10.            output logic [NINSTR_BITS-1:0] lcd_instruction,
  11.            output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
  12.            output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
  13.              lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
  14.            output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);
  15.  
  16.  
  17.   logic [1:0] clk_1;
  18.   logic [1:0] tempo;
  19.   always_ff @(posedge clk_2) begin
  20.     clk_1 <= clk_1 + 1;
  21.   end
  22.  
  23.   enum logic [1:0] {
  24.     base,
  25.     copiando,
  26.     sem_papel,
  27.     error
  28.   } state;
  29.  
  30.   logic reset, copiar, papel, enrolado, tampa;
  31.   logic saida, entupida, falta, last;
  32.   logic [1:0] quantidade, cnt;
  33.   always_comb begin
  34.     reset <= SWI[7];
  35.     copiar <= SWI[0];
  36.     quantidade <= SWI[2:1];
  37.     papel <= SWI[4];
  38.     enrolado <= SWI[5];
  39.     tampa <= SWI[6];
  40.   end
  41.  
  42.   always_ff @(posedge clk_1[1] or posedge reset) begin
  43.     if(reset) begin
  44.       cnt <= 0;
  45.       falta <= 0;
  46.       entupida <= 0;
  47.       state <= base;
  48.       last <= 0;
  49.     end
  50.     else begin
  51.       unique case(state)
  52.         base:
  53.           if(copiar) begin
  54.             cnt <= 0;
  55.             saida <= 1;
  56.             state <= copiando;
  57.           end
  58.         copiando:
  59.           if(!papel) begin
  60.             saida <= 0;
  61.             falta <= 1;
  62.             state <= sem_papel;
  63.           end else if(enrolado) begin
  64.             saida <= 0;
  65.             entupida <= 1;
  66.             state <= error;
  67.           end else if(cnt == quantidade) begin
  68.             saida <= 0;
  69.             state <= base;
  70.           end else if(papel) begin
  71.             saida <= 1;
  72.             cnt <= cnt + 1;
  73.           end
  74.         sem_papel:
  75.           if(papel) begin
  76.             falta <= 0;
  77.             state <= copiando;  
  78.           end
  79.         error:
  80.           if(!tampa && last) begin
  81.             entupida <= 0;
  82.             last <= 0;
  83.             state <= copiando;
  84.           end else if(tampa) last <= 1;
  85.       endcase
  86.     end
  87.   end
  88.  
  89.   always_comb begin
  90.     LED[7] <= clk_1[1];
  91.     LED[0] <= saida;
  92.     LED[1] <= falta;
  93.     LED[2] <= entupida;
  94.   end
  95. endmodule
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