impressora

// DESCRIPTION: Verilator: Systemverilog example module
// with interface to switch buttons, LEDs, LCD and register display

parameter NINSTR_BITS = 32;
parameter NBITS_TOP = 8, NREGS_TOP = 32;
module top(input  logic clk_2,
           input  logic [NBITS_TOP-1:0] SWI,
           output logic [NBITS_TOP-1:0] LED,
           output logic [NBITS_TOP-1:0] SEG,
           output logic [NINSTR_BITS-1:0] lcd_instruction,
           output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
           output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
             lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
           output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);


  logic [1:0] clk_1;
  logic [1:0] tempo;
  always_ff @(posedge clk_2) begin
    clk_1 <= clk_1 + 1;
  end

  enum logic [1:0] {
    base,
    copiando,
    sem_papel,
    error
  } state;

  logic reset, copiar, papel, enrolado, tampa;
  logic saida, entupida, falta, last;
  logic [1:0] quantidade, cnt;
  always_comb begin
    reset <= SWI[7];
    copiar <= SWI[0];
    quantidade <= SWI[2:1];
    papel <= SWI[4];
    enrolado <= SWI[5];
    tampa <= SWI[6];
  end

  always_ff @(posedge clk_1[1] or posedge reset) begin
    if(reset) begin
      cnt <= 0;
      falta <= 0;
      entupida <= 0;
      state <= base;
      last <= 0;
    end
    else begin
      unique case(state)
        base:
          if(copiar) begin
            cnt <= 0;
            saida <= 1;
            state <= copiando;
          end
        copiando:
          if(!papel) begin
            saida <= 0;
            falta <= 1;
            state <= sem_papel;
          end else if(enrolado) begin
            saida <= 0;
            entupida <= 1;
            state <= error;
          end else if(cnt == quantidade) begin
            saida <= 0;
            state <= base;
          end else if(papel) begin
            saida <= 1;
            cnt <= cnt + 1;
          end
        sem_papel:
          if(papel) begin
            falta <= 0;
            state <= copiando;
          end
        error:
          if(!tampa && last) begin
            entupida <= 0;
            last <= 0;
            state <= copiando;
          end else if(tampa) last <= 1;
      endcase
    end
  end

  always_comb begin
    LED[7] <= clk_1[1];
    LED[0] <= saida;
    LED[1] <= falta;
    LED[2] <= entupida;
  end
endmodule