edited_morse

module morsecode(SW,LEDR,KEY,CLOCK_50);
    //SW[2:0] is char input;
    //KEY[1] display;
    //key[0] reset

    input [9:0] SW;
    input [3:0] KEY;
    output [9:0] LEDR;



    input CLOCK_50;
    reg [13:0] load_val;

    wire load_n, halfclk;

//
//  assign LEDR[9] = 1;

    ratedivider d0(.clk_in(CLOCK_50),.clk_out(halfclk));

    shifter s0(.load_val(load_val),.load_n(KEY[1]),.reset(KEY[0]),.out(LEDR[0]),.clk(halfclk));

    always @(*)
    begin
        case (SW[2:0])

            3'b000: load_val <= 14'b11010100000000;
            3'b001: load_val <= 14'b11110000000000;
            3'b010: load_val <= 14'b11010111000000;
            3'b011: load_val <= 14'b11010101110000;
            3'b100: load_val <= 14'b11011101110000;
            3'b101: load_val <= 14'b11110101011100;
            3'b110: load_val <= 14'b11110101110111;
            3'b111: load_val <= 14'b11110111010100;

        endcase
    end

endmodule

module shifter(load_val,load_n,reset,out,clk);
    input [13:0] load_val;
    input clk, load_n,reset;
    output out;
    reg out;
    reg [13:0] temp;
    always @(posedge clk or negedge load_n or negedge reset)

    begin
        if(reset == 0)
            temp <= 0;
        else if (load_n==0)
            temp <= load_val;
        else
            begin
                temp = temp <<1;
                out <= temp[13];
            end
    end
endmodule


module ratedivider0(clk_in,clk_out);
    input clk_in;
    output clk_out;
    reg clk_out;

    reg [24:0] count;
    always @(posedge clk_in)
    begin
        count <= count + 1;
        if(count == 25'b0101111101011110000011111)
            begin
                count<=0;
                clk_out <= !clk_out;
            end
    end
endmodule

module ratedivider(reset_n, speed,clk_in,clk_out);
    input [1:0] speed;
    input clk_in;
    output clk_out;

    input reset_n;
    reg [25:0] q;

    reg clk_out,enable;
    reg [25:0] d;

    reg temp;

    always @(posedge clk_in)
    begin
        if(reset_n == 1'b0)
            q<=0;
        else if (enable == 1'b1)
            begin
                if(q == d)
                    begin
                        q <= 26'b0;
                        temp = 1;
                    end
                else
                    begin
                        q <= q + 1'b1;
                        temp = 0;
                    end
            end
    end

    always @(*)
    begin
        case (speed)
            2'b00:
                begin
                    enable = 0;
                end
            2'b01:
                begin
                    enable = 1;
                    d <= 26'b10111110101111000001111111;
                end
            2'b10:
                begin
                    enable = 1;
                    d <= 26'b01011111010111100000111111;
                end
            2'b11:
                begin
                    enable = 1;
                    d <= 26'b00101111101011110000011111;
                end
        endcase
    end

    always @(*)
    begin
        if (enable==1)
            clk_out = temp;
        else
            clk_out = clk_in;
    end
endmodule