// file: adc_inputs.v
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`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "adc_inputs,selectio_wiz_v2_0,{component_name=adc_inputs,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=false,use_phase_detector=false,serialization_factor=4,enable_bitslip=false,enable_train=false,system_data_width=11,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=DIFF,clk_io_std=LVDS_25,clk_buf=BUFIO2,active_edge=BOTH_RISE_FALL,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=NOT_APP,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=NONE,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS18,v6_clk_sig_type=DIFF}" *)

module adc_inputs
   // width of the data for the system
 #(parameter sys_w = 11,
   // width of the data for the device
   parameter dev_w = 22)
 (
  // From the system into the device
  input  [sys_w-1:0] DATA_IN_FROM_PINS_P,
  input  [sys_w-1:0] DATA_IN_FROM_PINS_N,
  output [sys_w-1:0] DATA_IN_TO_DEVICE_A,
  output [sys_w-1:0] DATA_IN_TO_DEVICE_B,

  input              CLK_IN_P,      // Differential clock from IOB
  input              CLK_IN_N,
  output             CLK_OUT_A,
  output             CLK_OUT_B,
  input              CLK_RESET,
  input              IO_RESET);


  // Signal declarations
  ////------------------------------
  wire               clock_enable = 1'b1;

  // After the buffer
  wire   [sys_w-1:0] data_in_from_pins_int;
  // Between the delay and serdes
  wire [sys_w-1:0]  data_in_from_pins_delay;

  // Create the clock logic
  IBUFGDS
    #(.IOSTANDARD ("LVDS_25"))
   ibufds_clk_inst
     (.I          (CLK_IN_P),
      .IB         (CLK_IN_N),
      .O          (clk_in_int));

  // Set up the clock for use in the serdes
  BUFIO2 #(
      .DIVIDE_BYPASS ("FALSE"),
      .I_INVERT      ("FALSE"),
      .USE_DOUBLER   ("FALSE"),
      .DIVIDE        (1))
   bufio2_inst
     (.DIVCLK       (clk_div),
      .IOCLK        (clk_in_int_buf),
      .SERDESSTROBE (),
      .I            (clk_in_int)
   );

  // also generated the inverted clock
  BUFIO2
    #(.DIVIDE_BYPASS ("FALSE"),
      .I_INVERT      ("TRUE"),
      .USE_DOUBLER   ("FALSE"),
      .DIVIDE        (1))
   bufio2_inv_inst
     (.DIVCLK        (),
      .IOCLK        (clk_in_int_inv),
      .SERDESSTROBE (),
      .I            (clk_in_int));


   // Buffer up the "divided" copied version of the input clock
   BUFG clkout_buf_inst
    (.O (CLK_OUT),
     .I (clk_div));

  // We have multiple bits- step over every bit, instantiating the required elements
  genvar pin_count;
  generate for (pin_count = 0; pin_count < sys_w; pin_count = pin_count + 1) begin: pins

    // Instantiate the buffers
    ////------------------------------
    // Instantiate a buffer for every bit of the data bus
    IBUFDS
      #(.DIFF_TERM  ("FALSE"),             // Differential termination
        .IOSTANDARD ("LVDS_25"))
     ibufds_inst
       (.I          (DATA_IN_FROM_PINS_P  [pin_count]),
        .IB         (DATA_IN_FROM_PINS_N  [pin_count]),
        .O          (data_in_from_pins_int[pin_count]));


    // Pass through the delay
    ////-------------------------------
   assign data_in_from_pins_delay[pin_count] = data_in_from_pins_int[pin_count];


    // Connect the delayed data to the fabric
    ////--------------------------------------
   // DDR register instantation
    IDDR2
     #(.DDR_ALIGNMENT  ("NONE"),
       .INIT_Q0        (1'b0),
       .INIT_Q1        (1'b0),
       .SRTYPE         ("ASYNC"))
     iddr2_inst
      (.Q0             (DATA_IN_TO_DEVICE_A[pin_count]),
       .Q1             (DATA_IN_TO_DEVICE_B[pin_count]),
       .C0             (clk_in_int_buf),
       .C1             (clk_in_int_inv),
       .CE             (clock_enable),
       .D              (data_in_from_pins_delay[pin_count]),
       .R              (IO_RESET),
       .S              (1'b0));

  end
  endgenerate



endmodule