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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 05/06/2022 07:53:46 PM
- // Design Name:
- // Module Name: cfo_memory
- // Project Name:
- // Target Devices:
- // Tool Versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module cfo_memory #(parameter DATA_WIDTH = 16)
- (
- input i_clk,
- input i_EN,
- input i_rstn,
- input [DATA_WIDTH-1:0] i_I,
- input [DATA_WIDTH-1:0] i_Q,
- output reg [DATA_WIDTH-1:0] o_I,
- output reg [DATA_WIDTH-1:0] o_Q,
- output reg o_valid
- );
- reg [DATA_WIDTH-1:0] r_I [DATA_WIDTH-1:0];
- reg [DATA_WIDTH-1:0] r_Q [DATA_WIDTH-1:0];
- reg [3:0] r_inputAddress;
- reg [3:0] r_outputAddress;
- reg [3:0] r_delayedAddress;
- reg [5:0] r_validCounter;
- reg [5:0] r_validEst;
- reg [1:0] r_flag;
- reg [1:0] r_flagEst;
- always@(posedge i_clk, negedge i_rstn)
- begin
- if(~i_rstn)
- begin
- r_inputAddress <= 4'd0;
- r_delayedAddress <= 4'd0;
- r_validCounter <= 6'd0;
- r_flag <= 2'b00;
- end
- else if(i_EN)
- begin
- r_inputAddress <= r_inputAddress+1;
- r_I[r_inputAddress] <= i_I;
- r_Q[r_inputAddress] <= i_Q;
- r_delayedAddress <= r_inputAddress;
- r_validCounter <= r_validEst;
- r_flag <= r_flagEst;
- end
- end
- always@(*)
- begin
- if(r_validCounter == 37)
- begin
- r_validEst = 6'd0;
- end
- else if(r_flag[0] == 1'd1)
- begin
- r_validEst = r_validCounter + 1;
- end
- else
- begin
- r_validEst = r_validCounter;
- end
- end
- always@(*)
- begin
- if(r_validCounter == 37)
- begin
- r_flagEst = 2'b00;
- end
- else
- begin
- r_flagEst = r_flag;
- end
- if(r_delayedAddress == 4'd12)
- begin
- r_flagEst = 2'b01;
- end
- else
- begin
- if(r_flag[0] == 1'b1)
- begin
- r_flagEst = 2'b11;
- end
- else
- begin
- r_flagEst = 2'b00;
- end
- end
- end
- always@(posedge i_clk, negedge i_rstn)
- begin
- if(~i_rstn)
- begin
- r_outputAddress <= 4'b0000;
- end
- else if(~i_EN && r_delayedAddress == 15)
- begin
- r_outputAddress <= r_outputAddress+1;
- o_I <= r_I[r_outputAddress];
- o_Q <= r_Q[r_outputAddress];
- end
- end
- always@(posedge i_clk, negedge i_rstn)
- begin
- if(~i_rstn)
- begin
- o_valid <= 1'b0;
- end
- else if(r_flag[0] == 1'b1 && r_validCounter == 6'd1)
- begin
- o_valid <= 1'b1;
- end
- else
- begin
- o_valid <= 1'b0;
- end
- end
- endmodule
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