module functionGenerator(Clk,data_out, freq, reg0, clk_out);
//declare input and output
    input Clk;
    output [9:0] data_out;
    output reg clk_out;
    input [3:0] reg0;
    reg [31:0] constantNumber;
    reg [9:0] sine [0:99];
    integer i;
    reg [9:0] data_out;
    reg [31:0] count;
//Initialize the sine rom with samples.
    initial begin
        i = 0;
        sine[0] = 0;        sine[1] = 10;        sine[2] = 20;        sine[3] = 29;        sine[4] = 39;
        sine[5] = 48;       sine[6] = 58;        sine[7] = 67;        sine[8] = 75;        sine[9] = 84;
        sine[10] = 92;      sine[11] = 100;      sine[12] = 107;      sine[13] = 114;      sine[14] = 120;
        sine[15] = 126;     sine[16] = 132;      sine[17] = 137;      sine[18] = 141;      sine[19] = 145;
        sine[20] = 149;     sine[21] = 151;      sine[22] = 153;      sine[23] = 155;      sine[24] = 156;
        sine[25] = 156;

    end


    always @ (reg0)
    begin
        if(reg0 == 4'b0000)
            constantNumber = 50000000;
        else if(reg0 == 4'b0001)
            constantNumber = 100000000;
        else if(reg0 == 4'b0010)
            constantNumber = 50000000;
        else if(reg0 == 4'b0100)
            constantNumber = 25000000;
        else if(reg0 == 4'b1000)
            constantNumber = 12500000;
        else
            constantNumber = 50000000;
    end

    always @ (posedge(Clk))
    begin
        if (count == constantNumber - 1)
            begin
            count <= 32'b0;
            end
        else
            begin
            count <= count + 1;
            end
    end

    always @ (posedge(Clk))
    begin
        if (count == constantNumber - 1)
            clk_out <= ~clk_out;
        else
            clk_out <= clk_out;
    end

    //At every positive edge of the clock, output a sine wave sample.
    always@ (clk_out)
        begin
            if ( i < 25 )
               data_out = sine[i];
            else if ( i < 50 )
               data_out = sine[50 - i];
            else if  ( i < 75 )
               data_out = - sine[i - 50];
            else
               data_out = - sine[100 - i];
            i = i+ 1;
            if(i == 100)
                i = 0;
    end
endmodule

module functionGeneratror_tb();

    // Inputs
    reg Clk;
    reg reg0;
    wire clk_out;
    // Outputs
    wire [9:0] data_out;

    // Instantiate the Unit Under Test (UUT)
    functionGenerator uut (
        .Clk(Clk),
        .data_out(data_out),
        .reg0(reg0),
        .clk_out(clk_out)

    );

    //Generate a clock with 10 ns clock period.
    initial
    begin
    Clk = 0;
    reg0 = 4'b0000;
    end
    always #5 Clk = ~Clk;

endmodule