module ezhik_summator (
               // inputs:
                address,
                chipselect,
                clk,
                reset_n,
                write_n,
                writedata,

               // outputs:
                readdata
             )
;

  output  [ 31: 0] readdata;
  input   [  2: 0] address;
  input            chipselect;
  input            clk;
  input            reset_n;
  input            write_n;
  input   [ 31: 0] writedata;

  wire             clk_en;
  reg     [ 31: 0] register1;
  reg     [ 31: 0] register2;
  reg     [ 31: 0] summ;
  wire    [ 31: 0] out_port;
  wire    [ 31: 0] read_mux_out;
  wire    [ 31: 0] readdata;
  assign clk_en = 1;
  //s1, which is an e_avalon_slave
  assign read_mux_out = {32 {(address == 0)}} & summ;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
    begin
          register1 <= 0;
          register2 <= 0;
    end
      else if (chipselect && ~write_n && (address == 1))
    begin
          register1 <= writedata[31 : 0];
        end
      else if (chipselect && ~write_n && (address == 2))
    begin
          register2 <= writedata[31 : 0];
    end
    summ <= register1 + register2;
    end


  assign readdata = read_mux_out;

endmodule